Meetings & Events

spring 1998 logo1998 MRS Spring Meeting & Exhibit

April 13 - 17, 1998 | San Francisco
Meeting Chairs: John A. Emerson, Ronald Gibala, Caroline A. Ross, Leo J. Schowalter









Symposium I—Advanced Interconnects and Contact Materials and Processes for Future ICs

Chairs

Moshe Eizenberg 
Dept of Materials Engr 
Technion-Israel Inst of Tech 
Haifa, 32000 ISRAEL 
972-4-8294585

David Fraser
Thin-Film Research
Intel Corp
Santa Clara, CA 95052-8119
408-765-2926

Roland Madar 
ENSPG Dept of MS&E
Inst Natl Polytechnique de Grenoble 
St. Martin d'Heres, 38402 FRANCE 
33-4-76-82-63-30

Shyam Murarka
Rensselaer Polytechnic Inst
CIE CII 6015
Troy, NY 12180-3590
518-276-2978

Raymond Tung 
Bell Labs, Lucent Technologies 
Room 1T-102 
Murray Hill, NJ 07974-0636 
908-582-6895 


Symposium Support 
*Bell Laboratories, Lucent Technologies 
*Intel Corporation 
*Novellus Systems, Inc. 
*Strem Chemicals, Inc. 
*Texas Instruments, Inc. 
*Watkins Johnson Company 

1998 Spring Exhibitor 

Proceedings published as Volume 514 
of the Materials Research Society 
Symposium Proceedings Series.
 


* Invited paper

SESSION I1: INTERCONNECT FRONTIERS - I 
Chairs: Moshe Eizenberg and David B. Fraser 
Monday Morning, April 13, 1998 
Salon 7
8:00 AM *I1.1 
INTERCONNECTION LIMITS ON XXI CENTURY GIGASCALE INTEGRATION (GSI). James D. Meindl, Georgia Institute of Technology, Electrical and Computer Engineering, Atlanta, GA. 

What are the critical limits that are most likely to detennine how many billions of transistors we will manufacture in commercially viable silicon chips in the early 21st century? For nearly four decades, silicon microelectronics has progressed at an unmatched exponential pace in both performance and productivity. The switching energy or power-delay product of a binary transition has been reduced by about five decades, the number of transistors per chip has been increased by approximately eight decades and the number of ``interconnect elements'' per chip has increased by over nine decades, while the price range of a chip has remained nearly constant. The National Technology Roadmap for Semiconductors projects a 64 billion bit DRAM chip by 2010. Perhaps the most compelling question confronting the surging $150 billion world-wide semiconductor industry is, ``How much further will the laws of physics (and econornics) enable this progress to continue?'' My current view is that early 21st century opportunities for GSI will be governed by a hierarchy of theoretical and practical limits whose five levels can be codified as: 1) fundamental, 2) material, 3) device, 4) circuit and 5) system. In this discussion I intend to review recent enhancements of this hierarchy and identify those critical limits-largely imposed by interconnects-that appear to present the most formidable challenges to continued progress of GSI. 

8:45 AM *I1.2 
POWER SUPPLY DISTRIBUTION AND OTHER WIRING ISSUES FOR DEEP SUB-MICRON ICs. W.T. Lynch, Semiconductor Research Corporation, Research Triangle Park, NC; L.A. Arledge, Texas Instruments. 

The ``Interconnect Problem'' has many components. These include; RC delays: introduction of new materials with associated issues of reliability and process/equipment development; yield loss in the BEOL; TCAD modeling of the individual processes; process parameter spread; electrical characterization and predictive circuit/system design; signal integrity and I/O pad interfaces. This presentation addresses the issues of scaled performance, power supply (PS) distribution from the pads to the power distribution feeders (pdf), and optimization of the wiring hierarchy. The present trends point toward an increasing number of wiring levels, with expanding hierarchical ratios of the dimensions and areas ot the ectomorphic (uppermost level) wiring to the ectomorphic (lowest level) wiring. RLCLL2 issues must be understood in terms of total scalling. The predicted area ratio for the minimum ectomorphic wire to the minimum ectomorphic wire at the 50 nm technology node is over 500. When scaled dimensions of transistor span (rather than metric dimensions) are used. The RC scaling of the ecto- interconnect is keeping pace with the W/L MOSFET scalling. Endo- wiring, on the other hand, should be scaled with chip dimension, and these global wires the only minimum relief that is associated with the replacement of Al/SiO2 with Cu/Low K. Semi-global meso- wiring is more likely to be associated with Reni's rules for an increasing number of gate blocks. The fundamental issue is that the clock frequencies are scaling higher at the same or higher rate as the transistors are scaling down, and this requirement can only be met by increased ``cleverness,'' more detailed predictive modeling, and improved architectures. The progression of the power supply paths is tracked from the pads PS pads through the pad eacape paths and the hierarchical wiring levels to the lowest level pdf. The analysis points to similar issues and approaches for clocks and signal paths. Dependencies and analyses associated with I/O pad size and spacing, PS gridding at the ecto- and meso- levels, isolated (unlinked) pdf, resistances, and layout are presented. Gridding is critical at the endo- level in order to provide equipotontial planes than can service the transistors directly below without harmful lateral (and variable) IR spreads. The total metallization area required solely for power supply distribution will become greater than three equivalent metal levels. Clock distribution issues will be similar to those for power, but with a lower density requirement. Finally, a top level approach is presented for analyzing the interconnect performance as set by its RLCLL2 limitations. The initial goal is to separate the reality of the ``problem'' from the exaggerated worst case scenarios. The ultimate goal is to have an optimized distribution of wiring levels, wiring sizes, and I/O pad sizes consistent with the available technology. Fundamental approaches exist, based on past generation prototypical wiring histograms, to provide predictive designs for meeting intrinsic delay requirements. There are improvements that could be made in the presently available histograms. 

9:30 AM *I1.3 
MULTILEVEL INTERCONNECTION TECHNOLOGIES AND FUTURE REQUIREMENTS FOR LOGIC APPLICATIONS. Michel Brillouët, France Telecom CNET, Centre Commun CNET SGS-Thomson, Crolles, FRANCE. 

The logic ICs are more and more dominated by the interconnection system, whose development is targeting an higher packing density and increased performances. The density of the interconnects is obtained by shrinking the feature sizes and by increasing the number of metal layers. However the limit of this approach should be reached early in the next century. At the same time, the optimisation of the interconnect system is driven by higher frequencies of the signals, reduced power consumption of the product and reduction of the parasitic effects (cross-talk and IR drop). While the semiconductor industry was able to stay for a long time with the classical Al/SiO2 system, there is a growing trend to move to new interconnect materials. For most devices, the reduction of metal line capacitance is essential at a wiring pitch of less than 1m. With the increased integration density, and thus the resulting higher aspect ratios, the use of a SiO2 IMD with constant thickness is more and more difficult and costly. Advanced materials are expected to lower the dielectric constant around 2 to 3. However no clear choice in the material emerges and the integration of theses materials is complex. The resistance of the conducting line can be a concern. In order to deal with conflicting requirements, a differentiated approach is usually taken. At the transistor interconnect level, TiSi2 salicide remains the mainstream interconnect for logic applications. For local or short range interconnect, CVD W can be used, taking advantage of its good coverage and extremely high resistance to electromigration. The intermediate metal levels (presently Al, later dual Damascene Cu) have the most stringent requirements: low resistance in order to connect large blocks, tight pitch in order to provide a good integration density and reduced cross-talk. The top interconnect levels are used for power and clock distribution and bonding. The pitch can be relaxed while sheet resistance is of prime importance. The contact and via resistances become a growing concern in deep submicron multilevel technologies, where they are a significant fraction of the total line resistance. Owing to its filling capability and high reliability, CVD W is the present material of choice in order to fill the contacts with high aspect ratio. At the via level, plugs are targeting a low via resistance, while being formed at low temperature (esp. with low k dielectrics) and providing a zero-overlap capability. Whatever the plug material (W, Al or Cu), the liner (usually Ti/TiN) becomes a limiting factor, as its contribution to the overall contact or via resistance is increasing. Reliability is a well known problem in the interconnect systems: hillocks, electromigration, stress voiding in Al lines were overcome by adding some complexity in the process. In addition to that, there is still some discussion on the criteria used for a reliable interconnect. Manufacturability of the interconnect system is a great concern for the future products: improving the defectivity level of the metallisation is more and more critical, as more than half the process steps are now involved in the fabrication of the interconnection levels. eyond these technological improvements, a breakthrough is needed: improvements through the introduction of new materials are limited and new interconnect concepts are necessary. 

10:45 AM *I1.4 
COPPER ULSI ITERCONNECT TECHNOLOGY. D. Edelstein, IBM T.J. Watson Research Center, Yorktown Heights, NY. 

Recently IBM announced the first implementation of full copper ULSI wiring in a CMOS technology, to be manufactured on its high-performance 0.22 um CMOS products this year. Features of this technology will be presented, as well as functional verification on CMOS chips. To reach this level, extensive yield, reliability, and stress testing had to be done on test and product-like chips, including those packaged into product modules. Data will be presented from all aspects of this testing, ranging from experiments designed to promote Cu contamination of the MOS devices, to temperature/humidity/bias stressing of assembled functional modules. The results in all areas are shown to be equal to or better than standards set by our current Al(Cu)/W-stud technology. This demonstrates that the potential problems associated with copper wiring that have long been discussed can be overcome. 

11:30 AM *I1.5 
INTEGRATION OF MULTI-LEVEL COPPER METALLIZATION INTO A HIGH PERFORMANCE SUB-0.25m TECHNOLOGY. R. Venkatraman, G. Hamilton, A. Jain, D. Denning, C. Simpson, J. Mendonca, B. Rogers, L. Frisa, T.P. Ong, M. Herrick, V. Kaushik, R. Gregory, E. Apen, M. Angyal, S. Filipiak, P. Crabtree, T. Sparks, J. Farkas, D. Watts, S. Anderson, C. Capasso, D. Coronell, R. Islam, V. Misra, B. Smith, R. Fiordalice, H. Kawasaki, J. Klein, S. Venkatesan, E. Weitzman, Motorola Inc., Advanced Products Research and Development Laboratory, Austin, TX. 

high performance sub-0.25m CMOS technology has been developed with six levels of copper metallization. Copper offers the possibility of superior electromigration resistance over conventional Al(Cu) alloys and due to its lower resistivity, minimizes wiring induced RC delays. The integration of copper demands the use of newer materials and processes, most notably the use of diffusion barriers which have to satisfy requirements of barrier characteristics, adhesion, low resistivity, step coverage, overall integratability and manufacturability. Copper diffuses into commonly used dielectric materials and can affect ``front-end'' device characteristics as well as intra-level electrical leakage under elevated temperatures and electrical bias. Three barriers, TiN, TaN and TaSiN have been successfully integrated into interconnect structures. Details of process development, film properties and microstructure and electrical results on structures integrated using these materials will be reported. The barrier properties of the interconnect can be enhanced by the use of a ``hybrid barrier'' wherein a thin Si-O N barrier is formed below the surface of SiO2 by nitridation of the exposed SiO2 layer. The impact of copper on transistor and diode properties was also evaluated by processing wafers with Cu and Al(Cu) metallizations and measuring the diode characteristics at the end of processing and after a separate annealing step. Dual inlaid technology wherein the via and interconnect patterns are etched into the dielectric was used to integrate the copper. The planarity of the structure after chemical mechanical polishing (CMP) of copper is crucial to achieving the required device paramaters such as line resistance and interlevel capacitance and to integrate multiple levels of copper. An optimized CMP process was developed which minimizes the planarity across a wide array of line widths and layout topology. Electromigration testing of titanium nitride cladded copper was conducted and showed a 10X improvement in mean time to failure over conventional Al(Cu) metallurgy. 

SESSION I2: INTERCONNECT FRONTIERS - II 
Chairs: Roland Madar and Shyam P. Murarka 
Monday Afternoon, April 13, 1998 
Salon 7
1:30 PM *I2.1 
SCALING AND INTEGRATION OF HIGH PERFORMANCE INTERCONNECTS. Simon Yang, Portland Technology Development, Intel Corporation, Hillsboro, OR. 

The three key requirements for an interconnect system are: sufficient wiring capability to support signal routing, sufficient current carrying capability to support chip power density, and RC delay not to limit chip clock frequency. However, as has been highlighted in many recent publications, interconnect RC was insignificant (as compared to front-end gate delays) until recently when the Si technology has been scaled to deep sub-micron dimensions. Unlike front-end transistor scaling where dimension shrink will generally lead to gate delay reduction, continuing interconnect pitch scaling (which will be shown as a requirement for maintaining sufficient routing capability) will generally lead to RC delay increase. This led to the well known ``interconnect crisis'' for the world wide semiconductor industry. In order to meet the first requirement for an interconnect system - sufficient routing capability, analyses based on the Rent's rule showed that scaling of interconnect pitch to match the pace of transistor scaling is likely to be insufficient. A moderate increase of interconnect layers will also be required. Scaling analysis for power density indicated that current per unit line width has to be in general maintained. This implies that, for common conductive material, the conductive layer thickness will tend to stay constant. For wires which are not limited by RC, minimum line/space aspect ratio is expected to constantly increase with technology generations. Assuming that interconnect delay reduction has to match the transistor delay reduction in the near future, it can be shown that the number of interconnect layers has to increase very rapidly after the 0.18um technology generation. Introducing Cu and low k dielectric will only delay this rapid increase by one generation. Major process integration options for limiting RC delay impact will be discussed. A project of interconnect architectures and key process challenges for next two technology generations (0.18um and 0.13um) will be presented at the conclusion. 

2:15 PM *I2.2 
SUB-QUARTER MICRON METALLIZATION USING IONIZED METAL PLASMA (IMP) TECHNOLOGY. Fusen Chen, Zheng Xu, and Ashok Sinha Metal Deposition Product Business Group, Applied Materials, Inc., Santa Clara, CA. 

As the feature size of VLSIs shrinks below quarter-micron, the conventional metallization techniques face substantial challenges in liner / barrier formation, contact hole filling and total thermal budget management. In the sub-quarter micron VLSIs, the aspect ratio of contacts / vias is close to 10. The traditional collimation and long throw technology become obsolete due to poor bottom coverage. Moreover, the time delay in the multilayer interconnects becomes increasingly significant, comparing to the channel transition time delay. Multilayer metals up to 10 has been explored together with the integration of low-k dielectric IMD in order to reduce the RC delay. Low thermal budget becomes a basic requirement for increased metal layers and low-k IMD process integration. It is evident that the traditional magnetron sputtering Ti/TiN, CVD tungsten plugs, and aluminum interconnects scheme can not meet the needs of ultra-high speed complex logic and high density memory devices. The ionized metal plasma (IMP) technology provides a high directional sputtering technology for deposition into high aspect ratio contact holes. The IMP source involves the use of a inductively coupled plasma between the magnetron source and the substrate in order to efficiently ionize the sputtered atoms which then can be accelerated to the substrate through the use of a small DC or RF bias. Besides high bottom coverage, the energetic Ti+ bombardment in IMP Ti deposition may induce Ti/Si reaction at relatively low temperature, and Ti silicide may be instantly formed even without rapid thermal annealing. The another unique advantage in IMP TiN process is that the surface morphology and stochiometry are flexibly tunable through process parameters, and this enables the aluminum filling at relative low temperature. In this work, Ionized Metal Plasma (IMP) technology has been developed for liners and wetting layer deposition of sub-quarter-micron devices. Numerical modeling showed the unique advantages of IMP source over ECR source and long throw sputtering in enhancing bottom coverage . TiN bottom coverage up to 70% were demonstrated. The deposition rate, uniformity, bottom coverage and film stress were optimized by tuning RF and DC powers, process pressure and bias power. The feasibility of forming in situ TiSi2 was verified. The TiN film microstructure such as crystal orientation and grain size was tunable through process parameters. The combination of IMP TiNx (x<1) film and ALPS source provided superb wetting layer for low temperature aluminum plug process. Numerous electrical test data showed lower via resistance of IMP Ti/TiN deposition, comparing to other technology. The extendability of IMP technology into Ta, TaN and Cu deposition was also demonstrated. 

3:15 PM *I2.3 
BARRIERS FOR Cu INTERCONNECTIONS. S. Simon Wong, Changsup Ryu, Haeburn Lee, Kee-Won Kwon, Center for Integrated Systems, Stanford University, Stanford, CA. 

Interconnection has been, is, and will continue to be a key factor that limits the performance and cost of integrated circuits. As technology is scaled below a quarter-micron, the problems associated with interconnection are ever more pressing and could potentially become the roadblock to progress. Fundamental changes in the interconnection materials are needed. Low resistivity metal, namely Cu, is expected to be introduced into manufacturing in the near future. The integration of Cu interconnections will require sophisticated structures to prevent Cu from coming into contact with devices. This presentation will describe the interactions between Cu and various barrier metals. 

4:00 PM *I2.4 
MATERIALS AND DEVICES FOR SILICON ON-CHIP OPTICAL INTERCONNECT. J.M. Ballantyne, Cornell University, School of Electrical Engineering, Ithaca, NY. review progress on growth of direct-bandgap GalnP/GaP and other materials for light emitters monolithic on Silicon, and discuss design, fabrication, process compatibility, and performance issues for optical emitters and detectors made in these materials. 

SESSION I3: ALUMINUM INTERCONNECTS 
Chairs: Shyam P. Murarka and Hiroshi Onoda 
Tuesday Morning, April 14, 1998 
Salon 11/12
8:00 AM *I3.1 
TEXTURE CONTROL AND ELECTROMIGRATION PERFORAMNCE IN Al-BASED AND Cu-BASED LAYERED INTERCONNECTS. H. Onoda, M. Kageyama, K. Abe and Y. Harada, VLSI R&D Center, Oki Electric Industry Co., Ltd., Tokyo, JAPAN. 

Electromigration is one of the most serious issues in LSI interconnects even in the process trend changes from Al-layered interconnects to Cu-damascene interconnects for sub-quarter micron devices. Crystal texture of the metal film is an important parameter which affects electromigration performance, and now it would be controllable not only in Al layered metallization but also in Cu metallization. Al film texture can be controlled by the undelayer metal. The texture of Al-alloy orients to <111> when it is sputter deposited on TiN(111) or Ti(002), because the atom arrangement of Al(111)is almost the same as that of TiN(111) and Ti(002) within 3% of lattice mismatch. Partial epitaxy can be observed at the interface between Al-alloy and TiN, while the grain size of underlayer TiN is much smaller than upper Al-alloy. When Al films are deposited on Ti, they react and the compound would be formed at interface, but this alloying does not prevent partial epitaxy in Al/Ti structure, because the atom arrangement of Al3Ti(112) is almost the same as that of Al(111). The stronger oriented Al-alloy shows longer electromigration lifetime in these system, and this phenomenon is observed not only in monolayer lines, but also in multilayered lines with W-stud vias. The similar effect was also observed in sputter deposited Cu on TiN underlayer. It was revealed that Cu<111> orientation is promoted by TiN<111> in spite of the lattice mismatch of 15%. In order to study the probability of epitaxial growth, TiN, which was sputter deposited on Cu, was investigated by TEM and electron beam diffraction. The TiN grains are much smaller than Cu grains, however, every TiN grains shows fully epitaxial growth on the Cu. The large lattice mismatch would be released at TiN grain boundaries. This result indicates that partial epitaxy which controls Cu texture occurs in Cu/TiN system. Electromigration performance of damasecne-Cu interconnects formed by sputter reflow method was also improved with controlling the film texture to <111>. Since the texture of Cu film deposited by electro-plating was controlled by sputter deposited seed layer, the texture control would be effective for dual-damascene for future devices. 

8:30 AM *I3.2 
Al DUAL DAMASCENE TECHNOLOGY FOR MULTILEVEL INTERCONNECTS. Kuniko Kikuta, NEC Corp., ULSI Device Development Labs., Kanagawa, JAPAN. 

As a device dimension decreases, number of metal layer increases and metal pitch decreases. Al dual damascene has been known to achieve low fabrication cost because the fabrication processes can simplify by using Al sputter-filling technology and Al CMP. However, from the electrical characteristics and reliability point of view, it was not clear if the Al dual damascene is suitable for fine pitch metallization. In this paper, we compared via characteristics among W-plug, Al-plug and Al dual damascene for multilevel interconnects. We investigated the via resistance and electromigration characteristics. Al dual damascene was formed by Al hot sputtering to fill via and trench, and by sequent Al-CMP. The electromigration lifetime for via holes with misalignment between the 1st via and 2nd Al for dual damascene is larger than that for conventional Al plug. On the dual damascene structure, via holes are opened first, then 2nd metal trench are paterned. Even misalignment between the 1st via and the 2nd Al occurs, contact area for dual damascene become large because of making contact at both of the via top and the side wall of the 2nd Al. The electromigration lifetime is long for dual damascene with misalignment, in compared with that for Al plug and W plug with misalignment. Via resistance for dual damascene is almost the same as the via resistance for Al plug, which is lower than W plug. Via yield for dual damascene with misalignment is better than that for Al plug and W plug In conclusion, we compared W-plug, A plug and Al dual damascene for multilevel interconnects. Al dual damascene was found to be durable and reliable in structure and process against misalignment in terms of electromigration lifetime and via resistance, as well as yield. Al dual damascene is the most promising technology for fine-pitch metallization. 

9:00 AM I3.3 
CRYSTALLOGRAPHIC TEXTURE AND PHASE FORMATION IN BLANKET Ti/TiN/AlCu FILMS. P.W. DeHaven,IBM Analytical Services, Hopewell Junction, NY; L.A. Clevenger*, F.R. Schnabe.**, S. J. Weber**, and R.C. Iggulden*, DRAM Development Alliance, Hopewell Junction, NY, *IBM MIcroelectronics, **Siemens Microelectronics; K.P. Rodbell, IBM Research Division, Yorktown Heights, NY. 

Interconnection metallization uses film stacks, often composed of thin (<10 nm) Ti, TiN, or Ti/TiN underlayer(s) with a thick (200 - 1000 nm) Al-alloy film deposited on top. The texture or preferred orientation in such film stacks has important implications for both processing and reliability. Earlier studies1 have demonstrated the importance of the underlayers on Al texture; however to date no systematic work has been done on the effect of processing conditions on underlayer texture. This study examines the effect of deposition parameters on the underlayer texture development as well as the effect of this underlayer texture on subsequently deposited Al-alloy films. Fiber plots were obtained for Ti<002> and <101> and Al <111> reflections for a series of 20 nm Ti/ 10 nm TiN/ 400 nm AlCu films using both a conventional Siemens D500 diffractometer with a pole figure attachment and a Siemens HI-STAR Area Detector system using Cu radiation from a rotating anode source. Because of overlap between the Al <111> and Ti <101> reflections, the Al was removed with a subtractive etch. In this way both the Al and underlayer film textures could be quantified. It was found that the Ti and Al-alloy film textures vary depending on the deposition temperature, deposition method and final film thickness. For example, an increase in the substrate temperature from 300º to 500C caused the Ti film texture to change from <002> to <101>. Additionally, switching the TiN deposition process from physical vapor deposition (PVD) sputtering to chemical vapor deposition (CVD) in a Ti/TiN/AlCu film stack caused a degradation in the AlCu <111> texture. 

9:15 AM I3.4 
MICROSTRUCTURE AND LIFETIME STUDY OF ALUMINUM/YTTRIUM LINES. K.F. Poole*, R. Singh**, L. Vedula* and V.S. Nimmagadda*. *Department of Electrical and Computer Engineering, **Department of Electrical and Computer Engineering, and Materials Science and Engineering Program, Clemson University, Clemson, SC. 

We have studied the influence of adding yttrium to aluminum interconnects. Al/Y(0.1wt) metal films were deposited on Si/SiO2 substrates by D.C magnetron sputtering. Though the resistivity value of as-deposited metal films was much higher than that of aluminum, it reduced significantly after annealing. Transmission electron microscopy was used to examine the microstructure. The addition of yttrium contained the grain growth of aluminum during the annealing process. As a result metal films with finer and more uniform grain sizes are obtained. Lifetime testing measurements were done on these samples at 0.1 MA/cm2 and 150 oC. This paper will discuss the improvement in lifetime and its correlation with the microstructure of the metal lines obtained by the addition of yttrium. 

9:30 AM I3.5 
INVESTIGATION OF THE HOMOVALENT IMPURITY IN ALUMINUM TO FORM ALLOYS WITH ENHANCED RELIABILITY. Sridhar K. Kailasam, S.P. Murarka, M.E. Glicksman, Center for Advanced Interconnect Science and Technology, Rensselaer Polytechnic Institute, Troy, NY. 

One of the chief concerns with the metallization in the ULSI era is the issue of electromigration(EM) in the interconnects. The addition of solute elements to aluminum interconnects often leads to improvement in the resistance to electromigration failure. Our research has been focused on studies of Al-In, Al-La, and ternary Al-In-La alloys. The choice of these alloying elements is based on the fact that they are homovalent and have negligible solid solubility in aluminum. Lower solubilities may lead to grain boundary stuffing and hence to the improved EM resistance. In addition, the homovalency minimizes the adverse effect on the metal resistivity from addition of impurities to the metal. 
Attempts are also being made to use multicomponent diffusion principles to tailor a aluminum-based ternary which would exhibit a multicomponent effect leading to the occurrence of zero flux planes (ZFPs), regions in the reaction zone of the diffusion couple where the flux of a component goes to zero.