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spring 1998 logo1998 MRS Spring Meeting & Exhibit

April 13 - 17, 1998 | San Francisco
Meeting Chairs: John A. Emerson, Ronald Gibala, Caroline A. Ross, Leo J. Schowalter

Symposium J—Electronic Packaging Materials Science X


Daniel Belton 
Assembly Technology Dept 
Intel Corp 
Chandler, AZ 85226 

Michael Gaynes
Chip Assembly Technology
IBM Corp
U12 Bldg 23-2
Endicott, NY 13760

Elizabeth Jacobs 
DSPS Packaging Development 
Texas Instruments Inc 
Semiconductor Group 
Dallas, TX 75265 

Raymond Pearson
Dept of MS&E
Lehigh Univ
MS 477
Bethlehem, PA 18015-3195

Tien Wu 
Dept U12 
IBM Microelectronics 
Endicott, NY 13760 

Symposium Support 
*Intel Corporation 
*Intel Japan 
*Texas Instruments, Inc. 

Proceedings published as Volume 515 
of the Materials Research Society 
Symposium Proceedings Series.

* Invited paper

Chairs: Daniel Belton and Raymond Pearson 
Tuesday Morning, April 14, 1998 
Salon 1
8:30 AM *J1.1 
MEASUREMENT OF HYDRO-THERMAL FATIGUE RESISTANCE OF A MODEL UNDERFILL/PASSIVATION INTERFACE FOR DIRECT CHIP ATTACH ASSEMBLIES. Charan K Gurumurthy, Department of Materials Science and Engineering, Cornell University, Ithaca, NY; Chung Yuen Hui, Department of Theoretical and Applied Mechanics, Cornell Univesity, Ithaca, NY; Edward J. Kramer, Department of Materials, University of California at Santa Barbara, Santa Barbara, CA. 

Delamination of underfill/passivation interface in a flip chip microelectornic assembly is a major cause for failures during reliability testing of these assemblies. The underfill/passivation interface experiences severe thermal stresses due to large coefficient of thermal expansion (CTE) mismatches between the flip chip component (silicon) and the printed circuit board (PCB) on which they are mounted. In addition, this interface undergoes hydro-thermal fatigue during reliability testing and during real-life operation. Adhesion testing of underfill/passivation interface using realistic loading conditions is a serious challenge due to the complex loading state present in the assembly. Most of the currently available adhesion measurements techniques either do not provide correct loading or do not test for fatigue. These tests can also be very cumbersome. We have developed a simple and quick hydro-thermal fatigue testing method using a fiber optic sensor to measure the displacement of the cracked end of a bimaterial beam. From the displacement at the lowest temperature in the cycle, we measure the crack growth rate per cycle (da/dN) along a model underfill/passivation interface. A plot of crack growth rate as a function of the strain energy release rate (which acts as the crack driving force) characterizes the hydro-thermal fatigue resistance of the interface. We will present results on interfaces between a model anhydride cured epoxy, which captures the basic chemistry of the commercial underfills and a commercial PMDA/ODA polyimide passivation. 

9:00 AM J1.2 

As the surface mounted plastic packages become thinner and smaller, reliability of these packages has become an important issue. Plastic packages are usually subject to thermal stress coming from the thermal expansion mismatch among component materials, as well as vapor pressure loading from the expansion of absorbed moisture during the reflow soldering process, which often leads to the interface delamination and popcorn cracking. Therefore, it is important to know micromechanisms of the interface delamination, and understand how initial cracks at various interfaces would behave during the reflow soldering process. The popcorn cracking phenomena of the plastic IC packages during reflow soldering are investigated by the combination analysis of heat transfer and moisture diffusion with the interface fracture mechanics theory. At first, the uncoupled transient heat transfer and moisture diffusion through the epoxy molding compound(EMC) under the die pad are analyzed by the finite difference method during the preconditioning and reflow soldering, and the deformation, moisture mass and vapor pressure at the delaminated interface between the die pad and EMC are calculated during the reflow soldering. By this analysis, the vapor pressure at the delaminated interface is obtained quantitatively on the basis of the diffusion theory, and the systematic and quantitative explanation of the mechanism of popcorn cracking phenomena are presented. Secondly, using these calculated vapor pressures, the fracture mechanics parameters like the energy release rate, stress intensity factor and phase angle, which were modified so as to satisfy the conservation law even under the thermal load condition, are calculated at the crack tip of the delaminated interface between the die pad and EMC as a function of interface delamination length within the very small length range. And it is tried to evaluate the interface crack propagation behavior by a comparison of the numerically calculated energy release rate with the qualitatively introduced interface fracture toughness at the same phase angle, and it is estimated separately the effects of the thermal load, crack face vapor pressure load and mixed load of both. Finally it is shown under the reflow heating condition that thermal load is dominant to the crack propagation within the very small delamination length range, but as the length increases, vapor pressure load is more significant. 

9:45 AM *J1.3 
ADHESION AND RELIABILITY OF ORGANIC/INORGANIC INTERFACES IN MICROELECTRONIC PACKAGES. Reiner H. Dauskardt, Jeff Snodsgrass, and Seung-Yeop Kook, Dept. of Materials Science and Engineering, Stanford University, Stanford, CA; and Amol Kirtikar, INTEL Corporation, Chandler, AZ. 

Resistance to progressive debonding of interfaces profoundly influences the long-term reliability of microelectronic packages during service. Such time or loading cycle dependent debonding leads to a loss of thermal, mechanical and, in some cases, electrical integrity of the package. In this presentation, we examine such debonding properties of representative polymer/metal and polymer/silicon interfaces commonly found in microelectronic packages. Interface fracture techniques are described to characterize both critical adhesion values and progressive debonding behavior under cyclic fatigue and monotonic loading conditions. Debond-growth rates were found to display a power-law dependence on the applied debond driving force characterized in terms of the strain energy release rate, G. Critical values of adhesion are shown to be sensitive to a range of salient microstructural and environmental variables including the interface morphology, polymer layer thickness, relative humidity, and loading mode mixity. While progressive debonding was in general found to be sensitive to the same factors, some surprising behavior was apparent particularly with regard to polymer layer thickness. Micromechanisms controlling interfacial adhesion and progressive debonding are discussed in terms of the prevailing deformation mechanisms and related to interface structure and morphology. Implications for package reliability and life-time prediction are discussed. 

10:15 AM J1.4 
ADHESION AND SUBCRITICAL DEBONDING OF POLYMER/SILICON INTERFACES FOR MICROELECTRONIC PACKAGING. J.M. Snodgrass, J. Lin and R.H. Dauskardt, Department of Materials Science and Engineering, Stanford University, Stanford, CA. 

The increasing complexity of microelectronic packages means that product reliability is often dependent on the integrity of interfaces between the chip (silicon) and the package materials (polymers). In this presentation, we discuss techniques for evaluating both critical interface adhesion values as well as the sub-critical debond behavior that is relevant in predicting the in-service life behavior of microelectronic packages. Our research characterizes adhesion and subcritical debonding of a model PMMA/silicon interface system, as well as a technologically relevant underfill/polyimide/silicon interface system. Adhesion values are measured by driving a stable debond along the polymer/silicon interface. A sandwich structure is utilized for the sample geometry, thereby constraining the polymer of interest between two rigid silicon substrates, which prevents the relaxation of residual stresses during testing. Issues of crack path selection involving the selection of microstructurally weak paths in the layered system are considered. The effects of subcritical as opposed to critical loading conditions is described and related to life prediction methodologies. 

10:30 AM J1.5 
ANALYSIS OF A CATASTROPHIC FIELD FAILURE DUE TO CONDUCTIVE ANODIC FILAMENT (CAF)FORMATION. W. Jud Ready, Brian A. Smith, and Laura J. Turbini, Georgia Institute of Technology, School of Materials Science and Engineering, Atlanta, GA. 

Under certain environmental conditions, printed wiring boards (PWB) respond to applied voltages by developing subsurface deposits of copper salts extending from anode to cathode along separated fiber / epoxy interfaces. These deposits, termed conductive anodic filaments (CAF) require high humidity (80RH) and high voltage gradient (5V/mil). The humidity may be due to the storage environment, which affects the failure in the use environment. CAF formation is enhanced by the use of certain hot air solder leveling (HASL) fluids and / or water soluble flux constituents. In this work, a catastrophic field failure was analyzed. This failure was related to boards produced in a manufacturing process, which included HASL. The CAF failure occurred on an inner layer of a multi-layer board (MLB) between a via and ground plane held a potential difference of 320V with 0.015'' nominal spacing. The nature of the CAF was analyzed using scanning electron microscopy (SEM) and energy dispersive x-ray spectroscopy (EDS). Ion chromatography (IC) and high performance liquid chromatography (HPLC) were used to identify residue extracted from the failed boards. The failure phenomena known as CAF poses serious long-term reliability concerns in electronic applications exposed to adverse and hostile environments, especially those with closely spaced conductors.

Chairs: Daniel Belton and Raymond Pearson 
Tuesday Afternoon, April 14, 1998 
Salon 1
1:30 PM *J2.1 
FRACTURE AND FATIGUE AT INTERFACES IN ELECTRONIC PACKAGES . Subra Suresh, Dept of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, MA. 

This presentation will address some critical issues which determine the conditions for cracking at interfaces between dissimilar solids, with applications to electronic packages. Theoretical studies of fracture and fatigue along and at various angles to the interfaces will first be presented. This will be followed by discussions of systematic experiments of fatigue fracture parallel to and inclined to the interfaces in model systems designed to produce different elastic, plastic and thermal mismatches across the interfaces. The presentation will conclude with experimental studies of fatigue crack propagation along polymer-metal interfaces in electronic packages. Some strategies for improving the fatigue crack growth resistance at interfaces in packaging materials will also be highlighted. 

2:00 PM *J2.2 
EFFICIENT INTERFACIAL DESIGN - A MULTIDISCIPLINARY VIEW. C.F Shih, W.T. Chen, B. Cotterell, and S.K. Lahiri,Institute of Materials Research and Engineering, National University of Singapore, SINGAPORE. 

Successful microelectronics products need the active collaboration of many disciplines to ensure improved cost manufacturability and guaranteed reliability. Packaging is a key enabling element in the success of the electronic product. The search for higher performance, lower cost, and the growth of the portable electronic product market, calls for the design of smaller and lighter packages with specific electrical, mechanical and thermal attributes, which necessarily contain a wide variety of materials with quite different coefficients of thermal expansion. Great strides have been made in packaging higher density and larger chips with cost competitive plastic packages (PEM, PBGA, FP-PBGA, CSP) while maintaining quality and reliability. The microelectronics industry is forecasting that the present density, complexity, and cost trends will continue at least in the first decade of the next millennium. 
One of the most important mechanical features in electronic packaging is the interface. An improved knowledge of interfacial design in all its aspects - mechanical, material, surface chemistry and manufacturing - will give us the capability to meet future challenges. Although the general precepts of classic continuum fracture mechanics apply, linear elastic fracture mechanics is not the best means of characterising many aspects of interfaces in microelectronic packaging. Incorporating a fracture process zone in the model for the interface provides a better approach which can quantify effects such as crack bridging that can be used to toughen an interface through mechanical design. 
Concomitant with the mathematical modelling of interfacial fracture is the measurement of interfacial toughness. While fractures in homogenous bulk materials are usually pure mode I, interfacial fractures are almost invariably mixed-mode. In general the mixed-mode interfacial toughness is very much larger than the mode I toughness and measurements must take mode-mixity into account. The mechanics community is addressing the interface robustness issues from the continuum mechanics perspective, while the materials community is developing new materials and processes to tailor the interfaces for toughness and manufacturability. Some of the materials involved in packaging are composite materials themselves. Thus there are interfaces at many different scale levels. Modelling at the atomic level is also progressing with the ultimate aim of bridging the gap with continuum mechanics. Of equal importance is the effort in both industry and academia to transfer basic research to the drawing boards and the factory floors. 
In this paper recent developments in modelling interfacial fracture and the measurement of interfacial toughness relevant to microelectronic packaging are discussed. 

3:00 PM J2.3 
EXPERIMENTAL INVESTIGATION ON INTERFACIAL ADHESION IN MICROELECTRONIC ASSEMBLIES. Xiang Dai, University of Texas, Materials Lab for Interconnect & Packaging, Austin, TX; Mark V. Brillhart, Hewlett-Packard Co., Electronic Assembly Development Center, Palo Alto, CA; Paul S. Ho, Materials Lab for Interconnect & Packaging, Austin, TX. 

The performance requirements of future electronic packages create the need to transition from traditional wire bond connections to advanced technologies such as flip chip on laminate packages and direct chip attach. These high performance connections utilize a particulate reinforced structural epoxy (underfill) to adhere the chip to the package or board. The integrity of the underfill/silicon chip and underfill/substrate (ceramic or polymer laminates) interfaces are crucial for the reliability of these chip attach methods. This paper presents novel fracture-mechanics-based experimental and analytical techniques for quantitatively and reproducibly determining the adhesive performance of chip/underfill and polymer substrate/underfill interfaces. These techniques can be employed to rapidly evaluate new materials and examine process modification impact on adhesive performance in a wide range of environments. Additionally, the interfacial fracture energy measured with high accuracy can provide a basis for realistic modeling of thermo-mechanical reliability within microelectronic assemblies. At present, we are performing the adhesion studies on underfill/passivated silicon and undefill/polymer coated FR4 board interfaces (G1c ranges from 10 to 300 J/m2 for these interfaces). Furthermore, we are actively investigating the effects of different underfill formulations and different chip passivation layers, such as silicon nitride, polyimide, BCB, etc., on underfill/chip interfacial performance. Initial studies are promising because they show the differences between structures of same underfill with different substrates and different underfill formulations with same substrate are distinguishable with no ambiguity. These results and further progress will be presented and discussed. 

3:15 PM J2.4 
MOLECULAR MODELING AS A TOOL FOR ADHESIVE PERFORMANCE UNDERSTANDING. N. Iwamoto, J. Pedigo, A. Grieve, M. Li, Johnson Matthey Electronics, San Diego, CA. 

As higher levels of reliability are sought, it will become increasingly important to understand the relationship between the adhesive formulation and its bonded substrate. Johnson Matthey has been addressing this need by using molecular modeling to simulate the physical effects of adhesive components on properties such as adhesion, surface spread or bleed, and underfill flow. Newtonian molecular modeling was chosen as a method of choice because of ease of use and the increased system size capability over quantum techniques. Additionally, by using a molecular modeling method as opposed to a continuum calculation, the individual components of an adhesive may be theoretically manipulated without pre-determination of properties or property effects. The potential utility of the technique lies in the prediction or confirmation of property trends when different components or processes are used. Two major areas of interest have involved bleed and adhesion. For spreading issues such as bleed, calculations have involved the modeling of specific monomeric components on various substrates, with subsequent comparison to experimental results. Although not quantitative, the modeling has allowed us to determine qualitative trend directions of formulation components, including the spurious effects of moisture. The modeling technique is also being used to understand the impact of formulation on underfill flow. Similar techniques were used to predict polymer adhesive behavior, in which the predicted adhesion trend was calculated to generally fall with the surface energy, in agreement with the literature. In addition, calculations are being used to determine adhesive trend directions under the influence of moisture for reliability correlation. For moisture studies of adhesion and flow it was assumed that moisture concentrated at the interfaces contribute greatly to the failure of the material, which is consistent with other studies done at NIST detecting moisture accumulation at interfaces. 

Chair: Elizabeth G. Jacobs 
Wednesday Morning, April 15, 1998 
Salon 1

8:30 AM J3.1 
PHASED-IN Cr-Cu AS UNDER-BUMP METALIZATION FOR HIGH-Pb AND EUTECTIC SnPb SOLDERS. Ann A. Liu, TRW Space & Electronics Group, Redondo Beach, C A; G.Z. Pan, H.K. Kim & K.N. Tu, Dept of Materials Science & Engineering, UCLA, Los Angeles, CA; P.A. Totta, IBM East Fishkill Facility, Hopewell Junction, NY. 

Multilayer Cr/Cu/Au thin films have been used as under-bump metallization (UBM) in electronic packaging for flip chip joint. Due to the limited amount of Cu supply in the UBM, spalling of Cu-Sn intermetallic compounds occurred in solder reflows in the Cr/Cu/Au case, and a phased-in Cr-Cu/Cu/Au was introduced to impede the spalling effect. The phased-in Cr-Cu layer was found to be intermixed and the grains of both Cr and Cu elongated along the growth direction. This special compositionally graded or functionally graded microstructure presents a lock-in effect of the Cr and Cu grains. The phased-in Cr-Cu/Cu/Au multilayer UBM has been proven to be successful in preventing the spalling of Cu3Sn in solder joints formed with the high-Pb solder, 95Pb-5Sn, but failed in preventing the spalling of Cu6Sn5 in solder joints formed with the eutectic SnPb solder. In this talk, we propose that the difference may be due to the different dissolution and ripening rates of the two compounds in the solders. In addition, cross-sectional scanning and transmission electron microscopic images of the phased-in Cr-Cu microstructure will be presented. 

8:45 AM J3.2 
THE STUDY ON THE UNDER BUMP METALLURGY (UBM) AND 63SN-37PB SOLDER BUMPS INTERFACE FOR FLIP CHIP INTERCONNECTION. Se-Young Jang, Kyung-Wook Paik, Korea Advanced Institute of Science and Technology, Dept of Material Science and Engineering, Yusong-Gu, Taejon, KOREA. 

In the flip chip interconnection using solder bump, the Under Bump Metallurgy (UBM) is required to perform multiple functions in its conversion of an aluminum bond pad to a solderable surface. The UBM(Under Bump Metallurgy) systems for flip chip bumping technology using the low melting point eutectic 63Sn-37Pb solder were investigated to find reliable condition. 60m size bumps were prepared using an electroplating process. After sequential deposition of the UBM on Si substrate thick photoresist was patterned, and then 63Sn-37Pb alloy was electroplated in an organic sulfonate bath. Solder reflowing was performed in an infrared reflow oven at ambient atmosphere. The effect of the number of reflowing process - solder ball forming reflow, flip chip bonging reflow, organic carrier bonding reflow, and PCB board assembly reflow - were investigated at 150C for various aging times. Intermetallic Compounds(IMC) growth at the solder and UBM interface for the selected UBM systems such as Al/Ti/thick Cu, Al/Ti/1m Cu, Al/Ni/1m Cu, Al/Pd/1m Cu was also investigated. Sn-Cu, Sn-Ni, Sn-Pd, Sn-Ti reaction at interfaces were observed by the back scattered scanning electron microscopy(SEM), energy dispersive X-ray(EDX) and X-ray diffractometer(XRD). The effect of UBM/solder interface reaction on mechanical bond strength is under investigation using a solder ball shear test. 

9:00 AM J3.3 
UNDER BUMP METALLIZATION DEVELOPMENT FOR EUTECTIC PB-SN SOLDERS. S.J. Hong, T.M. Korhonen, M.A. Korhonen and C.-Y. Li, Dept of Materials Science and Engineering, Cornell University, Ithaca, NY. 

Due to its advantages over other IC chip interconnections, the solder bump flip chip on board technology has emerged to be the most promising chip-attachment method for high I/O density electronic systems. In order to use flip chip bonding on organic substrates, lower melting temperature solders (such as eutectic solder) with reflow temperature around 200 C must be used. It turns out that the conventional Cr/Cr-Cu/Cu/Au under bump metallization(UBM) is not adequate for solders containing large amount of Sn due to fast Sn-Cu reaction which causes dewetting and loss of adhesion between the solder and substrate. Thus improved metallization schemes which are compatible with high Sn solders must be found. In the present research, several new UBM schemes based on Ni and Ni-Cu alloys are investigated. The reliability of the joints adopting the proposed new UBM schemes are estimated by performing mechanical cycling tests. 

9:15 AM J3.4 
MORPHOLOGY OF THE WETTING REACTIONS OF LOW MELTING POINT Pb-FREE SOLDERS ON Ni FOILS AND FILMS. Jessica P. Almaraz and K.N. Tu, Dept. of Materials Science & Engineering, UCLA, Los Angeles, CA. 

In direct chip attachment technology, a low melting point solder is used to join a chip to its module. This is because the module is typically a polymerbased printed circuit board or card. On both the chip and the module, under-bump metallization (UBM) must be deposited for the solder joint. The typical UBM is Cu-based such as a layered Au/Cu/Cr thin film structure. We found that eutectic SnPb or its Pb-free substitutes (eutectic SnBi or eutectic SnAg) reacts very quickly with the UBM due to the high Sn concentration in these solders, and it leads to spalling of Cu-Sn intermetallic compounds. Even the well-known phased-in Cu-Cr structure cannot prevent spalling when it is soldered by eutectic SnPb. At present, Ni is the potential material of choice to replace the Cu, yet very few systematic studies of solder-Ni reaction have been published. In this talk, we report a comparison of reactions of eutectic SnBi and eutectic SnAg to eutectic SnPb on Ni foils as well as Ni films. The change in wetting angles and interfaces will be shown. The soldering reaction on Ni is dominated by the scallop-type Ni3Sn4 compound formation, however, its rate of formation is much slower than that of Cu6Sn5

9:30 AM J3.5 
FLIP CHIP METALLURGIES FOR LEAD-FREE SOLDERS. T.M. Korhonen, S.J. Hong, M.A. Korhonen and C.-Y. Li, Dept of Materials Science and Engineering, Cornell University, Ithaca, NY. 

The most commonly used lead-free solders contain large amounts of tin, which makes them incompatible with the conventional copper-based underbump metallization (UBM) schemes. The tin in the solder reacts with the copper layer of the UBM, depleting the UBM of copper and causing loss of adhesion and a weak interface. Since the intermetallic growth kinetics are slower in the Ni-Sn system than in the Cu-Sn system, the semiconductor industry has identified Ni or Ni-based alloys as the most likely candidates to replace Cu as the metallization adhering to the solder. In this research, Ni has been introduced into the UBM to suppress the growth rate of the intermetallics. Nickel can be utilised either as a thin Ni layer on top of Cu, or by replacing the Cu in the UBM by a Cu-Ni alloy. Reactions between Ag-Sn and Bi-Sn based solders and CuNi alloys of different compositions have been studied. Based on the results, several UBM schemes utilising Ni were fabricated. To test them, solder bumps were reflowed on the UBMs and the resulting interfacial microstructures were studied as a function of reflow time. The joints were also mechanically tested in fatigue and shear to assess the quality and reliability of the interface. 

10:00 AM *J3.6 

The filp chip solder technique for joining chip to module by an area array of solder bumps has gained industrial wide attention laterly. It offers a much larger number of chip-to-packaging connections than the wire bond technique. To apply the solder bump technique to attaching a chip directly to a card or board, low melting point eutectic SnPb (about 200 deg C) solder bumps are required due to the organic nature of the substrates. The eutectic solder, however, contains a high concentration of Sn which reacts very fast with the under-bump Cu thin film metallurgy, leading to spalling of the Cu-Sn compounds and weakening of the solder interface. While Ni-based under-bump metallurgy reduces spalling, it nevertheless has high residure stresses. The kinetic process of spalling and the issue of stress in Ni thin films will be discussed 

10:30 AM J3.7 
MASKLESS, DIRECT DEPOSITION OF COPPER ONTO ALUMINUM BOND PADS FOR FLIP CHIP APPLICATIONS. M. Fang and T. O'Keefe, University of Missouri-Rolla, Rolla, MO; M. Stroder and W. Shih, Brewer Science, Rolla, MO; M. O'Keefe and R. Strawser, Air Force Research Lab, Wright-Patterson AFB, OH; and D. Via, Wright St. University, Dayton, OH. 

Flip chip interconnection of integrated circuits for packaging applications such as direct chip attachment use Pb-Sn solders as the connection between the die and the substrate. Underbump metallization is typically used to transition from the non-solderable Al bond pad on the IC to a solderable surface such as copper using traditional blanket metal deposition, photolithography and etching procedures. In this study we report for the first time the use of a novel process for selectively depositing adherent copper directly onto aluminum thin films, eliminating the need for adhesion promoting transition layers and additional patterning steps. Utilizing copper bearing organic solutions and standard electroless and electrolytic copper plating baths, as-deposited and annealed sputter deposited Al-x%Cu (x=0 to 2) thin films were coated with metallic copper. An increase in the organically deposited copper nucleation site density was observed with increasing copper concentration in the sputtered aluminum/copper thin films. Preliminary results using focused ion beam microscopy indicated that dissolution of the aluminum oxide surface and subsequent deposition of copper by cementation occurs in the non-conducting organic solution at sub-micron reaction lengths. Qualitative adhesion testing of samples resulted in the majority of films passing the tape test. Demonstration of the process using 50 micron diameter vias in BCB coated flip chip test vehicles from MCNC will be presented. 

10:45 AM J3.8 
ALLOY JOINTS FOR HIGH TEMPERATURE ELECTRONIC PACKAGING. William W. So, Chin C. Lee, University of California, Irvine, CA.

Abstract not available.