Film Measurement Div
Milpitas, CA 95035
Electronic and Electrical Engineering
Sheffield, UNITED KINGDOM
44 (114) 222 5384
IBM T.J. Watson Research Ctr
Yorktown Heights, NY 10598
JEOL USA, Inc.
*Kevex Instruments, Inc.
*LEO Electron Microscopy Inc.
*Nissei Sangyo America Ltd.
*NORAN Instruments, Inc.
*Philips Electron Optics
*R.J. Lee Instruments Ltd.
1998 Spring Exhibitor
Proceedings published as Volume 523
of the Materials Research Society
Symposium Proceedings Series.
* Invited paper
8:30 AM *U1.1
SESSION U1: SPECIMEN PREPARATION AND DEFECT ANALYSIS IN SEMICONDUCTING DEVICES
Chairs: Clive Hayzelden and Paul D. Brown
Wednesday Morning, April 15, 1998
TRANSMISSION ELECTRON MICROSCOPY OF SEMICONDUCTOR BASED PRODUCTS. John Mardinly
, David Susnitzky, Intel Corporation, Dept. of Materials Technology, Santa Clara, CA.
The demand for increasingly higher performance semiconductor products has stimulated the semiconductor industry to respond by producing devices with increasingly complex circuitry, more transistors in less space, more layers of metal dielectric and interconnects, more interfaces, and the number of manufacturing steps approaching 1,000. As all features are being shrunk in the quest for higher performance, the role of Transmission Electron Microscopy as a characterization tool takes on a continually increasing importance over older, lower-resolution characterization tools, such as SEM. The ngstrom scale spatial resolution for imaging and nanometer scale spatial resolution for chemical and diffraction analysis provided by modern TEMís are particularly well suited for solving materials problems encountered during research, development, production engineering, reliability testing, and failure analysis. A critical enabling technology for the application of TEM to semiconductor based products as the feature size shrinks below one quarter micron is advances in specimen preparation. The traditional 1,000 thick specimen will be unsatisfactory in a growing number of applications. It can be shown by a simple geometrical model, that the thickness of the specimens must shrink as the square root of the feature size reduction. Moreover, the center-targeting of these specimens must improve so that the center-targeting error shrinks linearly with the feature size reduction. Control of the specimen preparation process will require a new generation of polishing and ion milling tools that make use of high resolution imaging to control the ion milling process. In addition, as the specimen thickness shrinks, the total amount of surface amorphization produced must also be reduced. Gallium focused ion beam systems can produce hundreds of ngstroms of amorphised surface silicon, an amount which can consume an entire thin specimen. This requires a method of removal of amorphised material that leaves no artifact in the remaining material.
9:00 AM U1.2
FAILURE ANALYSIS USING EBIC AND VOLTAGE CONTRAST. Larry Rice
, Bob Carpenter, Wei Chen, Materials Characterization Laboratory Materials Research and Strategic Technologies, SPS, Motorola, Mesa, AZ.
As the ULSI device critical demension continues to shrink to sub micron sizes, electron microscopy techniques such as electron-beam-induced-current (EBIC) and Voltage Contrast are finding more applications towards pinpointing failure sites for subsequent cross-sectioning or deprocessing. In addition to the traditional use of EBIC for junction delineation, EBIC has been applied to locate leakage sites in capacitor structures and SOI devices as well. Similarily, Voltage Contrast has been applied to identify single or multiple opens in via chains which consist of thousands of vias. In addition to a brief revisit of the basic principles of EBIC and Voltage Contrast, focus will be placed the application of EBIC and Voltage Contrast in the failure analysis of semiconductor devices. Examples of using Voltage Contrast combined with precision FIB cross-sectioning for identifying the failure mechanism of 0.8µm vias will be presented. Also, the use of EBIC for identifying leakage sites in SOI and subsequent FIB/SEM analysis will be presented as well. Finally, FIB induced deposition for EBIC analysis of a 4MB FSRAM device will be discussed.
9:15 AM *U1.3
PREPARATION OF TEM PLAN VIEW SECTIONS ON SPECIFIC DEVICES USING THE TRIPOD POLISHER. J.P. Benedict
, Ron Anderson, S.J. Klepeis, IBM Analytical Services Group, Hopewell Junction, NY.
One way to establish the connection between the electrical test data and the morphology of a specfic device is by examining a TEM section of that device in top-down or plan view. This plan view section must have a large TEM transparent area to encompass the specific area and enough of the surrounding area to do an adequate analysis on a number of devices. Also, the transparent area must be large enough to scan for random defects that are not discovered by cross sections of specific devices. Because devices today may have storage and isolation trenches extending deep into the substrate, the surface topography induced by preparing a plan view sample using extensive ion milling in conjunction with chemical etching or mechanical dimpling makes viewing the area of interest difficult. This problem is overcome by mechanically polishing down to TEM transparency using the Tripod Polisher. The specific device is located and marked on the device side by cutting some small marker trenches near to it using a FIB ( Focused Ion Beam) tool. The FIB marked side of the sample is then glued to a Tripod Polisher and wet polished using diamond paper. The polishing is monitored using light transmitted up through the sample to gauge its thickness and to make small side-to-side adjustments in the polishing. The sample is final polished using a colloidal silica slurry until it is TEM transparent and all the surface scratches are removed. The sample is taken off the polisher and analyzed in the TEM with little or no additional ion milling. Since the sample has only been polished, it is relatively uniform in thickness across the entire sample. Because of this, the area of interest and a large area around it, hundreds of square microns in size, are available for TEM analysis.
10:15 AM U1.4
APPLICATIONS OF PLASMA CLEANING FOR ELECTRON MICROSCOPY OF SEMICONDUCTING MATERIALS. Thomas C. Isabell
, Paul E. Fischione, E.A. Fischione Instruments, Inc., Export, PA.
Specimen contamination and amorphous irradiation damage severely limit the ability to perform accurate electron microscope analysis of semiconducting materials, especially as specimen areas of interest decrease in size. To analyze smaller areas of interest, electron probe sizes have decreased, while probe currents have increased. The combination of these two factors results in an increase in the amount of carbonaceous contamination formed on the specimen under the electron beam. Recently, the use of low energy plasmas has been shown to be effective in preventing such contamination from occurring. For TEM, the simultaneous placement of the specimen holder and specimen into such a plasma for short periods of time results in the ability to hold a converged probe on the specimen for analysis without contamination becoming an problem. Furthermore, in this presentation we show that existing contamination from prior TEM analysis can often be removed from the specimen by plasma cleaning.
As the device size in the semiconductor industry is reduced, site specific preparation of TEM specimens becomes more important. One method of such preparation gaining in popularity is the use of focused ion beam (FIB) equipment. In FIB, heavy ions are highly accelerated to directly and accurately mill the specimen to electron transparency. One side effect of such preparation is the formation of an amorphous damage layer on the specimen. By adjusting the plasma processing parameters, we have found that amorphous damage on a specimen can be directly removed through low energy sputtering. Additionally, through the use of more chemically reactive gas species in the plasma, such damage can be chemically removed at low ion energies. Such removal of damaged zones is beneficial not only for damage from FIB, but for damage induced by conventional ion milling as well.
10:30 AM U1.5
REDUCTION OF THE DAMAGE INDUCED IN AN FIB-FABRICATED TEM SPECIMEN. Naoko I. Kato
, Nobuhito Miura, IBM Japan, ITES Reliability and Material Engineering, Shiga, JAPAN; Tsujimot Katsuhiro, IBM Japan, Display Technology, Kanagawa, JAPAN.
Focused ion beam (FIB) milling has been intensively used for preparation of cross-sectional transmission electron microscopy (X-TEM) specimens. However, in FIB fabrication, highly accelerated ion beams sometimes cause serious damage. The damage can be induced in the specimen surface as well as in the side walls. To avoid the former, a protective layer is normally formed on the specimen surface. We used X-TEM observation to investigate the damage to the side walls in the cases of conventional FIB etching and gas-assisted etching (GAE). The depth of damage to the side walls in crystalline silicon was found to be about 20 nanometers for conventional etching and GAE alike. We also investigated the surface damage caused by the formation of protective layers by methods such as ion-beam-assisted metal deposition, sputter-coating, and plasma-polymerization. It was found that the damage depth is about 40 nanometers for ion-beam-assisted deposition, and a few nanometers or less for sputter-coating.
10:45 AM *U1.6
APPLICATION OF TEM ON SUB-HALF MICRON SEMICONDUCTOR DEVICES. Hong Zhang
, PVD Technology, Applied Materials, Santa Clara, CA.
Manufacture of Semiconductor industry has rapidly shifted into sub-half micron regime. 0.35um devices are on production and 0.25um technology is ready to launch. Although there is no major change in basic materials used to build the devices, many new process methods, like IMP, long throw, HDP CVD, CVD-PVD integration for metal deposition, must be implemented correctly and process conditions must be controlled tightly in order to distribute the materials to the ideal positions in right amount. Semiconductor manufacture has never been so much relying on precise characterization of each process step and device performances have never been so sensitive to film quality, interface structure, impurities and contamination. Obviously, transmission electron microscope, because of its high image and spatial resolution as well as analytical ability, is expected to play a critical role in future development and manufacture of sub-half micron devices. In fact, we have already been benefited greatly by applying transmission electron microscope (TEM) to assistant process development on 0.35um, 0.25um and 0.18um metal deposition technologies. In this paper, we will address some special issues and concerns related to perform TEM on sub-half micron devices. A large number of examples are given to illustrate how the TEM techniques can be utilized to assistant process development and resolve manufacture issues. Meanwhile, precision TEM techniques will be explained in terms of not only precisely reaching smallest features on devices, but also precisely pointing out the single process step which causes failure. In addition, a wedge type TEM sample preparation procedure will be explained accordingly. By using a new polish device called T-tool, one can make a cross section TEM specimen within two hours. This very compacted device has precise control on polish front and wedge angle, and is very easy to use. Given examples include TEM images of semiconductor devices with six layer metallization and more than 1mm long electron migration structure.
11:15 AM U1.7
THE CHALLENGE AND METHODS OF PRECISION TEM CROSS-SECTIONING OF < 0.25 MICRON PLUGS. C. Amy Hunt
, Yuhong Zhang, Electron Microscopy Services, Accurel Systems, Sunnyvale, CA.
Transmission electron microscopy (TEM) is a useful tool for process monitoring / evaluation and failure analysis. A well-prepared sample is essential for analysis. Precision cross section sample preparation involves thinning the sample to <100nm thick around the feature of interest with a tolerance of a few microns in the lateral directions and less than a tenth of a micron deep. As the feature size decreases these tolerances also decrease, and the difficulty of precision sample preparation rises sharply. For example, in order to examine the adhesion layer of a 250-nm plug in a cross-sectional view, the cross-sectional plane should be centered on the plug center. The adhesion layer is about 20nm thick and subtends the entire 100nm thick specimen at essentially a right angle. This condition will allow high contrast viewing of the adhesion layer. However, if the cross-section is off-center by more than 25nm then there will be no through-thickness areas of the adhesion layer. The adhesion layer quickly becomes invisible as the cross-section becomes more off-center because of contrast from the interlayer dielectric and the plug material. This problem is increasingly more challenging as the plug size gets smaller. The common methods of TEM cross-section preparation (XTEM) are mechanical dimpling & ion milling (dimple/ mill), focused ion beam milling (FIBXTEM), and wedge mechanical polishing (wedge/ mill). Each precision XTEM technique has important advantages and limitations that must be considered for each sample. The presentation will discuss these considerations as well as strategies for precise localization of the cross-section.
11:30 AM U1.8
EVALUATION OF SINGLE SEMICONDUCTOR DEFECTS USING MULTIPLE MICROANALYSIS TECHNIQUES. Yuri Uritsky
, Richard Savoy, Applied Materials, Inc., Santa Clara, CA; Patrick Kinney, MicroTherm, LLC, Minneapolis, MN; E.L. Principe, Ian Mowat, Lori McCaig, Charles Evans and Associates, CA.
New analytical techniques are being employed to meet the stringent requirements for controlling defects in semiconductor manufacturing. While SEM/EDX continues to be an effective tool for root-cause analysis of particles and defects on the wafer surface, increasingly it is necessary to employ multiple techniques in analysis of a single defect to obtain sufficient information to resolve the problem. Until recently, this approach was impractical because the defects were too difficult to locate in standard analytical tools, especially on unpatterned wafers. But with the newly developed Mark-Assisted Defect Analysis (MADA) technique, the positioning problem has been eliminated, and it is a simple matter to employ multiple techniques on the same defect. In this paper we present results for defects analyzed by SEM/EDX, TOF-SIMS, -ESCA, and AUGER, highlighting how these techniques compliment each other. Particular emphasis is given to the issue of the analytical technique changing the sample chemistry and influencing the results of subsequent analysis techniques.
11:45 AM U1.9
APPLICATION OF ELECTRON MICROSCOPY TOWARDS SUB-MICRON PARTICLE ANALYSIS. Larry Rice
, Wei Chen, Materials Characterization Laboratory Materials Research and Strategic Technologies, SPS, Motorola, Mesa, AZ.
Small particles in ULSI devices are known to be one of the key causes for affecting device yield. This is especially true since the modern devices are shrinking in all dimensions, and therefore the critical size for ìkillerî particles is also shrinking. It is increasingly challenging to identify the root cause of particle contamination in terms of locating and identifying the particles. A precise cross-section through the particles is required to be able to identify at which processing step the particles were incorperated into the layers, and an EDS microanalysis helps identify the source. This presentation focuses on the methodology for carrying out particle analysis. In addition to the much needed processing knowledge, it demonstrates the importance of techniques such as SEM, EDS, and FIB and when to use them. This discussion will include the analysis of subµm aluminum particles observed after final passivation, a tungsten particle shorting M1 to M2 causing a word failure in SRAM array, and iron particles shorting adjacent metal lines.
1:30 PM *U2.1
SESSION U2: METALLIZATION, SILICIDES AND DIFFUSION BARRIERS
Chairs: Frances M. Ross and Hong Zhang
Wednesday Afternoon, April 15, 1998
CRYSTALLOGRAPHIC MAPPING OF MULTIPHASE MATERIALS. David Dingley
, TexSEM Laboratories, Inc., UT, and Bristol University, UNITED KINGDOM.
Both the techniques of electron backscatter diffraction and Orientation Imaging Microscopy are well established tools for the characterization of polycrystalline materials. Application of the techniques to the study of copper and aluminum metallization layers has shown that the limiting resolution for mapping is of the order 0.1 microns. A progressive step forward has been the addition of a method by which the diffraction patterns from different crystal phases can be distinguished permitting multiphase crystallographic maps to be drawn. In subsequent analysis the multiphase data sets are partitioned into the separate phase and texture components permitting the grain size distribution, the orientation distribution function and the misorientation distribution function to be calculated for each subset or between subsets where appropriate.
Most recently the technique was extended to the transmission electron microscope to enable nanocrystalline materials and semiconductor cross sections to be studied. The technique couples the standard hollow cone microscopy facility with dark field microscopy. The dark field image is scanned to detect which crystals are diffracting at a particular setting of the hollow cone scan. Each setting defines one diffraction condition. The dark field search is repeated for all possible settings of the hollow cone scan so that eventually for each crystal in the image there will be recorded a number of settings under which it diffracts. Analysis permits determination of both phase and crystal orientation.
Current experiments have been limited to plan view investigations of single phase polysilicon, aluminum and copper films. Future experiments are to be conducted on multiphase cross sections of semiconductor devices. The limiting resolution is of the order 10nm.
2:00 PM U2.2
COMPARISON OF ORIENTATION IMAGING MICROSCOPY AND X-RAY POLE FIGURE ANALYSIS FOR TEXTURE DETERMINATION IN Al THIN FILMS. Derrick T. Carpenter
, Lehigh Univ, Dept of Materials Science and Engineering, Bethlehem, PA; Roger Alvis, Guarionex Morales, Advanced Micro Devices, Sunnyvale, CA.
Preferred crystallographic orientation, or texture, is known to have a large effect on the electromigration resistance of Al-based metallization materials. There is substantial evidence in the literature to show that strong 111 fiber texture improves reliability. The most common analytical method used to measure texture is X-ray diffraction (XRD), usually a simple rocking curve generated about the 111 peak. While this data gives relative information about peak sharpness, it is not sufficient to fully characterize texture. Pole figure analysis yields complete information about texture, but is not commonly available outside of specialized laboratories. Orientation imaging microscopy (OIM) is a technique based on electron diffraction which measures texture using a scanning electron microscope. OIM data are discrete grain orientations rather than the continuum of intensity gathered by XRD, but given sufficient counting statistics and the proper analysis, they may be directly compared. OIM and XRD analyses of the same samples are essentially identical, however the discrete nature of the OIM data gives it near-infinite dynamic range. This means that features of extremely low intensity, which are undetectable in a typical XRD analysis due to noise, can be detected using OIM without a priori knowledge of their existence. Extremely small (but statistically real) peaks have been detected in 111 pole plots generated by OIM from 111 fiber textured Al films, indicating that 1% of the grains analyzed are far from a 111 orientation. These rogue grains may be important in early failures of lines. Details of these findings and the analysis applied to the OIM data will be presented.
2:15 PM U2.3
GRAIN SIZE DISTRIBUTION AND DEGREE OF TEXTURE IN FILMS USED IN INTEGRATED CIRCUITS. Richard Lindsay
, John Chapman, Alan Craven, Dept of Physics and Astronomy, University of Glasgow, UNITED KINGDOM; Donna McBain, Motorola Ltd, East Kilbride, UNITED KINGDOM.
As miniaturisation proceeds, the electrical properties of a conductive film used in modern ICís are increasingly influenced by the grain sizes and the texture of the film. There is a need therefore to devise techniques which can examine these properties. Described in this work are two cross-sectional TEM techniques for use on fully-processed ICís to determine grain size distributions and the degree of texture in a film. A 3-level metallization memory chip is cross-sectioned for the TEM using the tripod polishing technique. Grain sizes in aluminium metallization films are often indeterminable through imaging as not all grain boundaries are visible. With the microscope set up in scanning mode, an electron probe is slowly scanned along the centre of the film. As the probe crosses a grain boundary the diffraction pattern changes. At this point the TEM operator changes the signal from the STEM unit to an imaging program on a PC from high to low and vice versa at the next grain boundary. This way a bright and dark pattern is produced where all the grain boundary positions are manifest. Further statistical analysis to the grain boundary separations produce a distribution of the grain sizes. In a similar fashion the microscope is set up to scan rapidly across a rectanglular area of a polycrystalline film defined by the user. If enough (>30) grains are covered in the scan the diffraction pattern can be used to identify texture in the film by comparison to theoretical patterns. The strengths of the upper column lenses in the microscope are adapted to enable easier resolution of the spots. Further analysis on the diffraction pattern is used to identify the degree of texturing; i.e. the fraction of grains with a common orientation.
2:30 PM U2.4
AUTOMATED MICROSTRUCTURAL ANALYSIS FROM TEM/STEM IMAGES. D.T. Carpenter
, J. M. Rickman, and K. Barmak, Lehigh University, Dept. of Materials Science and Engineering, Bethlehem, PA.
The microstructure of the components of a device can have a profound effect on the performance of that device. For example, changes in the grain size distribution of the metallization result in substantial differences in electromigration resistance. Grain size is most commonly measured from TEM images manually, typically from only a few hundred grains. In cases where differences may be more subtle, for instance diffusion barriers or intermetallic underlayers, this small sampling may be insufficient. Automatic grain size analysis can improve statistics, but simple image analysis techniques give unacceptable results when applied to TEM images due to complex contrast such as bend contours or grain boundary fringes. A more robust image analysis algorithm has been developed and applied to TEM/STEM images to measure the grain size distribution from approximately 10,000 grains. The details of this novel algorithm and its application to real microstructures will be discussed.
3:15 PM U2.5
EFFECT OF Mo DOPING ON FORMATION OF Ti-SILICIDE PHASES STUDIED BY HRTEM. M.A. Gribelyuk
, S.B. Samavedam* and J. Kittl, Texas Instruments Inc., Dallas, TX; *
Massachusetts Institute of Technology, Cambridge, MA.
Titanium silicides have received considerable interest due to their application in submicron CMOS devices. The microstructure of undoped (no Mo) and Mo-doped n+ poly-Si/Ti system after RTA reaction at 650ºC was studied by combination of HRTEM and image simulation. Our results can be summarized as follows: a) In the undoped (no Mo) system a tetragonal Ti5
phase is formed along with C49-TiSi2
at the poly-Si/Ti interface after 10s anneal. Subsequent anneal leads to further growth of C49-TiSi2
and consumption of Ti5
. b) In the Mo-doped system C54-TiSi2
is formed along with tetragonal Ti5
at the poly-Si/Ti interface after 10s anneal, bypassing C49-TiSi2
phase formation. Subsequent anneal leads to further growth of C54-TiSi2
.c) Several unidentified Ti-silicide phases have been observed at the poly-Si/Ti interface in the Mo-doped system only. Our data proves that one of the phases exhibits epitaxial relationship to C54-TiSi2
. This suggests that these phases are responsible for an earlier nucleation of the C54-TiSi2
phase. Our results shed a new light on morphology of novel Ti-silicide structures proposed for deep-submicron devices.
3:30 PM U2.6
TRANSMISSION ELECTRON MICROSCOPY INVESTIGATION OF TITANIUM SILICIDE THIN FILMS. A.F. Myers
, E.B. Steel, L.M. Struck, Surface and Microanalysis Science Division, Chemical Science and Technology Laboratory, NIST Gaithersburg, MD; H.I. Liu, J.A. Burns, MIT Lincoln Laboratory, Lexington, MA.
Titanium silicide films grown on silicon were analyzed by high resolution transmission electron microscopy (HRTEM), selected area electron diffraction (SAED), scanning transmission electron microscopy (STEM), energy dispersive x-ray (EDX) spectroscopy, and electron energy loss spectroscopy (EELS). The films were prepared by sequential rapid thermal annealing (RTA) at 675ºC and 850C of 16-nm-thick sputtered Ti on Si (001) wafers. In some cases, a 20-nm-thick TiN capping layer was deposited on the Ti film before the RTA procedure and was removed after annealing. HRTEM and STEM analysis showed that the silicide films were less than 0.1 m thick, varying from 20 nm for the capped film to 80 nm for the uncapped film. SAED was used to investigate the titanium silicide phases present in the films; more than one phase appears to exist. The results of this microscopy study will be presented.
3:45 PM U2.7
CHARACTERIZATION OF ELECTRICALLY PULSED CHROMIUM DILICIDE FUSABLE LINKS. A.G. Domenicucci
, IBM Microelectronics Division, Hopewell Junction, NY; B. Cunningham, Dominion Semiconductor, Manassas, VA; P. Tsang, Micrus Corporation, Hopewell Junction, NY.
Fusible links, fabricated from silicon rich chromium disilicide thin films, were subjected to voltage pulses in the 3-5 volt range. An optimum voltage existed at which the fuses blew. Transmission electron microscopy(TEM) was used to study the microstructural characteristics of the fuses both before and after the application of the voltage pulses. The TEM characterization, coupled with electrical and physical measurements, revealed that the mechanism underlying the fuse blow was hole current induced Si electromigration. Below the optimum voltage, the amount of Si transported was insufficient to cause fuse rupture. Above the optimum voltage, the current-voltage characteristics of the fuses became nonlinear and a unique sequence of material phases were formed. The composition of the phases suggests that both thermomigration and electromigration processes were operating at voltages above the optimum voltage for fuse blow.
4:00 PM U2.8
MICROSTRUCTURAL CHANGES IN W-POLYCIDE GATES CAPPED WITH A THIN POLYSILICON LAYER. Y.O. Kim
, J. Bevk, W. Mansfield, R. Oplia, and R. Masaitis, Bell Laboratories, Lucent Technologies, Murray Hill, NJ.
Tungsten silicide has been widely used for gate electrodes and interconnections in VLSI applications. Its advantages include excellent thermal stability and high manufacturability, and resistivity about one order of magnitude lower than that of polysilicon. The resistivity of refractory metal silicides is sensitive to their Si to metal ratio as well as to other crystalline characteristics. When tungsten silicide is deposited onto polysilicon subfilms, the excess silicon in the as-grown film is known to diffuse to the interface between WSix
and poly-Si during subsequent annealing after deposition. This reduction of the Si to W ratio results in a lower sheet resistance. We find that sheet resistance of tungsten silicide can be further reduced up to 40 of the films.