Chairs
Dirk D. Brown
Technology Dev Group
Advanced Micro Devices
MS 160
Sunnyvale, CA 94088-3453
408-749-3828
Ad H. Verbruggen
DIMES
Delft Univ of Technology-DIMES
Delft, 2628 CJ NETHERLANDS
31-15-2786124
Cynthia A. Volkert
Max Planck Inst-Metallforschung
Stuttgart, 70174 GERMANY
49-711-2095-123
Symposium Support
*Advanced Micro Devices, Inc.
Proceedings published as Volume 563
of the Materials Research Society
Symposium Proceedings Series.
* Invited paper
SESSION M1/R4: JOINT SESSION:
RELIABILITY OF ULTRATHIN GATE DIELECTRICS
Chair: Cynthia A. Volkert
Tuesday Morning, April 6, 1999
Nob Hill B/C/D (M)
8:30 AM M1.1/R4.1
DIELECTRIC BREAKDOWN OF THIN SiO
2 FILMS IN MOS CAPACITORS AFTER FOWLER -NORDHEIM OR HOT ELECTRON STRESS. S. Lombardo , C. Spinella, A. La Magna, CNR-IMETEM, Catania, ITALY; C. Gerardi, STMicroelectronics, Central R & D, Catania, ITALY; F. Crupi, University of Pisa, Dept. of Electrical Engineering, Pisa, ITALY.
We have studied dielectric breakdown of gate oxides of thickness in the 35 - 5.6 nm range in n+ poly-Si / SiO2 / Si MOS capacitors after either constant voltage or constant current stress and in conditions of either Fowler-Nordheim tunneling or hot electron injection in the oxide. The wearout phase preceding breakdown has been characterized by following the evolution of quasi-static C-V curves and of stress-induced leakage current (SILC) as a function of the injected charge. Moreover, the transient during hard breakdown and in particular the time dependence of voltage, current, and power during the transient have been monitored with a 2 ns time resolution. The corresponding thermal damage has been characterized by transmission electron microscopy. It is shown that the transient during which hard breakdown occurs is characterized by a power dissipation of the order of W/cm2 through a small region which, during this phase, is subjected to rapid melting followed by solidification in times of the order of a few nanoseconds. Moreover, the critical values observed immediately before breakdown of interface trap density at Si/SiO2 interface and of trapped charge in the oxide, the critical SILC level, the peak power dissipated during hard breakdown, and the amount of consequent thermal damage are determined as a function of oxide thickness. In addition, stress conditions leading to soft breakdown have been clearly defined and characterized.
8:45 AM *M1.2/R4.2
A MICROSCOPIC PERSPECTIVE OF HOT ELECTRON EFFECTS AND RELIABILITY ISSUES IN ULTRATHIN GATE OXIDES. R. Ludeke , IBM T. J. Watson Research Center, Yorktown Heights, NY; Huajun Wen, IBM Austin Research Laboratory, Austin, TX; Andreas Schenk, Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich, SWITZERLAND.
Most of our present knowledge of hot electron transport through gate oxides, including their role in defect generation and eventual breakdown, has been obtained from transport measurements (I-V and C V) on large-area MOS devices and capacitor structures. Yet such processes are basically microscopic phenomena that occur on an atomic scale, which renders their properties difficult to deduce solely from a macroscopic perspective. We have taken a different approach at characterizing hot electron transport on a microscopic scale by using the high lateral confinement of electrons injected into the thin (1.5-4 nm) metal ``gate'' of a MOS capacitor with the tip of a scanning tunneling microscope (STM); the technique is called Ballistic Electron Emission Microscopy (BEEM). When the energy of the injected electrons, determined by the bias of the STM tip relative to the gate, exceeds the potential barrier between the gate and the oxide, the electrons can propagate in the conduction band of the oxide and emerge in the Si substrate as a collector current. The barrier height, and hence the collector current threshold, is particularly sensitive to any local oxide charge encountered by the transiting electrons. The charge, which may exhibit either polarity, arises from filled traps of both process induced defects, and, for sufficiently energetic electrons, impact generated traps. Their density and in-depth distribution has been determined. Local trap densities in the mid-to-high 10E13/cm2 have been observed. Yet severe stressing at injected fluences and energies far exceeding those leading up to oxide breakdown on macroscopic samples, have generally failed to break down the oxide locally. We conclude from our studies that intrinsic breakdown in SiO2 has not yet been achieved for oxides <10 nm in thickness, and that most if not all observed breakdowns are due to still unidentified defects dilutely dispersed in the oxide. BEEM also lends itself to a direct re-evaluation of fundamental oxide parameters of relevance in transport simulations, such as the dynamic dielectric constant, and the effective conduction band mass. The latter, including its energy dispersion, has been obtained from quantum interference effects observed in the collector current for 2-3 nm oxides.
9:15 AM M1.3/R4.3
ENHANCED DEGRADATION IN P+ -POLY PMOSFETS WITH OXYNITRIDE GATE DIELECTRICS UNDER HOT-HOLE INJECTION. Y.Y. Chen , M. Gardner1, J. Fulford1, D. Wristers1, A.B. Joshi2, L. Chung2 and D.L. Kwong, Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas, Austin, TX; 1Advanced Micro Devices, Austin, TX; 2Rockwell Semiconductor Systems, Newport Beach, CA.
In this paper, a significant degradation under hot hole injection is observed in P+-poly PMOSFETs with oxynitride gate dielectrics. Both oxynitrides formed by gate oxide grown on Nitrogen Implanted Si Substrates (NISS) and NO-annealed SiO2 oxynitride gate dielectrics are used and compared to control SiO2 gate dielectrics of identical thicknesses. For PMOSFETs with control SiO2, the maximum device degradation occurs at the Vg@Ig,max stress condition which is consistent with the conventional degradation mode. However, for NISS and NO-annealed PMOSFETs, the most severe degradation happens at Vg=Vd stressing. Significant Gm degradation and Vt shift are observed in NISS and NO-annealed PMOSFETs under hot hole injection stressing (Vg=Vd). To further confirm the enhanced degradation without considering the effects caused by boron penetration, the hot-hole injection condition at Vg=Vt is performed on N+-poly NMOSFETs. The hot-hole stressing mainly causes Gm degradation in 36Å NMOSFETs and it is worse for NISS NMOSFETs. On the other hand, Vt shift is also larger for 55Å NO-annealed NMOSFETs processed with higher nitridation flow. A physical model responsible for such enhanced degradation in PMOSFETs with oxynitride gate dielectric is proposed. When nitrogen is incorporated into the gate oxide, its concentration peaks at the SiO2/Si interface. As a result, this nitrogen-rich layer has higher dielectric constant and smaller bandgap than the bulk SiO2. The bandgap reduction of the nitrogen-rich layer at the SiO2/Si interface lowers the injection barrier height, particularly for holes. The 4eV bandgap difference between SiO2and Si3N4 contributes to only 1eV electron barrier height lowering but 3eV hole barrier height lowering. Thus the hole injection barrier height is lowered in oxynitride due to the [N] at the SiO2/Si interface. As a result, enhanced hole injection under hot hole injection stress causes enhanced degradation in PMOSFETs with oxynitride gate dielectrics. Our discovery plays a key role in the future applications of high-k dielectric materials.
9:30 AM *M1.4/R4.4
STRESS-INDUCED LEAKAGE CURRENTS IN ULTRA-THIN GATE OXIDES. E. Cartier , IBM Research Division, T.J. Watson Research Center, Yorktown Heigths, NY.?
The physics of stress-induced leakage currents (SILC) has attracted much attention recently. This interest is to a large part stimulated by the practical implication of these currents on the performance of electronic devices, nonvolatile memories in particular and by the possibilities to learn about the degradation behavior and possibly the lifetime of advanced logic devices. While practical use can be made of SILC measurements without a complete understanding of the physical/chemical processes causing these currents and without understanding the details of the conduction mechanisms, it is obvious, that its usefulness may greatly increase with the advances made in our basic understanding of the SILC phenomena, which at this point in time is fare from complete.
In this presentation, an outline of the general phenomenology of SILC generation and conduction during homogeneous stress of ultra-thin gate insulators will be given, providing an overview on the complex phenomena. Some practical applications of SILC measurements will than be discussed, such as their usefulness for lifetime evaluation of future CMOS device technologies. This example will also illustrate the need for a deeper understanding of SILC generation and conduction. If time permits, the presentation will be concluded with an update on recent advances in the understanding of SILC generation and conduction mechanisms.
10:15 AM M1.5/R4.5
RELATIONSHIP BETWEEN INTERFACIAL ROUGHNESS AND DIELECTRIC RELIABILITY FOR SILICON OXYNITRIDE GATE DIELECTRICS PROCESSED WITH NITRIC OXIDE. J. Sapjeta , J.P. Chang, M.L. Green, P.J. Silverman, T.W. Sorsch, B.E. Weir, Bell Laboratories Lucent Technologies, Murray Hill, NJ; W. Gladden, Y. Ma, Bell Laboratories Lucent Technologies, Orlando, FL; W.N. Lennard, University of Western Ontario, London, Ontario, CANADA.
Si oxynitrides are leading candidates to replace conventional oxides as ultrathin gate dielectrics in future generations of MOS devices, due to their improved reliability and ability to suppress boron penetration. Protection against boron penetration at the SiO2/polysilicon interface and improved hot carrier resistance at the Si/SiO2 interface can be best obtained by placing the bulk of the nitrogen at these two interfaces. One method of profiling nitrogen in this manner is to use a three-step thermal process consisting of oxynitridation in NO, followed by reoxidation in O2, and subsequent reoxynitridation in NO (NO/O2/NO). Since the reliability of gate dielectrics is sensitive to Si/SiO2 interface quality, it is important to understand the effect of such processing on interface roughness. The present study uses atomic force microscopy to characterize oxidation- and oxynitridation-induced microroughness at the Si/SiO2 interface. Furnace-grown films of 4 nm thickness have been prepared to compare the effect of NO/O2/NO, O2/NO, and O2 processing schemes. Experiments were performed to determine the influence of gas sequence and film nitrogen content on interface roughness. An initial NO step roughens the interface, as does subsequent reoxidation. Increased NO exposure yields a greater nitrogen content (1 - 4 at. ) and a concomitant increase in interface roughness. These films show a degradation in charge to breakdown (Qbd, a reliability metric) of an order of magnitude when compared with similarly prepared O2-oxide films. For wafers that received O2/NO processing, interface roughening after oxidation is negligible, nitrogen content can be several times less than that for NO-first films, and charge to breakdown is comparable to that of pure oxide. We find that the oxynitride reliability depends on the exact processing scheme for incorporating nitrogen into SiO2. If the interfacial RMS roughness exceeds 1.5 , reliability will decrease sharply.
10:30 AM M1.6/R4.6
TRIGGERING OF THE SOFT BREAKDOWN PHENOMENON IN THIN GATE OXIDE FILMS STUDIED BY MERCURY PROBE SYSTEM. Serge Evseev and Antonio Cacciato, Philips Semiconductors, Nijmegen, THE NETHERLANDS.
The breakdown of ultra-thin gate oxide layers is investigated by using fast-feedback Hg-gate measurements to perform Ramped Voltage Stress (RVS) and Exponentially Ramped Current Stress (ERCS) tests. Several parameters have been varied in the ERCS test: oxide thickness (4nm, 5nm, 6nm and 7nm), capacitance area (0.12cm2 and 0.023cm2) and initial injected current (5 10-5 A and 5 10-4 A). The source-measure unit of the SSM5100 Mercury probe (Keithley, Model 237) is capable to ramp up the current over 3 decades with a compliance limit at 100mA. The triggering of soft breakdown is demonstrated. It is found that the soft breakdown probability has dependence on oxide thickness, capacitance area, stressing current density and dielectric strength of the oxide. In particular, it is shown that for physical thickness of 4 or 5nm, the fraction of measured points on which soft breakdown occurs decreases if the injected current density increases. By further increase of the current density the soft breakdown can be completely eliminated. On the contrary, for 6 and 7nm oxides hard breakdown was always observed for similar changes in the injected current. The risks that soft breakdown can be easily overlooked and ultra-thin oxide reliability overestimated in conventional ERCS tests are discussed. The statistical distributions of soft and hard (thermal) breakdowns are compared.
10:45 AM *M1.7/R4.7
SOFT BREAKDOWN IN ULTRA-THIN DIELECTRICS. B.E. Weir , P.J. Silverman, G.B. Alers, D. Monroe, M.A. Alam, T.W. Sorsch, M.L. Green, G.L. Timp, Y. Ma, M. Frei, F. Baumann, C.T. Liu, J.D. Bude and K.S. Krisch.
An understanding of dielectric breakdown mechanisms is critical for continued oxide scaling. Although working transistors have been demonstrated with sub-2nm silicon dioxide gate dielectrics, the manufacturability of such devices hinges on the reliability of the oxides. Predictions based on dielectric breakdown studies claim that silicon dioxide will not be usable beyond 2.7nm. However, we have shown that as oxides become thinner and operating voltages become lower, a fundamentally different mode of dielectric breakdown occurs. This has been called soft breakdown and is considered to be the formation of a small, localized tunneling path through a dielectric. We will demonstrate that soft breakdown in ultra-thin oxides is an intrinsic phenomenon distinct from the electric breakdown observed in thicker oxides. For transistors with 2-nm gate oxides, threshold voltage and maximum transconductance are not affected by soft breakdown, implying that circuits may continue to operate after soft breakdown. The increase in gate current or voltage noise associated with soft breakdown is not a limiting factor for many applications. The implications of such a noise increase will be discussed. In order to make comparisons of ultra-thin oxide quality, it is important to be able to reliably detect soft breakdown. J-ramp, a commonly used ramped-current measurement to determine oxide quality is sometimes unable to detect soft breakdown in ultra-thin oxides. We will demonstrate the incorporation of noise measurements in a commercial J-ramp algorithm which enables consistent detection of soft breakdown.
11:15 AM M1.8/R4.8
Abstract Withdrawn.
11:30 AM M1.9/R4.9
MODELING SOFT BREAKDOWN OF ULTRA-THIN GATE OXIDE LAYERS. Michel Houssa , P.W. Mertens and M.M. Heyns, IMEC, Advanced Semiconductor Processing Division, Leuven, BELGIUM.
The electrical characteristics of metal-oxide-semiconductor devices with an ultra-thin gate oxide layer are investigated. After the occurrence of soft breakdown, which is observed during constant current stress of the devices, the gate current increases by 3 to 4 orders of magnitudes and behaves like a power law of the applied gate voltage. Besides, this large gate current increase is followed by complex fluctuations in the time dependence of the gate voltage as the MOS device is stressed further. In this work, it is shown that the power law behavior of the gate current observed after soft breakdown is due to the formation of a percolation path between the electron traps generated in the gate oxide layer during electrical stress of the devices. A simple model is proposed which accounts for the current-voltage characteristics between two neighbor trapping sites as well as a distribution of percolation thresholds in these (finite size) ultra-thin silicon dioxide layers. The predictions of the model are in good agreement with the experimental results and lead to a better description of the data than previously reported models. The time dependence of the gate voltage signal after soft breakdown is next analysed. It is shown that the fluctuations in the gate voltage are non-gaussian and that long-range correlations exist in the system. These results can be explained by a dynamic percolation model, taking into account the trapping-detrapping of electrons within the percolation cluster formed at soft breakdown.
11:45 AM M1.10/R4.10
BREAKDOWN CHARACTERISTICS OF ULTRA-THIN GATE OXIDES CAUSED BY PLASMA CHARGING. Chi-Chun Chen , Chun-Yen Chang, Chao-Hsing Chien, Tiao-Yuan Huang, Natl Chiao Tung Univ, Inst of Electronics, Hsinchu, TAIWAN, R.O.C.; Horng-Chih Lin, Natl Nano Dev Lab, Hsinchu, TAIWAN, R.O.C.
Breakdown characteristics of ultra-thin gate oxides caused by plasma charging were investigated. It is observed that both hard and soft breakdown events could be induced in antenna devices with 4.2 nm-thick gate oxide. As oxide thickness is further thinned down to 2.5nm, however, only soft breakdown is observed. Such findings are consistent with the results obtained by constant current stressing. It is also found that the oxide degradation after soft-breakdown does not significantly affect transistor's drain current characteristics. Therefore, traditional methods of monitoring transistor parameters, such as threshold voltage, subthreshold slope and transconductance, are no longer appropriate for detecting the charging damage in ultra-thin gate oxides. As a result, some destructive methods, such as the charge-to-breakdown measurement, hot carrier stressing, or noise characterization technique, are necessary for evaluating plasma damage in ultra-thin oxides. Overall, though the plasma charging damage does not result in significant degradation of the drain current characteristics of the device, however, it does degrade device performance by increasing noise as well as gate leakage, which may impact certain circuit applications. Therefore, careful characterization of plasma charging damage in ultra-thin gate oxide remains very important and efforts should still be made to minimize the damage.
SESSION M2: SOLDER AND BARRIER LAYER RELIABILITY
Chairs: Dirk D. Brown and Lorraine C. Wang
Tuesday Afternoon, April 6, 1999
Salon 10 (M)
1:30 PM M2.1
DECREASE IN GROWTH KINETIC OF THE TiAl
3 FORMATION FROM THIN FILMS USED IN MICROELECTRONICS. Xavier Federspiel , Michel Ignat, Frédéric Voiron, LTPCM/INPG, Grenoble, FRANCE; Harry Fujimoto, Tom Marieb, Intel Components Research, Santa Clara, CA.
The interfacial reactions that occur during aging integrated circuits can change their properties and produce failures. It is then crucial to understand the phenomena that control these reactions and also important to know their kinetics. The object of this work was to characterize the role of impurities and grain size on the growth rate of TiAl3 from Al/Ti interface. The kinetic study consisted of annealing and electrical measurements. These data were correlated with microstructural and composition evolution as observed using TEM, SIMS and AES. The kinetic data were fit using a combination of two methods. Classical kinetic models (parabollic, Avrami, Aronson) were complemented by a more detailed simulation, which accounted for nucleation frequency, grain boundary diffusion and crystal anisotropy. This simulation consist of a computer program that simulates the growing of individual grains of the intermetallic in 2D cross section or in 3D by reconstructing the surface from a 2D top view. The role of the impurities is discussed and the model is compared to the TEM microstructures.
1:45 PM M2.2
DIFFUSION BARRIER CHARACTERISTICS OF ZIRCONIUM DIBORIDE FILMS GROWN BY REMOTE PLASMA CVD. Jung H. Sung , John R. Abelson, University of Illinois, Dept of Materials Science and Engineering, Urbana, IL; Dean M. Goedde, Greg S. Girolami, University of Illinois, Dept of Chemistry, Urbana, IL.
Zirconium diboride is potentially suitable as an advanced diffusion barrier in ULSI circuits and high temperature electronics because of its low electrical resistivity, refractory melting temperature, and high chemical inertness. We report the growth of device quality zirconium diboride films using Zr(BH4)4 precursor and a remote hydrogen plasma. At a substrate temperature of 150C, the film resistivity is 80 -cm, and the step coverage of trench substrates appears highly conformal. We show that the H plasma suppresses the incorporation of oxygen from the vacuum background in the form of B2O3 and greatly improves the film microstructure. To analyze the diffusion barrier properties, metal/ZrB2/Si sandwich structures are fabricated and annealed at various temperatures. We will present elemental depth profiles as a function of contact metal, diffusion barrier thickness and microstructure, and discuss the future applications of ZrB2.
2:00 PM M2.3
HOMOGENEOUS ULTRATHIN DIFFUSION BARRIERS DEPOSITED ON LOW DIELECTRIC CONSTANT POLYMERS. M. Kiene , P.P. Abramowitz, P.S. Ho, Institute for Materials Science, University of Texas, Austin, TX.
TiN and TaN thin films are proposed as barrier layers between copper interconnects and low dielectric constant (low-k) polymers. As the barrier layer thickness is scaled down, the uniformity and morphology of these films will be severely affected by the nitride-polymer interface and become an important issue for the reliability of the whole interconnect structure. In order to evaluate nitride formation and the interfacial chemistry we deposited TiN and TaN on fully cured low-k polymers by two different techniques: reactive evaporation of the metal in nitrogen ambient and by ion assisted reactive deposition using a low energy (100eV) nitrogen ion beam during evaporation. Photoelectron spectra were recorded in situ for metal coverages from 0.1nm until bulk like metal or metal nitride spectra were obtained. Nitride concentrations, extracted from the photoelectron spectra, show that even though very similar nitride films are produced by both techniques for thicker films (>5nm) we only find significant amounts of nitride at the interface in the ion assisted case. Thinner films formed by reactive evaporation in nitrogen ambient were very similar to those where the pure metal was deposited and were dominated by the formation of compounds with carbon and oxygen from the polymer. This shows that the composition of barrier layers can be drastically altered near the polymer interface. Low energy ions in contrast allow the growth of more homogeneous films which can significantly improve the reliability of copper based high density interconnects.
2:15 PM M2.4
THE INFLUENCE OF SI SURFACE PLASMA INDUCED DEFECTS ON THE MICROSTRUCTURE AND FAILURE OF TI-SI-N CU DIFFUSION BARRIERS. W.F. McArthur , K.M. Ring, K.L. Kavanagh, Department of Electrical Engineering Materials Science Program, University of California-San Diego, CA.
Ti-Si-N is an effective diffusion barrier in Cu metallized semiconductors. Metal-Si-N ternary amorphous materials are believed to act as diffusion barriers up to their crystallization temperature. Ti-Si-N films are an amorphous matrix with imbedded crystals of TiN. When annealed, TiN crystals nucleate and grow. Failure is associated with grain boundary diffusion of Cu through the crystallized film. We prepare thin films of Ti-Si-N by RF magnetron co-sputtering of Ti and Si in Ar/N2. Si pn-junction diodes metallized with 20nm films of Ti29Si18N53/Cu fail (increased reverse leakage current) at temperatures between 400 and 850C depending on the extent of crystallization of the as-deposited film. Transmission electron microscopy (TEM) images and diffraction patterns show that films deposited on plasma etched Si substrates have a higher extent of crystallization than films deposited on unetched Si substrates. Correlated to the TEM data is diode I-V data for samples which have been subjected to a longer contact plasma over-etch. These samples fail at 400C. Samples which have been etched using a minimum allowable over-etch do not fail until 850C. The extent of crystallization of the as-deposited Ti-Si-N film is presumed to be controlled by the damage imparted on the Si contact surface by the plasma etch.
2:30 PM M2.5
TiB2 AND Ti-B-N AS DIFFUSION BARRIERS FOR <Si>/Cu METALLIZATION. J.L. Wang and J.S. Chen , National Cheng Kung University, Dept. Materials Science and Engineering, Tainan, TAIWAN.
TiB2 and Ti-B-N thin films were deposited by sputtering on (100) Si substrates and were tested as diffusion barriers with a Cu overlayer. Metallurgical interactions of <Si>/TiB2/Cu and <Si>/Ti-B N/Cu samples annealed at 400-800C for 30 min were investigated by grazing angle X-ray diffraction. Auger electron spectroscopy (AES), and scanning electron microscopy (SEM) for phase identification elemental distribution and surface morphology. Sheet resistance and reverse-biased diode leakage current were also measured for electrical characterization. As-deposited TiB2 and Ti-B-N thin films are amorphous. X-ray diffraction shows peaks of Cu crystallites only for the <Si>/TiB2/Cu and <Si>/Ti-B-N/Cu samples annealed at 800C, indicating that there is no caustic interfacial reaction for both systems. Variation of sheet resistance with annealing temperature is insignificant for both <Si>/TiB2/Cu and <Si>/Ti-B-N/Cu samples, in spite of appearance hillocks and openings on the surface of Cu films.
3:15 PM M2.6
THE THERMAL RESISTANCE OF ALUMINUM/TITANIUM MULTILAYER THIN FILMS AND THEIR INTERFACES. Daniel Josell , Eduardo Gonzalez, Grady White, National Institute of Standards and Technology, Gaithersburg, MD.
As the individual layers within electronic materials become thinner, heat flow predictions based on bulk properties become increasingly inaccurate. This inaccuracy arises in part because the thermal transport properties of thin film materials can differ from those of bulk materials. In addition, the thermal resistance associated with interfaces between layers becomes more significant as the layers become thinner. Accurate modeling of heat flow in future devices will require at least empirical understanding of these individual effects. We have, therefore, measured the thermal diffusivity (thermal conductivity divided by specific heat per unit volume) of Al/Ti multilayer thin films prepared by electron beam evaporation. All tested films were 3.1 m thick, with each specimen possessing a particular bilayer thickness (10 nm or more). The thermal diffusivity was measured both perpendicular and parallel to the plane of the layers using the Mirage (Photothermal Deflection) Technique. Noninterfacial effects (e.g., systematic variation of microstructure with layer thickness) were determined from the in-plane thermal diffusivities. The interfacial thermal resistance was determined from the dependence of the perpendicular thermal diffusivity on bilayer thickness, suitably corrected for the noninterfacial effects. Uncorrected for, these noninterfacial effects lead to an overly large value of the interface resistance. The Al/Ti materials system was selected because such bilayers form the ohmic contacts to GaN and other devices.
3:30 PM M2.7
RESISTANCE INCREASE AND LOCAL JOULE HEATING IN VOIDED METAL INTERCONNECTS. Y.L. Shen , W. Li, Dept of Mechanical Engineering, The University of New Mexico, Albuquerque, NM.
In multilayer metal interconnects, thin redundant layers such as TiN directly above and below Al lines can act as alternative conducting paths. In cases when large enough voids caused by electromigration and/or thermal stress form in Al, the current can be shunted to the TiN layers. This has been regarded as a built-in reliability feature. As higher-performance devices are being developed, the reliability of this feature itself becomes a question. When TiN becomes a major conducting path, the overall resistance of the circuit increases significantly, and enhanced Joule heating near the void can be expected.