Meetings & Events

Spring 1999 logo1999 MRS Spring Meeting & Exhibit

April 5-9, 1999 | San Francisco
Meeting Chairs: Katayun Barmak, James S. Speck, Raymond T. Tung, Paul D. Calvert

Symposium R—Ultrathin SiO2 and High-K Materials for ULSI Gate Dielectrics


Martin Green 
Lucent Technologies, Bell Labs 
Rm 2D-316B 
Murray Hill, NJ 07974 

Takeo Hattori
Dept of Elect & Electronic Engr
Musashi Inst of Technology
Tokyo, 158-8557 JAPAN
81-33703-3111 x2768

Howard Huff 
Austin, TX 78741-6499 

Gerald Lucovsky
Physics Dept
North Carolina State Univ
405 E Cox Hall 
Raleigh, NC 27695-8202

Curt Richter 
Semiconductor Electronics Division 
National Inst of Standards & Technology 
Gaithersburg, MD 20899 

Symposium Support 
*Hitachi, Ltd. 
*Mitsubishi Electric Corporation 
*NEC Corporation 
*SONY Corporation 
*Texas Instruments, Tsukuba R&D Center 
*Toshiba Corporation 

Proceedings published as Volume 567 
of the Materials Research Society 
Symposium Proceedings Series.

* Invited paper
Chair: Martin L. Green 
Monday Morning, April 5, 1999 
Nob Hill B/C/D (M)
8:30 AM *R1.1 
LOW TEMPERATURE FORMATION OF SiO2 AND HIGH-K DIELECTRICS FOR ULSI IN 21st CENTURY. Tadahiro Ohmi , New Industry Creation Hatchery Center, Tohoku University, Sendai, JAPAN; Mosaki Hirayama and Ryu Kaihara, Dept of Electronics, Graudate School of Engineering, Tohoku University, Sendai, JAPAN.

High functional ULSIs are strictly required to drastically improve total system performance in 21st century. In order to realize these targets, the author in planning to introduce metal gate high dielectric gate insulator SOI ULSIs having a metal layer under the buried insulator layer where the high speed signal pulse propagation performance is improved up to 0.1 nsec pulses (corresponding 10 GHz clock rate operation) and the substrate surface potential is maintained at constant level due to the very low resistance of the substrate itself even for such very high speed operation up to 10 GHz clock rate, I.E., this means a possibility of very accurate high speed binary-multiple valued-analog operation by suppressing cross-talk-error. 
Substrates themselves include a metal layer, so that total low temperature processes are essentially needed in ULSI manufacturing in 21st century. Very well regulated high density plasma source is crucial for improving the process quality even at low temperatures as well as ultraclean processings. So far, 300C single silicon epitaxy has been developed by introducing Ar, Kr and Xe ion bombardment having energies less than 20eV, as well as low temperature annealing of ion implanted source and drain region (n+ and p+ region) less than 550C by introducing metallic contamination free ion implantation to bare silicon surface. Very high quality and low temperature direct oxidation of silicon surface at 300C to 400C has been developed by introducing oxygen radical oxidation where oxygen radicals are obtained by microwave excited high density plasma of He/O2 ambience. Oxide film thickness is controlled up to 15nm by this oxygen radical low temperature oxidation technology. It is already confirmed so far that the breakdown field intensity of this oxide is greater than 15 MV/cm and the charge to breakdown(QBD) a larger than 10C/cm2 at a stress current density of 0. 1A/cm2. Same high density plasma technology is applied to silicon surface direct nutridation by using Ar/N2/H2 gas ambience and/or Ar/NH3. Nitride film thickness is controlled up to 5 to 6nm. The breakdown field intusity of this nitride film is around 15MV/cm and the value of QBD is up to 100C/cm2. This microwave excited high density plasma is characterized by its very high density higher than 11012cm-3, low electron temperature less than 1eV and very low plasma potential less than 9V. Thus, this high density plasma process exhibits very excellent process qualities such as metallic contamination free process free from chamber wall sputtering and damage free process having very low bombardment ion energies less than 7eV. This high density plasma process is now just applied to the formation of high dielectric such as BST and ferroelectric film such as STNO by combining very advanced gas supply system consisting of newly developed vaporizer, flow control system and electrically controlled valve, and advanced gas pumping system where various source gas concentrations in the process chamber are very accurately controlled from the first atomic larger deposition.

9:00 AM R1.2 
GROWTH OF THIN SiO2 BY SPIKE RAPID THERMAL OXIDATION. A.T. Fiory , Bell Laboratories Lucent Technologies, Inc., Murray Hill, NJ.

Wafers prepared with HF and RCA cleaning were oxidized in an atmospheric pressure O2 ambient in an incandescent-lamp processor. Minimal effective oxidation times of several seconds were obtained by rapidly heating wafers at rates up to 150C/sec and then turning off lamp power just as the desired peak temperature is approached. Cooling rate varies up to about 80C/sec. Film thickness obtained by this method ranges from about 16  for peak temperature of 1000C to about 22  for peak temperature of 1100C. Oxidation process uniformity under 1% at one standard deviation over 150 mm wafers, equivalent to 2.5C temperature variation, was obtained by optimizing relative power ratios to the lamps.

9:15 AM R1.3 
ULTRATHIN SILICON DIOXIDE FORMATION BY PURE OZONE ON ULTRAFLAT SI SURFACE. Akira Kurokawa , Tatsuro Maeda, Kunihiro Sakamoto, Atsushi Ando, Hiroshi Itoh, Shingo Ichimura, Electrotechnical Laboratory, Tsukuba, JAPAN.

This paper reports on ozone oxidation of an atomically flat silicon surface to form ultrathin oxide. To achieve our final goal to make an ultrathin oxide with device grade quality, we have focussed on an oxidant, the initial roughness of substrate surface and the roughness of oxidized surface. We used pure ozone as oxidant because ozone is known to be highly active oxidant and is expected to make a dense oxide at low temperature. An ozone jet generator supplied ozone gas and concentration of accumulated ozone in the generator was more than 99% and supplied pressure was controlled between 10-4Pa to 102Pa. To prepare the super flat surface we made a homoepitaxial Si(100) substrate, because the roughness of initial surface will control the roughness of interface between oxide layer and substrate layer when the oxide is ultrathin. The initial structure of epitaxial surface was confirmed by RHHED on the long-range order and confirmed by AFM on the local structure. The results showed that the surface was super flat and only a step-terrace structure was observed. The super flat surface was oxidized with pure ozone to form SiO2 layer as thick as 1nm. The thickness of oxide was confirmed by XPS and an eliipsometer. The temperatures for ozone oxidation were room temperature and 300C which were lower than that for typical thermal oxidation with oxygen. After the oxidation the surface were observed with AFM. The AFM images showed still step-terrace structure in which the height of each step corresponded to that of step height before oxidation. The images showed neither spike nor vote on the terrace. From the above results we concluded that the ozone did not make the surface rough to form ultrathin oxide and that ozone oxidation proceeded in the layer-by-layer growth manner.

9:30 AM R1.4 
ULTRA THIN OXIDE FILM USING RADICAL OXYGEN IN UHV SYSTEM. Koji Watanabe , Toru Tatsumi and Shigeru Kimura, NEC Corporation, Silicon Systems Research Laboratories, Tsukuba, JAPAN.

The gate oxide thickness in 0.18 um devices rule requires under 2.0 nm. It is important to control exactly the thickness of these ultra thin oxides. We use radical oxygen by ECR plasma to make an ultra thin oxide film in UHV system. In this result, it is easy to control the thickness at Tsub = 750 C under 2.0 nm using radical oxygen in 5.0x10-3 Torr. The uniformity on the 6-inch wafer is +/-0.01 nm, and the interface roughness is 0.106 nm as RMS. Si(100) wafers were treated with the SC-1 cleaning followed by HF dipping. Then annealing at 900 C for 5 min. was carried out in UHV system under 1.0x10-9 Torr to remove the native oxide and to flatten surface. With subsequent annealing, an oxide film was grown in a radical oxygen from 5.0x10-4 to 5.0x10-3 Torr using ECR plasma at Tsub = 750 C. As in these conditions, the oxide thickness increases gradually to 2.0 nm for a few minutes, thus we can easily control the thickness by radical oxidation time. Furthermore, the oxide density is measured by X-ray scattering reflectivity. A high density of oxide film is necessary for low leak current. The density increases from 2.26 to 2.46 g/cm3 as the oxygen pressure increases from 5.0x10-4 Torr to 5.0x10-3 Torr. The density of radical oxide annealed in oxygen molecule at Tsub = 750 C also increases, without increasing the oxide thickness. The first insertion of an oxygen atom in first layer of Si has a much higher energy barrier than the next insertion in same layer. The radical oxygen can pass through this higher energy barrier, then the radical oxygen or oxygen fill the oxide layers. From this mechanism, we can control the oxide thickness and density separately under 2.0 nm by radical oxidation time and annealing time in oxygen gas. We expect that radical oxidation in low pressure is most suitable for the future ultra thin gate oxidation.

10:00 AM *R1.5 
PROGRESS TOWARD 10nm CMOS DEVICES. Gregory Timp , Bell Laboratories, Lucent Technologies, Murray Hill, NJ.

One of the primary means for improving performance and increasing the scale of integration in an integrated circuit is the miniaturization of the devices and wires that comprise it. So far, the guiding principal for miniaturization has been the scaling of successful device designs to smaller dimensions. The SIA roadmap projects that future gains in performance will accrue from this approach, and while there may be no phyiscal, compelling reason why the SIA targets cannot be achieved, an accurate assessment of the limiting performance that can be derived from scaling conventional CMOS is crucial for identifying the principal impediments, and for developing alternative technologies. In our attempts to scale the MOSFET toward 30nm gate lengths using a 0.7nm gate oxide thickness and 15nm junctions, we have achieved phenomenal performance: i.e. with an SiO2 thickness of 1.3nm and a gate length of 60nm, we have produced nMOSFETs with a 1.8mA/m drive current at 1.5V, and pMOSFETs with a 0.3mA/m drive at -1.5V. We have achieved this performance with a low gate leakage current (20nA/m2), without noticeable boron penetration through the gate dielectric, and with negligible penetration of the gate oxide etch into the underlying silicon substrate. However, for SiO2 thicknesses less than 1.3nm, we find that the drive current performance does not improve, while the gate leakage current increases exponentially (due to direct tunneling) and it becomes increasing difficult to reproducibly stop the gate stack etch on the hyperthin oxide. To be practical, an alternative gate dielectric must exceed the criteria we have established with SiO2 at a thickness of 1.3nm.

10:30 AM R1.6 
LOW DAMAGE NITRIDATION OF SILICON OXIDE SURFACES BY REMOTE-PLASMA-EXCITED NITROGEN. Yoji Saito , North Carolina State Univ, Dept of Physics, Raleigh, NC; Ukyo Mori, Seikei Univ, Dept of Electric Engineering and Electronics, Tokyo, JAPAN.

Nitrogen incorporation into the silicon dioxide gate dielecric at the polycrystalline silicon gate interface is required for preventing the transport of boron to the substrate in MOS devices. We have incorporated a significant density of nitrogen only near the top surfaces of thermally or remote-plasma grown oxides by surface fluorination at room temperature followed by an atomic nitrogen treatment at temperatures between 350-750 C. The process gases contain no hydrogen, which can induce electronic traps in the films. The thin oxide films, 5-30 nm thick, formed on silicon substrates were exposed to unexcited F2 diluted in He for 1 min, where the partial pressure of F2 was 0.01 Torr. Then, N2 gas was introduced into the reaction chamber through a plasma discharge tube: the total pressure was maintained 1 Torr and the applied microwave power (2.45GHz) was 90 W. The typical nitridation time was 60 min. Atomic force microscopy measurements show that the surface roughness is improved during the nitridation process. We fabricated MOS devices using the nitrided oxide films without hydrogenation, and measured capacitance-voltage, C-V, characteristics. The density of nitridation induced interface defects in the MOS device was estimated to be below 2  1010cm-2 essentially the same as for conventional oxide films. The bonding of nitrogen atoms has been studied by x-ray photoelectron spectroscopy. The proposed technique identifies a unique process for obtaining high quality ultrathin dielectrics.

10:45 AM R1.7 

The placement of nitrogen within the gate oxide can serve as a highly effective barrier to boron penetration in dual gate CMOS applications. Plasma immersion ion implantation has been employed to controllably place nitrogen ions from an inductively coupled plasma into a thin furnace grown gate oxide 2.0nm thick. The implant energies can be controlled to extremely low values to ensure nitrogen implantation mainly within the oxide. Rapid thermal annealing is essential in repairing any damage to the silicon dioxide and incorporating the nitrogen into the oxide matrix prior to gate polysilicon deposition. Capacitance-voltage measurements of capacitors made with BF2+ implanted gates throughout a series of furnace anneals demonstrates the efficiency for blocking boron compared to non-nitrided oxides and to re-oxidized NO oxides of similar thickness. With this technique, the dose can be tailored to achieve the blocking necessary for a given process flow, and the depth can be controlled to avoid nitrogen pile-up at the silicon to silicon oxide interface, which degrades the carrier mobility and device performance. 

Chair: Gerald Lucovsky 
Monday Morning, April 5, 1999 
Nob Hill B/C/D (M)
11:00 AM *R2.1 
JVD SILICON NITRIDE AND TITANIUM OXIDE AS GATE DIELECTRICS. T.P. Ma , Yale University, Dept of Electrical Engineering, New Haven, CT.

Ultra-thin gate dielectrics made of JVD (jet-vapor deposited) silicon nitride (abbreviated SiN) and titanium oxide (abbreviated TiO) will be the focus of this talk. First, the JVD technique will be briefly reviewed, and the factors that affect the film quality will be discussed. The properties of JVD silicon nitride films will then be presented. It will be shown that the most attractive properties of the JVD silicon nitride as a gate dielectric include low leakage current, high resistance to boron penetration, low stress-induced leakage current (SILC), high breakdown strength, and competitive transistor characteristics. The properties of the JVD TiO/SiN stack dielectric, in which the SiN layer serves as an interfacial buffer, will follow. It will be shown that the nice interface properties of the SiN/Si system are preserved in the TiO/SiN/Si system, suggesting that the ultra-thin SiN layer is indeed a good interfacial buffer. Transistors made with TiO/SiN as the gate dielectric demonstrate excellent electrical quality. Reliability test results of the TiO/SiN stack indicate low trapping probability, high breakdown strength, and very little SILC. This and other pertinent results will be presented at the meeting.

11:30 AM R2.2 
MORPHOLOGY OF CVD SILICON NITRIDE ON OXIDE. M. Copel , P.R. Varekamp, D.W. Kisker, F.R. McFeely, IBM Research Div., Yorktown Hts., NY; K.E. Litz and M.M. Banaszak Holl, Univ. of Michigan, Ann Arbor, MI.

Future CMOS device development will require the availability of low capacitance gate dielectrics, such as nitride/oxide stacks. A critical step in the fabrication of ultra-thin N/O stack dielectrics is the nucleation of the silicon nitride layer. We have investigated the growth mode of CVD silicon nitride on thermal oxide using medium energy ion scattering (MEIS). Nitrides were grown in situ using trisilylamine (TSA) and NH3 or in a furnace using conventional DCS/NH3 chemistry. TSA is a novel inorganic precursor developed for silicon nitride CVD. The TSA growth conditions were between 720C and 740C for 2 to 20 minutes with a TSA partial pressure of  torr and an NH3 5:1 overpressure. Silicon nitride was observed to nucleate in islands which eventually coalesced to form a uniform layer for both in situ and furnace grown samples. In thicker films, oxygen was observed to permeate the film, due to either pinhole formation or inadvertent post-oxidation. Since the same growth mode was observed for widely differing reactor conditions and precursor chemistries, it is quite likely a fundamental characteristic of LPCVD growth of nitride on thermal oxide.

11:45 AM R2.3 
HIGH QUALITY ULTRA THIN Si3N4 GATE DIELECTRICS FABRICATED BY RAPID THERMAL CVD PROCESS. S.C. Song , H.F. Luan, D.L. Kwong, The University of Texas at Austin, Dept of Electrical Engineering, Austin, TX; M. Gardner, J. Fulford, M. Allen, Advanced Micro Devices, Austin, TX.

As MOS devices are scaled down, ultra thin alternate gate dielectric materials with lower leakage and enhanced boron diffusion barrier properties are needed. We report ultra thin (<20Å Si3N4 gate dielectric fabricated by rapid thermal CVD process, and the first sub-micron n- and p-MOSFETs made with such ultra thin (<20Å CVD Si3N4 gate dielectric, whose performance and reliability are compared to control SiO2 device of identical thickness (Teq). Conventional CMOS process was used, and entire gate dielectric films were formed by RTCVD process. The Si interface passivation layer (67Å is grown in NO. Si3N4 films were deposited using SiH4 and NH3, followed by post deposition annealing in NH3 and N2O. Control SiO2 films were also grown in the same RTCVD system. Thickness is calculated based on high frequency C-V measurement in strong accumulation without considering quantum-mechanical effect. Si3N4 devices exhibit higher ID and peak Gm compared to SiO2 devices for both n- and p-MOSFETs. Subthreshold swing values of both Si3N4 and SiO2 devices are excellent and comparable (66mV/dec for n-MOSFET and 74mV/dec for p-MOSFET). Under DAHC(Drain A valanche H ot C arrier injection) condition, less Gm degradation is observed for both n- and p-MOSFET with Si3N4 compared to SiO2 devices, attributed to extremely low electron trap density as well as stronger interface properties. Contrary to conduction in thick Si3N4 film known as P-F emission, ultra thin CVD Si3N4 film exhibits F-N tunneling based on linear fitting in F-N plot and the leakage current independence of temperature. Significantly lower gate leakage current is observed for ultra thin Si3N4 devices compared to SiO2. VFB difference between SiO2 and Si3N4 is as small as 50mV. Stress induced leakage current (SILC) after stress at a constant field is found much higher for SiO2 compared to Si3N4 device. TDDB is measured by stressing control SiO2 and Si3N4 capacitor with 5X10-5 cm2 area at a constant field. A 10X longer time-to-breakdown is observed in Si3N4 film at a given electric field. 

Chair: Takeo Hattori 
Monday Afternoon, April 5, 1999 
Nob Hill B/C/D (M)
1:30 PM R3.1 
SURFACE MORPHOLOGY OF ULTRATHIN OXIDE FORMED ON Si(100) SURFACE. Takeo Hattori , Masaaki Fujimura, Hiroshi Nohira, Musashi Inst. of Technology, Tokyo, JAPAN.

Studies on surface morphology, surface roughness and interface structure of extremely uniform ultrathin thermal oxide formed on Si(100) surface using non-contact mode atomic force microscopy and X-ray photoelectron spectroscopy [1] were continued up to the oxide film thickness of 2 nm. Hight distribution on the oxide surface over the area of 200 nm x 200 nm is approximated by the Gaussian function. Full width half maximum(FWHM) of this Gaussian function is equal to 0.135 nm, which is equal to single atomic step on Si(100) surface, below the oxide film thickness of 1 nm, which is equal to the thickness of structural transition layer, and then increases with increasing oxide film thickness. This implies that the surface roughness is limited to be equal to the interface roughness if the oxide surface is within 1 nm distant from the interface. Furthermore, the rms surface roughness exhibits oscillation with period in thickness of 0.17 nm up to the thickness of 2 nm. The amplitude of this oscillation does not change from 0.5 nm to 2 nm. According to the observation of surface morphology and the measurement of interface structure, this periodic change in surface roughness indicates the layer-by-layer oxidation reaction at the interface over the area of 5 nm x 5 nm. The period in oscillation below the oxide film thickness of 1 nm is slightly smaller than that above the oxide film thickness of 1 nm. This can be attributed to the difference between the strucuture of structural transiton layer and that of bulk silicon dioxide. 

1:45 PM *R3.2 
ATOMICALLY SMOOTH ULTRATHIN OXIDE LAYERS ON SILICON(113). Hans-Joachim Muessig , Jarek Dabrowski, Silvia Hinrich, Institute for Semiconductor Physics, Frankfurt (Oder), GERMANY.

The key mechanisms which govern the initial oxide growth on silicon surfaces have been analyzed on the basis of experimental (STM) and theoretical (ab initio) studies of certain atomistic features of oxygen interaction with Si(113). We report the first direct observation of dissociative chemisorption of oxygen molecules on a silicon surface and we link this to the fact that very smooth oxide layers can be grown on Si(113). The process of initial oxidation is discussed in terms of surface diffusion paths and surface stress. Because of the interplay between surface stress, dangling bond density, and chemical bond energies, the oxide formation on Si(113) is simpler in comparison with Si(001). Si(113) surfaces are interesting because of their thermal stability, low surface energy, high flatness, and natural anisotropy. Since Si(113) offers multiple possibilities for bonding and is structurally related to biatomic Si(001) or Si(111) steps, it is also a valuable system for studies of physical mechanisms which control reconstruction and growth of surfaces. Our first calculations indicate how the oxygen atoms affect the local density of states, and where the favored adsorption sites are located. Experimental evidence was found for bond geometries which support epitaxial growth of an ultrathin oxide layer on the substrate at increased temperatures. Neither defects nor the ejection of Si atoms play a significant role during initial stages of oxidation. This helps us understand how the Si ejection and forming of island nuclei on Si(001) is related to oxygen chemisorption. We conclude that the atomic smoothness of the oxide on the Si(113) surface is promoted by the tensile strain, i.e., an oxide grown on Si(001) prepared to have an increased tensile strain should be smoother than the oxide grown on Si(001) in a standard way.

2:15 PM R3.3 
LONG RANGE ORDER IN ULTRA-THIN SiO2 GROWN ON Si(100). Q.B. Hurst, N. Herbots , J. Shaw, M. Floyd, D.J. Smith, R.J. Culbertson, M. Grams, J.D. Bradley, Arizona State University, Dept. of Physics and Astronomy, Tempe, AZ; V. Atluri, Intel Corp., Chandler, AZ; B. Doyle, B. Roberds, G. Bai, Intel Corp., Santa Clara, CA.

We analyze the correlation of electrical properties and oxidation rates in 1-4 nm thick SiO2 grown on H-passivated Si(100) for ultra-thin gate applications. Ordered (1x1) Si(100) stable in ambient air is obtained at room temperature by wet chemical cleaning. C-V and I-V measurements are generally inconclusive for ultra-thin (1-2 nm) oxides because of leakage and breakdown. Surface channel analysis enables a comparison between ordered oxides and conventional oxides. Some ordered oxides produced in this work exhibit a lower oxide charge density and a minority carrier lifetime twice that measured for conventionally prepared thermal oxides. Ion Beam Analysis using a combination of ion channeling and 16O(,)16O nuclear resonance show that Oxygen areal density increases with increasing ion beam dose indicating damage to ordered oxide structure by incident ion beam. A comparison by HRTEM shows that the more ordered SiO2 films exhibit flatter, more periodic interfaces with Si(100) than the less ordered films which exhibit more stepped interfaces. Experimental data is compared to calculations done by Monte-Carlo simulation.

2:30 PM *R3.4 
LAYER-BY-LAYER OXIDATION OF SILICON SURFACES. Heiji Watanabe , Fundamental Research Laboratories, NEC Corporation, Ibaraki, JAPAN; Noriyuki Miyata and Masakazu Ichikawa, Joint Research Center for Atom Technology, Ibaraki, JAPAN.

Layer-by-layer oxidation of Si surfaces has been studied by using scanning reflection electron microscopy (SREM) combined with Auger electron and x-ray photoelectron spectroscopy (AES and XPS). We have demonstrated that SREM reveals the step and terrace configurations at SiO2/Si interfaces without the need to remove the SiO2 layer. Our SREM results show that the initial step structure on a Si substrate is preserved at the SiO2/Si interface, and that the buried steps do not move laterally during oxidation.