Meetings & Events

Spring 1999 logo1999 MRS Spring Meeting & Exhibit

April 5-9, 1999 | San Francisco
Meeting Chairs: Katayun Barmak, James S. Speck, Raymond T. Tung, Paul D. Calvert

Symposium T—Advanced Semiconductor Wafer Engineering


Robert Davis 
Dept of MS&E 
North Carolina State Univ 
Riddick Hall Rm# 229 
Raleigh, NC 27695-7907 

Ulrich Goesele
Max Planck Inst
for Mikrostrukturphysik
Halle, D-06120 GERMANY
49-345-5582 x657

Katsu Izumi 
NTT System Electronics Labs 
Atsugi, 243-0198 JAPAN 

Wilfried von Ammon
Wacker Siltronic AG
Burghausen, D-84479 GERMANY

* Invited paper

Chairs: Ulrich M. Goesele and Teh Y. Tan 
Monday Morning, April 5, 1999 
Golden Gate C3 (M)
8:30 AM *T1.1 
DEVELOPMENT OF SUPER-LARGE DIAMETER EPITAXIAL SILICON WAFER. Masato Imai , Masanori Mayusumi, Kazutoshi Inoue, Shinji Nakahara, Super Silicon Crystal Research Institute Corp., Epitaxial Technology Dept., Gumma, JAPAN. 

As device integrity is increasing, device yield drops drastically by micro-defects in wafer. However, improving quality for super large-diameter wafers is extremely difficult. Therefore, the epitaxial wafer is expected as main substrate for advanced device. 
However, as the expectation is increasing, requirement is also increasing. The quality improvements, especially, slip free, contamination free and high uniformity is required. The requirement for the production cost reduction become very stringent. 
In order to correspond to the severe requirements, we proposed the following approaches for 400mm epitaxial wafer development. (1) Development of low temperature process Lowering of process temperature is an effective means to decrease contamination, prevent slip generation, and lower cost. We are developing a process with maximum temperature bellow 1000C. (2) Development of Cl gas compound free process Cl gas compounds such as HCl and SiHCl3 are the primary cause of metal contamination in epitaxial wafers and impede toxin removal from waste gases. Therefore, SiH4 and H2 based processes, which don't use Cl gas compound, have been developed. (3) High accuracy process control Temperature distribution and gas flow in epitaxial growth process are closely connected with wafer quality as uniformity and slip generation. We study the phenomena during epitaxial growth process by computer simulation and experiments. (4) Optimal substrate matches epitaxial process To reduce epitaxial wafer cost, looking past the epitaxial process and considering all silicon wafer-manufacturing processes is desirable. Factors will be defined by those that have an influence on quality and those that don't; allowing selection of appropriate epitaxial wafers according to process conditions and achieving cost reductions. 'll summarize the technical issues about super-large diameter epitaxial silicon wafer, and introduce our activities. 

9:00 AM T1.2 
MISFIT DISLOCATION FORMATION IN P/P+ SILICON VAPOR PHASE EPITAXY. Petra Feichtinger , Hiroaki Fukuto and M.S. Goorsky, Dept of Materials Science and Engineering, University of California, Los Angeles, CA; D. Oster, J. Moreland and M. Rao, Wacker Siltronic Corp, Portland, OR. 

Edge polishing and other edge treatments are becoming important for large diameter silicon wafers. We examined the influence of wafer edge treatments on the evolution of misfit dislocations in p/p+ silicon wafers. Elimination of misfit dislocations is very important for the successful fabrication of high quality electronic devices. We investigated the origin and glide activation energies of misfit dislocations in p/p+ silicon wafers. The samples were 150 mm Czochralski grown wafers. Different edge treatments were used during the processing of the wafers to create a variation of edge shape and roughness. Nominally boron doped epitaxial layers beyond the critical thickness were deposited by vapor phase epitaxy at 1050 - 1100C in a single wafer reactor. The misfit dislocation propagation velocity as a function of stress in the epitaxial layers was measured using post-growth thermal treatments of wafers with different levels of stress. The influence of the wafer shape and roughness on the observed misfit dislocation segments was studied. Double crystal x-ray topography was used to visualize the length of the misfit dislocation segments around the wafer periphery. Various misfit segment lengths were observed within one sample. This distribution of misfit dislocation length suggests more than one misfit dislocation nucleation event. In regions where the misfit dislocations were located, triple axis x-ray diffraction measurements were performed to determine the amount of layer relaxation. Misfit segments around the wafer periphery were observed at the interface after removal of the epitaxial layer by Secco etching. Densities were counted using standard optical microscope with a Nomarski setup. All results suggest that a potential misfit nucleation source is crystalline roughness at the wafer periphery. 

9:15 AM T1.3 
IS SEGREGATION GETTERING WORKING FOR Cu AND Ni IN P/P+ EPITAXIAL WAFERS? Robert Hoelzl , Klaus-Juergen Range, University of Regensburg, Dept of Inorganic Chemistry, Regensburg, GERMANY; Lazlo Fabry, Juergen Hage, Reinhold Wahlich, Wacker Siltronic AG, Burghausen, GERMANY. 

p/p+ epi wafers are the ideal solution for futures IC applications due to their unmatched device parameter performances. While Ni has well been known to be a dangerous contamination, examinations are focusing more and more on Cu gettering to be able to control contaminations during novel Cu interconnect techniques. In order to evaluate gettering mechanisms, wafers were contaminated by the spin-on technique in the 1012 atoms/cm2 range and metal drive in was done under inert gas atmosphere. A new chemical etching technique was developed which allowed to homogenously etching off thinn layers of a Si-wafer. Afterwards the etching solution were analysed by ICP-MS. p/p+ epi-wafers with different substrate resistivities were examined. The results were: Ni was not gettered by the high boron concentration nor by stress formations at the epi/substrate interface. Instead, Ni precipitated completely at the wafer surfaces. Cu was gettered by the high boron concentration of the p+ substrate. Polysilicon backside was an effective gettering site for both, Ni and Cu. The gettering strength difference between the boron gettering and gettering by oxygen precipitates was evaluated by using p+/p wafers. The substrates had a high resistivity and were precipitated. p+ was still a good gettering site for Cu. We interprate the gettering results in a solid-state chemical treatment of the gettering process. 

9:30 AM T1.4 

X-ray imaging techniques such as diffraction topography and phase contrast imaging, greatly benefit from the exellent beam characteristics of dedicated third generation synchrotron radiation sources. High intensity, small angular source size and high energy photons, in combination with modern high resolution detectors are advantageous for the characterisation of semiconductor wafers, allowing short exposure times and high spatial resolution. In the paper results from a number of collaborations with several partners will be presented, for example: - topographical imaging of entire 300 mm Si wafers with an electronic registration (CCD camera) and with 10 m resolution, - parallel topographical imaging and local rocking curve measurements (position and width) of entire wafers; topographical resolution 10 m, spatial average for the local rocking curve parameters, possible to select between 10 m2 and 1 mm2, - phase contrast imaging of micro and macrodefects in SiC wafers, - topographical characterisation of SOI wafers (SIMOX wafers, Si-on-Si and SiC-on-Si bonding wafers); qualitative and quantitative, global and local determination of strain, detection and characterisation of threading dislocations in the thin layers, detection of larger voids, Ö - use of X-ray imaging results to improve crystal growth techniques. 

9:45 AM T1.5 
WAFER QUALITY IMAGING BY  RESOLVED HIGH RESOLUTION X-RAY DIFFRACTION. Daniel Lubbert , Tilo Baumbach, Fraunhofer-Institute for Non-Destructive Testing, Saarbrucken and Dresden, GERMANY; present address: ESRF, Grenoble, FRANCE; Elodie Boller, Jurgen Hartwig, José Baruchel, ESRF, Grenoble, FRANCE. 

Wafer quality inspection and defect analysis are crucial for improvements of the wafer fabrication technology as well as the correlation of device properties with the wafer treating processes. We present an equipment for wafer defect analysis and industrial wafer inspection at the European Synchrotron ESRF (Grenoble, France). The wafer quality evaluation concerns simultaneously the macroscopic warpage, the mesoscopic curvature and the microscopic defect structure and its distribution. The method is based on X-ray diffraction rocking curve imaging of the whole wafer with up to 2  resolution. The non-destructive wafer testing is performed at the ID19 beamline of the ESRF, where we use a well collimated X-ray beam of sufficiently high energy and with a large spot at the sample surface in a low dispersive diffraction arrangement. The new wafer testing equipment determines the maximal and integral Peak intensities, the peak position and the half width of the rocking curves with a microscopic resolution, imaging simultaneously the macroscopic quality parameters and the microscopic defect structure. This permits the direct one-to-one correlation between the microscopic defects and the resulting macroscopic effects. Wafers of different materials, fabrication technology and resulting perfection are studied. Examples will be given for GaAs, InP and SiC. 

10:30 AM *T1.6 

Using new techniques which manage intrinsic point defect concentrations during the growth of silicon crystals and subsequent processing of silicon wafers, it is possible to achieve two highly desirable results. First, using techniques which maintain a quasi-equilibrium state during growth, it is possible to grow large diameter CZ silicon crystals which are completely free of agglomerates of vacancies (voids) or self interstitials (dislocation loops). The control of both defect types is critical to the successful manufacture of high density Integrated Circuits. Material free of such microdefects is called ``Perfect Silicon''. Secondly, through the control of quenched-in vacancy concentration profiles in thin silicon wafers during Rapid Thermal Annealing processes, it is possible to obtain ideal oxygen precipitation behavior in silicon wafers. Such vacancy concentration engineered wafers are effectively programmed to produce robust defect distributions suitable for Internal Gettering (IG) applications. The performance of such wafers is independent of all parameters previously important to engineering of IG structures: oxygen concentration, crystal growth method and even the application in which the wafer is used. Such material is said to have a ``Magic Denuded Zone''. These two new types of material represent important simplifications to the successful defect engineering of silicon wafers in advanced IC applications. 

11:00 AM T1.7 

Recently, much research has been devoted to the reduction in the number of agglomerated point defects in Czochrolski (CZ) silicon crystals. Various strategies are being used to improve device yeilds and reduce production costs by managing point defect distributions. We present the results of numerical simulations that treat the time evolution of the concentrations of interstitial and vacancy point defects in a two dimensional axi-symmetric CZ silicon crystal. Diffusion and solid convection are treated within the crystal and equilibrium boundary conditions are maintained on the crystal periphery and at the solid-melt interface. The temperature distribution inside of the crystal can be determined separately by heat transfer simulations and/or measurements. The simulations are used to identify and demonstrate methods for reducing the supersaturation of point defects at all temperatures by managing the thermal history and the radial variation of the ratio V/G, where V is the crystal growth rate, and G is the local axial temperature gradient in the solid evaluated at the solid-melt interface. Comparisons will be made with measurements of agglomerated defect distributions in 200mm experimentally grown CZ crystals. Comments on the various models for point defect incorporation will be made in light of the simulation results. 

11:15 AM T1.8 
ON THE STATE OF VACANCIES IN AS-GROWN FLOAT-ZONE SILICON. Peter Pichler 1, Fabian Quast1, Heiner Ryssel2,1, Vladimir V. Voronkov3,4, Robert Falster51Fraunhofer-Institut für Integrierte Schaltungen, Bauelementetechnologie, Erlangen, GERMANY; 2Lehrstuhl für Elektronische Bauelemente, Universität Erlangen-Nürnberg, Erlangen, GERMANY; 3MEMC Electronic Materials SpA, Merano, ITALY; 4Permanent Address: Institute of Rare Metals GIREDMET, Moscow, RUSSIA; 5MEMC Electronic Materials SpA, Novara, ITALY. 

Platinum diffusion at temperatures of 730C has been developed to an important tool to study the spatial distribution of vacancies in silicon. Measuring platinum profiles in as-grown float-zone wafers, differences were noted to simulations based on the usual Frank-Turnbull and kickout mechanisms and were, at first, attributed to experimental uncertainties. Profiles measured after diffusion times of 10 min were found to penetrate deeper with markedly smaller surface concentrations than predicted by simulations. But also profiles measured after longer diffusion times were found to disagree slightly, but noticeably, with simulated profiles. Measurements since then indicated that the effects noticed cannot be attributed to merely experimental problems. For the temperature and process time of the experiments, neither diffusion of the intrinsic point defects nor the kick-out effect can be important. A detailed investigation of measured profiles indicates that at least two reactions of platinum interstitials with vacancy-like defects have to be taken into considerations for the incorporation of platinum atoms at substitutional sites. Both work with significantly different time-constants and with different vacancy-like defects. In the presentation, various models based on the interaction of intrinsic point defects and their clusters with interstitial platinum atoms will be discussed. The most simple model able to reproduce the shape of the experimental profiles is based on a rapid interaction of interstitial platinum atoms with divacancies to substitutional platinum and monovacancies. A slower mechanism is associated tentatively with the Frank-Turnbull reaction of interstitial platinum atoms and the liberated monovacancies. It is shown that the model results in a significantly better agreement between experiments and simulations than a model based on the Frank-Turnbull mechanism alone. 

11:30 AM T1.9 
GENERATION OF DISLOCATIONS AT OXYGEN PRECIPITATES IN SILICON. Kerstin Jurkschat , Semih Senkader, Andrew J. Peakman, Peter R. Wilshaw, Department of Materials, University of Oxford, UNITED KINGDOM; Robert Falster, MEMC Novara, ITALY. 

Oxygen, oxygen related defects, and dislocations are determining factors for the mechanical stability of Si-wafers and for the device yield. We studied the behaviour of dislocations at oxygen precipitates in Czochralski Silicon wafers for different precipitation sizes, densities and background oxygen concentrations using a bending technique with annular knife-edges causing a biaxial stress distribution. The stress level at which dislocation movement can be detected around precipitates and the generation rate of new dislocations have been found to depend on the mean precipitate diameter, the precipitate density, and the background oxygen concentration prior to precipitate growth. It is thought that precipitates which have dislocation loops attached to them can act as Frank-Read-Sources. In this case the stress threshold at which dislocations begin to move can be increased by a thermal treatment prior to deformation that allows oxygen to diffuse to the dislocation loops causing a locking effect. Compared to wafers with big precipitates (more than 50 nm in diameter) a much smaller proportion of precipitates seems to be activated as dislocation sources in wafers with small precipitates (less than 20 nm in diameter) thus suggesting a different precipitate type predominating in these wafers and/or a qualitative difference in the shape of the size distribution function for both wafer types. By using this technique it may be possible to define conditions for the thermal treatment of silicon wafers during manufacture where the internal gettering properties of oxygen precipitates can be exploited without weakening the silicon wafers. 

11:45 AM T1.10 
OXYGEN PRECIPITATION IN SILICON. K.F. Kelton , P.F. Wei, Department of Physics, Washington University, St. Louis, MO; R. Falster, D. Gambaro, M. Olma, M. Cornara, MEMC Electronic Materials SpA, Viale Gherzi, Novara, ITALY. 

Quantitative experimental measurements of the oxygen precipitate rate as a function of annealing in Czochralski-grown silicon wafers that contained different initial concentrations of oxygen are presented. These experimental data are compared with numerical predictions for time dependent nucleation. Good agreement is found with predictions from the classical theory of nucleation if the nucleation temperature is greater than 600C, though only over a narrow range of oxygen composition. Below 600C, however, the measured density for all samples is several orders of magnitude larger than is predicted from that model. Also, the measured data show an anomalously small temperature dependence for the induction time for nucleation that does not scale with the diffusion coefficient, as expected from the classical theory of nucleation. Preliminary results from a new model for nucleation that is based on a link between the interfacial and long-range diffusion fluxes are presented. These predictions are in much better agreement with the experimental data.
Chairs: Robert Falster and Peter Pichler 
Monday Afternoon, April 5, 1999 
Golden Gate C3 (M)
1:30 PM *T2.1 
SCIENCE-BASED GETTERING STRATEGIES IN SEMICONDUCTOR WAFERS. T.Y. Tan , Department of Mechanical Engineering and Materials Science, Duke University, Durham, NC. 

In the past, intrinsic gettering utilizing oxygen precipitation has been extensively studied for IC fabrications using CZ Si, with the main efforts concentrated on the engineering and scientific aspects of the creation of gettering sites. The present review will focus on recent progresses on a variety of processes and mechanisms of the gettering of the yield-detracting metallic impurities from the device active regions to the created gettering regions. Based on these knowledge, new challenges and strategies associated with fabrications of IC and other kinds of devices will be discussed. 

2:00 PM T2.2 
CAVITIES AND DISLOCATIONS INDUCED IN SILICON BY MEV HE IMPLANTATIONS. S. Godey , T. Sauvage, E. Ntsoenzok, CERI-CNRS, Orleans, FRANCE; H. Erramli, Univ CADI AYYAD, Marrakech, Maroc, M.F. Beaufort, H. Garem, J.F. Barbot, C. Blanchard Laboratoire de Metallurgie Physique, CNRS, Futuroscope, FRANCE. 

Cavities induced by high doses helium implantation and subsequent annealing are known to be efficient external gettering sites in silicon. In this paper damage formed after 1.6MeV implantation of He (Rp=5.5) and annealing at 800C for 30 min has been examined using cross sectional transmission electron -(microscopy. Two sets of experiments were done. In the first set samples were implanted at doses ranging from 1E+16 to 1E+17 He/ cm2 while keeping a constant dose rate whereas in the second the effects of the dose rates were studied. Results show that the density of cavities is dependent of the implanted dose. The so-created damage microstructure is shown to be also strongly flux dependent. With increasing dose rates, we observe an increase of the density of dislocations emerging from aggregates of large cavities. In some cases theses dislocations can even propagate until the sample surface. RBS experiments using 2.5MeV proton have also been performed to determine the fraction of helium remaining in cavities. In addition, in order to compare the effect of MeV implants with keV implants, a wafer was implanted with 50keV He ions at 5E+16 He/ cm2

2:15 PM T2.3 
PRECIPITATION KINETICS OF COPPER IN N- AND P-TYPE SILICON. Christoph Flink , Andrei A. Istratov, Univ of California-Berkeley, Dept of MS&ME, Berkeley, CA; Scott A. McHugo, Advanced Light Source Center, Lawrence Berkeley National Laboratory, Berkely, CA; Henning Feick, Henry Hieslmair, Winfried Seifert, Univ of California-Berkeley, Dept of MS&ME, Berkeley, CA; Thomas Heiser, Univ Louis Pasteur, Dept of Physics, Strasbourg, FRANCE; Stefan Sprater, Christian Kisielowski, National Center of Electron Microscopy, Lawrence Berkeley National Laboratory, Berkely, CA; Eicke R. Weber, Univ of California-Berkeley, Dept of MS&ME, Berkeley, CA. 

Copper, which is a major contaminant in silicon devices, is considered the number one candidate for metallic interconnections in ULSI technology. Feasible gettering techniques for copper in silicon have to be developed to guarantee device performance. Hence, detailed understanding of the precipitation kinetics of copper in silicon is imperative. 
We have studied copper in FZ-silicon after temperature diffusion at 600C - 1150C and quench. Transient Ion Drift (TID), X-Ray Fluorescence (XRF), and Transmission Electron Microscopy (TEM) are used to show the difference in the precipitation kinetics of copper in n-Si and p-Si. In n-Si, the concentration of precipitated copper as measured by XRF and TEM was close to the copper solubility at the diffusion temperature. No interstitial copper was detected after quench. In the contrary, in p-Si no copper precipitates were detected with XRF and TEM, if the solubility at the diffusion temperature was chosen below the doping concentration. At higher diffusion temperatures, more than an order of magnitude less precipitated copper was measured than indiffused during the heat treatment. The interstitial copper concentration after quench, as measured with TID, decreases over time as a function of the wafer thickness and depends on the amount of copper precipitated. Analysis of the experimental data suggests that the copper kinetics is dominated by bulk precipitation in n-Si and by out-diffusion in p-Si. If the copper concentration exceeds the acceptor concentration, type inversion may occur and precipitation takes place. 
Computer simulations of the process of out-diffusion and bulk precipitation of copper are presented. The simulations take into account the effective diffusivity of copper in p-type silicon and the electric field due to the interstitial copper concentration profile and are in a very good agreement with TID measurements. 
The implications of this model for gettering application are discussed. 

2:30 PM T2.4 
IDENTIFICATION OF THE CHEMICAL STATE OF METAL IMPURITIES IN SILICON. Scott A. McHugo , A.C. Thompson, G. Lamble, Lawrence Berkeley National Laboratory, Berkeley, CA; E.R. Weber, University of California at Berkeley, CA; W. Seifert, Technical University Freiberg, Freiberg, GERMANY; M. Werner, Max-Planck Institute-Halle, GERMANY. 

In order to maintain high performance and high yield of silicon-based integrated circuits and solar cells, metal impurities must be effectively gettered from the active device region. The ability to getter impurities and the stability of impurities at gettering sites is critically dependent on the chemical state of the metal impurities. Specifically, the chemical state determines the binding energy of the impurities to its precipitation site and, therefore, the rate of impurity release from the precipitation site. In this work, we examine the chemical state of metal impurities in single crystal and polycrystalline silicon using synchrotron-based x-ray fluorescence and x-ray absorption spectroscopy with 1m2 scale resolution and parts-per-million sensitivity. Nm-scale precipitates of Fe, Cu, Ni and Cr were detected at specific structural defects and the chemical state of the impurities was identified. Despite the high probability of metal silicide formation, we have identified metal oxides in the silicon material. Considering the high thermodynamic stability of metal oxides compared to metal silicides, our results suggest metal impurities in silicon can be found in highly stable states. 

2:45 PM T2.5 
HYDROGEN GETTERING AND LOSS AT POST-IMPLANTATION HYDROGEN PLASMA TREATMENTS AND ANNEALING OF HYDROGEN AND HELIUM IMPLANTED CZOCHRALSKI SILICON. Alexander Ulyashin, Anatolii Ivanov, Belarussian Polytechnical Acad, Minsk, BELARUS; Reinhart Job , Wolfgang Fahrner, Univ of Hagen, GERMANY; Faddei Komarov, Alexander Kamyshan, Belarussian State Univ, Minsk, BELARUS. 

The effect of the gettering of hydrogen by buried layers at post-implantation hydrogen plasma treatment and the loss of hydrogen by these layers at high-temperature annealing of hydrogen and helium implanted Czochralski (Cz) grown silicon has been investigated. Hydrogen ions were implanted in p-type Cz silicon with an energy of 70 keV and doses of 1  1016 cm-2 and 3  1016 cm-2. He implantation was done at 300 keV energy with a dose of 1  1016 cm-2. The samples were hydrogenated in a DC hydrogen plasma and annealed at different temperatures up to 1000C in flowing nitrogen and for comparison in a hydrogen ambient. Secondary ion mass spectroscopy was applied to measure the hydrogen concentration profiles in the samples. From the experimental results one can conclude that the buried defect layers created both by hydrogen or helium implantation operate as good getter centers for hydrogen at appropriate heat treatments. It can also be concluded that the hydrogen atoms are captured by buried layers and can be detected with the considerable concentrations after post-implantation annealing in hydrogen ambient of helium and hydrogen implanted samples even after high temperature annealings. It is shown that the loss of hydrogen by buried layers depends on the temperature, the time of annealing and the annealing ambient. 

3:30 PM *T2.6 
Si-WEDS: A CONSORTIUM APPROACH TO WAFER ENGINEERING OF DEFECTS IN SILICON. Eicke R. Weber , Christoph Flink, Henry Hieslmaier and Andrei Istratov Dept. of Materials Science, Univ. of California, Berkeley, CA. 

The investigation of imperfections in Si wafers that are detrimental for device performance has accompanied device development in the last 40 years. Although in most cases the understanding of a specific class of defects trails the technological solution, further progress and quick solutions would be impossible without the basic materials understanding provided by the research community.