Margit Zacharias Max-Planck-Institute of Microstructure Physics
Walter Riess IBM Research GmbH
Peidong Yang University of California-Berkeley
Younan Xia University of Washington
P1: Methods for Templating and Nanostructuring
Tuesday PM, April 18, 2006
Room 2024 (Moscone West)
11:30 AM - **P1.1
Template Approaches to Nanowire Growth.
Ulrich Goesele 1 , Danilo Zschech 1 , Martin Steinhart 1 , Woo Lee 1 , Kornelius Nielsch 1 , Silke Christiansen 1 , Peter Werner 1 Show Abstract
1 Experimental Dept. II, Max Planck Institute of Microstructure Physics, Halle Germany
For many technical applications it is desirable to grow nanowires ofdefined diameter and length at predefined positions. The talk willdescribe a number of approaches using templates either as mask fordefining the location of catalytic particles or as growth reactorwithin which the nanowires are grown. Special emphasis will be put ontemplates based on ordered pore arrays of alumina ordiblock-copolymers as well as those based on dislocation arraysfabricated by twist wafer bonding. The state of the art of theseapproaches will be discussed and potential future approaches will beoutlined.
12:00 PM - P1.2
Large Area Si Nanowire Arrays Fabricated Using Nano-Imprint Lithography.
Luke Hunter 1 , A. Talin 1 , Bhavin Rokad 2 , Francois Leonard 1 , Blake Simmons 1 , Paul Dentinger 1 Show Abstract
1 Nanoscale Science & Technology, Sandia National Labs, Livermore, California, United States, 2 , Cornell University, Ithica, New York, United States
12:15 PM - P1.3
Defined Preparation and Optical as well as Structural Characterization of ZnO Nanorods.
Thomas Buesgen 1 , Michael Hilgendorff 1 , Witold Kandulski 1 , Peter Karageorgiev 1 , Michael Giersig 1 Show Abstract
1 nanoparticle technology, caesar research center, Bonn Germany
We present structural and optical properties of ZnO nanorods grown by chemical vapor deposition (CVD) and wet-chemical syntheses. The CVD-growth is catalyzed by gold islands, pre-patterned on sapphire substrates by use of the nanosphere lithography (NSL) technique, resulting in laterally ordered, upright ZnO nanowires of diameters less than 100 nm and a length of up to several micrometers. By modifying the NSL mask using annealing or chemical treatment, the holes between adjacent nanospheres can be reduced, which results in smaller, well-separated catalytic islands on the substrate. Tilting and turning the sample holder during catalyst evaporation produces many different structures.Rods grown by the wet chemical approach from zinc organics or zinc salts as precursors are much thinner with diameters less than 10 nm and aspect ratios up to 10. We show, that the use of long-chain amines induces the one-dimensional growth. Currently, we are carrying out doping experiments on both CVD and wet-chemical synthetic routes, to influence the conductivity, magnetism or luminescence of ZnO. We are going to present first results on these doped ZnO nanorods, which probably have applications as light emitting devices, sensors, bio-labels or piezoelectric devices, etc. in the near future.All produced rods are characterized structurally by electron microscopy (SEM, TEM, HRTEM) and optically by absorbance and photo-luminescence spectroscopy. Furthermore, we show results obtained by scanning near-field optical microscopy of the ZnO nanowires.
12:30 PM - P1.4
Synthesis and Characterization of Silicon Nanorod Arrays for Solar Cell Applications
Brendan Kayes 1 , Joshua Spurgeon 1 , Nathan Lewis 1 , Harry Atwater 1 Show Abstract
1 , California Institute of Technology, Pasadena, California, United States
As a photovoltaic material, nanorods have the potential to enhance carrier collection and hence increase efficiency, in the case that the minority carrier diffusion length in the material is much less than the material’s “optical thickness”, i.e., thickness of material required to absorb 90% of the energy from solar photons above the band gap of the material. This can be achieved by creating an array of nanorods aligned normal to a substrate, either embedded inside another material, or with each nanorod having a radial pn junction (see Kayes, Lewis, and Atwater, in Jour. Appl. Phys. 97 (11): Art. No. 114302 JUN 1 2005). Silicon nanorods for photovoltaic applications have been grown by chemical vapor deposition (silane diluted to 5% concentration in argon), using either gold or indium as a catalyst for the vapor liquid solid (VLS) process. Rod morphology improves with increasing substrate temperature and decreasing silane partial pressure in the range T=300-600 C and for silane partial pressure = 50-1000 mTorr. Best results were achieved with substrate temperatures of 600 C and silane partial pressure of 50 mTorr. Flow rate was varied between 40 and 200 sccm. Growth was achieved on both silicon and germanium substrates. In most cases, catalyst particles were formed by partial de-wetting of vapor deposited films of the catalytic material from the substrate to form droplets with diameters of tens to hundreds of nanometers. Periodic arrays of catalyst particles with controlled size and spacing were achieved by both the use of porous alumina membranes and by e-beam lithography. Using these techniques, silicon nanorods were grown with diameters of 100nm to microns and lengths of microns to tens of microns. Using a gold catalyst with or without templating, and using an indium catalyst with a template, the goal of fabricating dense arrays of silicon nanorods aligned normal to the substrate was achieved.Nanorod morphology was investigated primarily by scanning electron microscope (SEM). It was found that indium acts as a VLS catalyst and can seed growth of nanorods that are straight for up to tens of microns. However, without templating, the growth of nanorods did not occur across the entire substrate, apparently due to both the high mobility of indium on the substrate surface and also the high indium vapor pressure at the deposition temperature. These problems were alleviated by the templating methods described above. Gold does not suffer from either of these qualities, making it apparently a more suitable catalyst. However, it appears that the incorporation of gold into the nanorod as it grows quenches luminescence (private communication with Prof. Mark Brongersma of Stanford University). Gold is well-known to form a deep-level impurity in silicon. We will present photoluminescence (PL) intensity measurements illustrating the effect that changing catalyst has on the optical properties of the nanorods.
P2: Nanowire Growth
Tuesday PM, April 18, 2006
Room 2024 (Moscone West)
2:30 PM - **P2.1
Silicon Nanowire Growth Kinetics from In situ Transmission Electron Microscopy.
Frances Ross 1 , Suneel Kodambaka 1 , James Hannon 1 , Ruud Tromp 1 , Mark Reuter 1 , Jerry Tersoff 1 Show Abstract
1 TJ Watson Research Center, IBM Research Division, Yorktown Heights, New York, United States
Nanowires grown by the vapour-liquid-solid process have exciting possible uses as elements of vertical transistors, sensors or microelectromechanical devices. Most applications of nanowires require the diameter to be uniform, the surface structure to be well defined, and the growth to initiate at specific positions on a substrate. A detailed understanding of the effects of different growth conditions on the growth kinetics and surface structure would be helpful in achieving the necessary control. We have therefore measured in real time the growth kinetics of individual Si and Ge nanowires formed using Au as the catalyst, observing nucleation and measuring growth direction, growth rate and surface structure as a function of temperature, gas ambient and wire diameter. This data was obtained by recording wire growth at video rate in an ultra high vacuum electron microscope which has deposition capabilities enabling wires to be grown in situ. We show that the kinetics of Si wire growth display interesting features which are not included in the basic vapour-liquid-solid growth mechanism. In particular, surface diffusion of the Au catalyst leads to droplet coarsening, changing the diameter of wires during growth, while surface oxidation slows this diffusion process and can also change the wire growth direction. We will compare these results for Si with kinetic and structural data obtained during Ge wire growth, and will also discuss in situ observations of the growth of heterostructures. Finally we will consider the implications of such real-time results on forming wirelike structures of controlled orientation and uniformity in Si and in other systems.
3:00 PM - P2.2
A New Understanding of Metal-assisted Growth of 1D Nanowire.
Zhenyu Ryu 1 , Judith Yang 1 , Kyeongjae Cho 2 Show Abstract
1 Department of Materials Science and Engineering, University of Pittsburgh, Pittsburgh, Pennsylvania, United States, 2 Department of Mechanical Engineering, Stanford University, Stanford, California, United States
One-dimensional (1D) nanostructures have attracted a considerable attention, due to their potential application as building blocks for electronic and photonic nanodevices. A remarkably elegant method of producing nanowires is through a metallic nanoparticle which catalyzes a solid nanowire from a vapor phase precursor molecules. However, detailed mechanistic understanding of the catalytic growth process is still lacking. Such understanding is needed for further control and development of nanowires. The interface between metal nanoparticle and nanowire is the growth front of the nanowire, and its detailed structure plays a crucial role in the nanowire formation. A detailed experimental analysis for metal nanoparticle-nanowire interface is being carried out by ex-situ and in-situ electron microscopy, including Z-contrast imaging, energy dispersive X-ray emission (EDX) and electron energy-loss spectroscopy (EELS) techniques, electron diffraction and high-resolution electron microscopy (HREM). The experimental data will be systematically compared with a multi-length scale modeling of nanowire growth from metal nanoparticles. The observed results showed that active sites or catalyst facets on the metal-nanoparticles are essential to nucleate the nanowires. Single active site would lead to one nanowire growth and two active sites would lead to formation of twin nanowires or biaxial nanowires, even branched heterostructured nanowires. These understandings on reaction mechanisms may be helpful for the controlling synthesis of 1D nanowire structures and further application development.
3:15 PM - P2.3
What Makes the Generation of Silicon Nanowires by Molecular Beam Epitaxy so Special
Peter Werner 1 , Nikolai Zakharov 1 , Gerhard Gerth 1 , Luise Schubert 1 , Ulrich Goesele 1 Show Abstract
1 , MPI of Microstructure Physics, Halle (Saale) Germany
Silicon nanowires (Si NW) can be successfully grown by applying the vapor-liquid-solid process (VLS). Small metal particles, e.g. of gold, deposited on a substrate are used as a seed for the subsequent NW growth. In the case of the mainly used chemical vapor deposition technique (CVD) a Si containing gas/precursor is cracked at the Au droplets and single Si atoms are subsequently solved in the liquid metal. Due to a supersaturation within this droplet, Si precipitates predominantly at the liquid-solid interface – a nanowire growth. At the substrate surface no Si deposition is observed. In the case of the low-pressure CVD technique, the surface is even covered by carbon or oxide layers, which favors the growth only at the metal tip of the NW. A partly completely different situation occurs, if NW are grown by molecular beam epitaxy (MBE) via the VLS mechanism. We will describe the differences between CVD and MBE generated NW. This concerns the role of the metal seed, the morphology of the NW and the aspect ratio of length and width. Especially surface diffusion including the metal used as well as Si strongly influences the growth process. Surface contamination (oxygen, carbon) have a significant influence on the MBE growth and on a further technological application.
3:30 PM - P2.4
Silicon Nanowire Epitaxial Growth Dependence on Substrate Orientation.
Pavan Aella 1 3 , W. Petuskey 1 3 , S. Picraux 2 3 4 Show Abstract
1 Department of Chemistry and Biochemistry, Arizona State University, Tempe, Arizona, United States, 3 Science and Engineering Materials Graduate program, Arizona State University, Tempe, Arizona, United States, 2 Department of Chemical and Materials Engineering, Arizona State University, Tempe, Arizona, United States, 4 , Los Alamos National Laboratory, Los Alamos, New Mexico, United States
Silicon nanowires were grown on different substrates to study the substrate influence on the growth characteristics of the wires. In contrast to recent reports we show a strong dependence of the nanowire growth rate and orientation on the substrate. Initially, catalytic, 1nm thick gold films were thermally evaporated onto hydrogen terminated Si (100), Si (111), and Si (110) substrates, as well as on 500 nm thick SiO2 films, heated to 250oC in a UHV deposition system. Silicon nanowires were grown in a low pressure chemical vapor deposition system by the catalytic vapor-liquid-solid (VLS) technique using 5% SiH4 diluted in H2 at temperatures ranging from 450 to 600oC. All substrates were placed side by side during VLS growth to allow a direct comparison of the nanowire morphology under identical growth conditions. Field emission SEM images show that the nanowires grow predominantly in the <110> and <111> directions. Clear differences in nanowire nucleation density are observed as a function of both substrate type and growth conditions with the nanowire density being much lower on the SiO2 substrate. The length of the nanowires is dependent on the substrate orientation and the growth temperature, with nanowires growing increasingly longer for epitaxial seeding from (100) vs (110) vs (111) substrates, and at higher temperatures. We also show the anomalous high seeding of very small diameter nanowires (≤20nm) on (110) oriented substrate, suggesting the presence of an easier nucleation configuration in this case.
3:45 PM - P2.5
Growth and Passivation of Vertically Aligned Germanium Nanowires for Three Dimensional Nanoelectronics
Hemant Adhikari 1 , Philippe Rouffignac 3 , Kevin Kim 3 , Roy Gordon 3 , Christopher Chidsey 2 , Paul McIntyre 1 Show Abstract
1 Materials Science and Engineering, Stanford University, Stanford , California, United States, 3 Chemistry and Chemical Biology, Harvard University, Cambridge, California, United States, 2 Chemistry, Stanford University, Stanford, California, United States
In the emerging technology of 3-dimensional (3-D) nanoelectronics, vertically aligned nanowires have been proposed to provide a solution to attain ultra high density nanoscale device arrays. Germanium nanowire (GeNW) transistors are very promising components for active device layers above a single crystal silicon substrate because of: (a) the relatively low growth temperature of these nanowires, which is compatible with sub-400°C temperatures expected to be required for 3-dimensional integrated circuits and (b) the high intrinsic hole and electron mobilities of Ge compared to Si. In this paper, we present results of growth of vertically aligned single-crystal germanium nanowires at temperatures of 350°C or less by metal nanoparticle-catalyzed chemical vapor deposition. Single crystal Ge (111), Ge (110), Ge (001) and an epitaxially-grown Ge film on a Si (001) wafer were used to explore the epitaxial relation between the nanowires and the substrate. We have observed homoepitaxial growth of GeNWs along <111> and <110> growth orientations on these substrates. Because wires grown at higher temperatures (350°C) are significantly tapered, a two-temperature growth procedure was devised to obtain epitaxial Ge nanowires of constant diameter. A short high-temperature step to promote nucleation is followed by a longer lower temperature nanowire growth step. Our results indicate that single crystal growth of GeNWs can occur at temperatures substantially less than those required for efficient nucleation of epitaxial nanowires. The defect free nature of the germanium nanowires and their homoepitaxial relationship with the substrate has been studied by high resolution transmission electron microscope imaging and diffraction. Detailed investigation of the surface chemistry of as-grown and air-exposed GeNWs and exploration of various chemical passivation pathways is valuable for understanding and controlling the behavior of devices made from these GeNWs. With the photoemission studies of the surface composition of GeNWs, using a low energy synchrotron source, we find that the wires are initially free of oxide, oxidize relatively slowly in air and can be cleaned of oxide by various aqueous treatments. This is, to our knowledge, the first report of as-grown GeNWs that are free of surface oxide. The control of surface composition demonstrated in this paper forms a sound basis for the deposition of high-quality gate-dielectric layers on the nanowires. We have deposited conformal layers of high dielectric constant hafnium nitride and hafnium oxide layers on the free standing germanium nanowires using atomic layer deposition. In an effort to embed and isolate the nanowire device layers from other layers in a 3 D circuit, the space between the nanowires was filled in with silica by a novel atomic layer deposition technique. The tips of these nanowires, when exposed by chemical mechanical polishing, can serve as seeds for epitaxial growth of another Ge device layer.
P3: Si Nanowires - Doping and Devices
Tuesday PM, April 18, 2006
Room 2024 (Moscone West)
4:30 PM - P3.1
Resistivity Measurements of Intentionally Doped Silicon Nanowire Arrays.
Sarah Dilts 1 , Alexana Cranmer 1 , Suzanne Mohney 1 , Joan Redwing 1 Show Abstract
1 Department of Materials Science and Engineering, The Pennsylvania State University, University Park, Pennsylvania, United States
Resistivity measurements of individual nanowires can be difficult, requiring the use of advanced assembly and lithography techniques. Additionally, contact resistance can dominate nanowire resistance measurements carried out using a simple two-point geometry. In this study, resistivity measurements were performed on high-density vertical arrays of intentionally doped silicon nanowires (SiNWs) synthesized by vapor-liquid-solid growth in nanoporous alumina membranes. Alumina membranes provided a support structure for the aligned growth of the nanowires and also assisted in the formation of electrical contacts via the top and bottom membrane surfaces. The alumina membranes used as templates in this study had a nominal thickness of 60 µm and 200 nm diameter pores. The membrane structures were prepared by initially sputtering a thin layer of silver on the back-side of the membrane followed by the sequential electrodeposition of 5 µm of silver, 30-50 µm of cobalt and 0.25 µm of gold within the pores. Vapor-liquid-solid growth of SiNWs within the pores was then carried out at 500 °C and 13 Torr using SiH4 as the silicon source and trimethylboron (TMB), and phosphine (PH3) for p-type and n-type doping, respectively. The dopant/SiH4 ratio was varied from 2E-2 to 2E-4 for p-type and from 2E-3 to 2E-5 for n-type doping. Circular top-side electrical contacts to the SiNW arrays were formed by e-beam evaporation of Al for p-type and Ti/Pt/Au for n-type SiNWs. For measurements of nanowire resistivity and contact resistance, a series of samples were prepared in which the length of the SiNWs was varied from 5 to 25 µm using a constant dopant/SiH4 inlet gas phase ratio during growth. Plots of total resistance versus SiNW length were used to extract the resistance of the SiNW arrays and average contact resistance. Measurements of nominally undoped nanowire arrays yielded an average resistivity of 2.84 +/- 0.30 Ω-cm. This result was similar to the resistivity of 2.1 Ω-cm determined for individual undoped SiNWs grown out the top of the membrane and assembled into a gated 4-point electrical testbed. The gated measurements reveal that an unintentional p-type impurity is present in SiNWs grown in nanoporous alumina membranes. The addition of dopant precursors during growth resulted in a decrease in the average nanowire resistivity to 0.22 +/- 0.07 Ω-cm for highly doped (TMB/SiH4= 2E-2) p-type wires and 0.034 +/- 0.002 Ω-cm for highly doped (PH3/SiH4= 2E-3) n-type wires.
4:45 PM - P3.2
Post Growth Doping of CVD Grown Silicon Nanowires with Boron
Sarang Ingole 1 , Teresa Clement 1 , Jacob Thorp 1 , Pavan Aella 2 , S Picraux 3 1 Show Abstract
1 Department of Chemical and Materials Engineering, Arizona State University, Tempe, Arizona, United States, 2 Department of Chemistry and Biochemistry, Arizona State University, Tempe, Arizona, United States, 3 , Los Alamos National Laboratory, Los Alamos, New Mexico, United States
Being able to obtain the desired electrical conductivity in silicon nanowires (SiNWs) via controlled doping is critical to the development of SiNW-based devices. From studies reported so far, the introduction of dopant gases during growth has been the preferred approach for electrically doping SiNWs. However in current silicon device technology the most commonly used doping methods involve diffusion and ion implantation. It is thus of technical and scientific interest to explore post growth techniques for doping SiNWs. In the present work we report a newly developed diffusion-based approach for electrical doping of SiNWs with boron. In this approach Spin-On-Dopant spun on an inert substrate serves as a boron source. The boron source and nanowire sample are kept in proximity to each other (~300 µm distance) during the predisposition stage. In a separate stage rapid thermal annealing is performed for drive-in diffusion. By using a separate source wafer for the predeposition stage we are able to better control the extent of boron oxide deposition and thus limit both chemical formation of difficult to remove surface layers as well as sacrificial oxidation of the SiNWs. SIMS analysis on clusters of nanowires doped in this fashion allows qualitative detection of the presence of boron. For studying electrical transport characteristics, the SiNWs are aligned using electric field between previously deposited Cr/Au contacts. These contacts are deposited on an oxidized Si substrate (oxide thickness 500 nm) with 2 µm separation. We also use contacts with 300 nm separation defined by Focused Ion Beam machining for short channel SiNW and four probe measurements. Linear I-V characteristics are observed after low temperature sintering of the contacts. To further confirm doping characteristics, gate voltage and temperature dependent I-V measurements are conducted. From the present I-V characteristics doping concentrations thus obtained are estimated to be in the 1017 to 1019/cm3 range. Work to improve the metal–SiNW contact formation and better control over the number of nanowires between electrodes is underway. We conclude that the present doping approach of Spin-On-Dopant in combination with proximity deposition is promising for post-growth diffusion doping of SiNWs.
5:00 PM - P3.3
Thermally-Oxidized Silicon Nanowires: Structural and Electrical Properties.
Yanfeng Wang 1 , Bangzhi Liu 2 , Tsung-Ta Ho 1 , Sarah Dilts 2 , Suzanne Mohney 2 , Joan Redwing 2 1 , Theresa Mayer 1 Show Abstract
1 Department of Electrical Engineering, The Pennsylvania State University, University Park, Pennsylvania, United States, 2 Department of Materials Science and Engineering, The Pennsylvania State University, University Park, Pennsylvania, United States
There has been considerable interest in bottom-up integration of semiconductor nanowires for their applications in future logic, memory, and sensor circuits. The ability to grow p- and n-type silicon nanowires (SiNWs) of varying carrier density has been demonstrated. However, the subthreshold properties of SiNW field effect transistors (FETs) often exhibit severe hysteresis partly due to their large unpassivated surface area. In this presentation, we will discuss the structural properties of thermally-oxidized p- and n- SiNWs and the electrical results of top-gated FETs fabricated using them, which show improved operational stability as compared to unpassivated SiNW FETs. The SiNWs used in these studies were synthesized by vapor-liquid-solid (VLS) growth from Au catalyst particles using 10% SiH4 in H2 as the silicon gas source, trimethylboron (TMB) as the p-type dopant, and phosphine (PH3) as the n-type dopant. The ratio of TMB or PH3 to SiH4 was varied from 0 to 10-2 to modulate the hole or electron carrier concentration in the SiNWs. Dry oxidation of the as-grown SiNWs was carried out at temperatures between 700 and 1000oC after removing the Au catalyst particles by wet etching and cleaning the NW surface to remove residual metal contaminants. The oxide thickness and interfacial roughness were investigated using transmission electron microscopy. These measurements show that the oxidation rate of the SiNWs is considerably faster than that observed on planar silicon substrates, and that the interface between the SiNW and the thermal oxide is very smooth. As-grown and thermally-oxidized SiNWs were integrated into top- and back-gated test structures. The breakdown field strength of a 10-nm thick layer of SiO2 was measured by probing between the top gate and the source of the FET, and was found to be approximately 5×106 V/cm, which is comparable to that observed for planar silicon samples. Significantly less hysteresis in the subthreshold characteristics was observed for different sweep rates and directions in top-gated, thermally-oxidized SiNW FETs as compared to back-gated, as-grown SiNW FETs. This improvement could be due in part to the improved passivation provided by the SiO2 shell as well as the smaller exposed surface area of the top-gated FETs. Top-gated p- and n- SiNW FETs have small subthreshold slope of ~ 0.25 V/dec and high ON/OFF ratios of ~ 105. These results demonstrate that SiO2 grown by thermal oxidation of the as-grown SiNWs can be used as a gate dielectric that improves the operational stability of SiNW FETs.
5:15 PM - P3.4
Vertical Silicon Nanowire Field Effect Transistors.
Joshua Goldberger 1 , Allon Hochbaum 1 , Rong Fan 1 , Peidong Yang 1 Show Abstract
1 Chemistry, UC Berkeley, Berkeley, California, United States
Silicon nanowires have received considerable attention as transistor components because they represent a facile route towards sub-100 nm single-crystalline Si features with minimal surface roughness. Typically, silicon nanowire transistors have a horizontal planar layout with either a top or back gate geometry. However, the difficulty in reliably assembling ultra-high density planar nanowire circuits, combined with the performance limitations of the horizontal device geometry may ultimately hinder nanowire-based electronics from realizing their full potential. Pushing the transistor geometry into the third dimension would result in ultra-high transistor densities without the need for multi-step post-growth nanowire alignment processes. In addition, a vertical nanowire geometry promises enhanced transistor performance due to the enhanced gate control efficiency in its surround-gate design. Herein we demonstrate the integration of vertically grown Si nanowire arrays into vertical field effect transistors with a surround-gate architecture. These first-generation vertically-integrated nanowire field-effect-transistors (VINFETs) exhibit electronic properties that are comparable to traditional metal-oxide silicon field effect transistors, suggesting that further optimization of this device structure may make them competitive with advanced solid state electronic devices, e.g. double-gate Fin field-effect transistors (FINFET), for future nanoelectronic devices. This presentation will focus on the fabrication and properties of our VINFET devices.
5:30 PM - P3.5
A Novel Cross-bar Structure Toward Ultrahigh-density Nanowire Devices.
Dunwei Wang 1 , Bonnie Sheriff 1 , James Heath 1 Show Abstract
1 , Caltech, Pasadena, California, United States
Nanowire or nanotube electronic devices, such as field effect transistors, memory and logic, units have been built by various groups on a wide range of materials with different structures. The research focus, however, have been mostly devoted to single unit functionality demonstration. For large scale integration toward comprehensive functionalities, routing of individual units requires conventional photo or e-beam lithography techniques. In this context, scaling of nanostructure devices still remains challenging due to the lack of advantageous integration schemes despite the small dimensions offered by nanostructures themselves. Here we present a novel cross-bar structure for ultrahigh-density devices. This structure is realized on highly order Si nanowires ~10nm in diameter and a spacing pitch less than 20nm, fabricated through superlattice nanowire pattern transfer (SNAP). Selectively doped p- and n-type Si nanowires building blocks as parallel arrays are fabricated on SiO2 substrates. Ohmic contacts and gate electrodes are formed perpendicular to the arrays, serving as power supply, input and output. Nanowire selection for different functionalities is realized by altering gate dielectric materials, either high-k or low-k to select or deselect certain nanowires. Complementary logic devices are realized using this scheme and it is also demonstrated that cross-bar structure is a generic approach toward ultrahigh-density nanowire devices.
5:45 PM - P3.6
Fabrication and Post-growth Doping of Silicon Nanowire for Novel Nano-electronic Devices.
Kumhyo Byon 1 , D. Tham 1 , A. Johnson 2 , J. Fischer 1 Show Abstract
1 Materials Science and Engineering, University of Pennsylvania, Philadelphia, Pennsylvania, United States, 2 Physics and Astronomy, University of Pennsylvania, Philadelphia, Pennsylvania, United States
One-dimensional silicon nanowires (SiNWs) are attractive materials for future nanoelectronic applications. Reliable control of the carrier type and concentration is crucial for the application of these nanowires to working devices and integrated systems. In this work, field effect transistors (FETs) were fabricated using both as-grown p-SiNWs and post-growth n-doped SiNWs. Single crystalline silicon nanowires (SiNWs) sheathed with oxide were synthesized by thermal evaporation without the use of catalyst. FET devices from p-type source materials behave as p-channel devices with channel mobilities 1 - 10 cm2 V -1 s -1. Using bismuth vapor, the as-grown SiNWs were doped into n-type materials with various doping concentrations depending on the oxide sheath thickness. The majority carriers in SiNWs can therefore be controlled by choosing proper vapor phase species for dopant. We anticipate that the presented fabrication and doping technique can be used to make more sophisticated devices such as diodes or bipolar transistors by selective patterning and doping of the SiNWs in the future.
Margit Zacharias Max-Planck-Institute of Microstructure Physics
Walter Riess IBM Research GmbH
Peidong Yang University of California-Berkeley
Younan Xia University of Washington
P4: Si Nanowires - Structure
Wednesday AM, April 19, 2006
Room 2024 (Moscone West)
10:00 AM - P4.1
Surface Control of Si Nanowire Electronic Structure.
Paul Leu 1 , Kyeongjae Cho 1 Show Abstract
1 , Stanford University, Stanford, California, United States
Semiconductor nanowires (NWs) are promising nanomaterials for diverse nanodevice applications. NW electronic and photonic devices have been experimentally demonstrated, and NW photonic devices can be used to develop tunable sub-wavelength photonic devices. NW band gaps show strong dependence on their diameters due to quantum confinement effects, and it is possible to tune the band gap by controlling NW diameter. The silicon nanowire (SiNW) is a well known example of NWs, and SiNW diameters can be controlled by controlling the size of the Au nanoparticle catalysts used during chemical vapor deposition (CVD) growth of SiNWs. However, the effects of chemical modification of SiNW surface is not well investigated even though silicon surface modifications are frequently used in microelectronic device processes such as HF treatment of Si surface to remove silica and terminate the surface with Si-H bonds. In this study, we have performed detailed ab initio simulations using density functional theory (DFT) method to investigate the effects of oxide, hydrogen, and halogen surface species on the SiNW electronic structure . The result shows that the surface chemical bonding change has stronger effects on the NW electronic structure (comparable to those of quantum confinement effects or even larger for some cases). A detailed analysis of the electronic structure and energetics is performed for different sized nanowires, and the results predict that the NW electronic structure can be controlled by controlling the chemical modification of NW surface. This prediction opens up new possibilities for controlling nanowire band gap and optical properties by through surface chemistry. Furthermore, this result indicates a possibility of developing SiNW chemical sensor based optical detection (rather than more commonly known electronic detection) by monitoring the optical response of NWs under the presence of chemical species [2, 3].  S. Peng and K. Cho, “Chemical Control of Nanotube Electronics,” Nanotechnology 11, 57 (2000). S. Peng and K.Cho, “Ab Initio Study of Doped Carbon Nanotube Sensors,” Nano Lett. 3(4), 513-517 (2003). S. Peng, K. Cho, P. Qi, and H. Dai, “Ab initio Study of CNT NO2 gas sensor,” Chem. Phys. Lett. V.387 p.271-276 (2004).
10:15 AM - P4.2
Raman Spectroscopy of Silicon Nanowires.
Andrea Ferrari 1 , Stefano Piscanec 1 , Mirco Cantoro 1 , Stephan Hofmann 1 , Alan Colli 1 , John Robertson 1 Show Abstract
1 Engineering, University of Cambridge, Cambridge United Kingdom
We measure the Raman spectra of silicon nanowires  produced by plasma enhanced chemical vapor deposition and oxide assisted growth [2,3]. In contrast to what often assumed, we show that local heating plays a major role in Raman spectroscopy of Si nanostructures. The Raman spectra strongly change as a function of laser power, since the low thermal conductivity of the nanowires results in intense heating under the laser beam . This contrasts with bulk Si, where no heating is observed for similar laser power. The local temperature on SiNWs can reach several hundreds K for an excitation power of ~2 mW [1,4], which is a typically power level in micro-Raman measurements in other materials, such as carbon nanotubes. Only by using extremely low laser power and low ambient temperatures we can eliminate the thermal effects and study the effects of phonon confinement on the Raman spectra . Unlike dots, wires are not confined along the axis, whilst nano-ribbons are confined only in one dimension. Thus, the trends in the peak position and width differ and allow us to identify these nanostructures. The diameter derived by phonon confinement is in good agreement with TEM measurements. For high power measurements the peak positions are significantly lower than what predicted by the confinement theory. To fully account for the measured spectra it is necessary to include an-harmonic phonon effects  and consider the in-homogeneous nature of the heating under the Raman microscope . The Raman induced heating effects are not peculiar to Si nanostructures, but are expected to be a general finding in semiconductor nanowires and nanocrstals.1.S. Piscanec et al. Phys. Rev. B 68, 241312(R) (2003)2.S. Hofmann et al. J. Appl. Phys. 94, 6005 (2003)3.R. Q. Zhang et al., Adv. Mater. 15, 635 (2003).4.R. Gupta et al., Nano Lett. 3, 627 (2003).5.M. Balkanski et al., Phys. Rev. B 28, 1928 (1983).
10:30 AM - P4.3
Strain in Semiconductor Nanowire Heterostructures
S. Picraux 1 3 , A Batwal 3 , P Peralta 3 , J Taraci 3 , M Hytch 2 , T Clement 3 , D Smith 3 , M McCartney 3 , Jeff Drucker 3 Show Abstract
1 , Los Alamos National Laboratory, Los Alamos, New Mexico, United States, 3 , Arizona State University, Tempe, Arizona, United States, 2 , Centre National de Recherche Scientifique, Vitry-sur-Seine France
10:45 AM - P4.4
Simulation of Semiconducting Nanowires with Core-shell Structures.
Rana Biswas 1 , Bicai Pan 2 Show Abstract
1 Dept. of Physics & ECpE, MRC, Ames Lab, Iowa State University, Ames, Iowa, United States, 2 Physics, Univ of Science and Technology of China, Hefei China
P5: Transport and Devices
Wednesday PM, April 19, 2006
Room 2024 (Moscone West)
11:30 AM - **P5.1
Quantum Coherent Transport in Semiconductor Nanowires.
Jorden van Dam 2 , Yong-Joo Doh 2 , Aarnoud Roest 3 , Erik Bakkers 3 , Leo Kouwenhoven 2 , Silvano De Franceschi 1 2 Show Abstract
2 Kavli Institute of Nanoscience , Delft University of Technology, Delft Netherlands, 3 , Philips Research Laboratories, Eindhoven Netherlands, 1 , CNR TASC-INFM , Trieste Italy
12:00 PM - P5.2
Electrical Characteristics of Epitaxially Integrated InP Nano-bridges Between Silicon Electrodes.
M. Saif Islam 1 , Ibrahim Kimukin 1 , T. I. Kamins 2 , Sung Soo Yi 3 , G. Girolami 3 , Jun Amano 3 Show Abstract
1 Department of Electrical and Computer Engineering, University of California Davis, Davis, California, United States, 2 Quantum Science Research, Hewlett-Packard Laboratories, Palo Alto, California, United States, 3 Molecular Technology Laboratory, Agilent Technologies, Palo Alto, California, United States
Heteroepitaxial growth of III-V compound semiconductors on Si can open exciting opportunities for Si optoelectronics. Almost 8% lattice and large thermal expansion mismatch along with differences in crystal structures, have hindered progress in epitaxial integration of III-V materials in the form of thin films on Si. However, metal catalyzed III-V nanowires were found to epitaxially grow on Si due to the small cross-sections of nanowires that accommodates large lattice mismatch and help relieve strain. This work presents a bridging technique that connects metal-catalyzed InP nanowires between pre-fabricated Si electrodes. Two opposing vertical and electrically isolated Si surfaces are fabricated using coarse optical lithography, along with wet and dry etching. Lateral InP nanowires are then grown from one vertical surface by metal-catalyst-assisted chemical vapor deposition (CVD) and connected to the other vertical surface during growth, forming mechanically robust 'nanobridges'. The InP nano-bridges make mechanically strong and robust connection at both vertical Si surfaces and resist considerable force. By forming the structure on a silicon-on-insulator substrate, electrical isolation is achieved. High-resolution TEM measurements show that InP nanowires are single-crystalline and of high quality. Electrical measurements indicate a potential barrier between the Si electrode and the p-doped InP nanowires. The Si-InP interface characteristics are studied to evaluate the barrier height. Photo-excited carriers were observed in the nanowires under optical illuminations. The growth and bridging of these InP nanowires can be integrated with existing silicon processes and can offer a new degree of freedom in the design of heterojunction nanodevices combined with Si technology.
12:15 PM - P5.3
Vertical Silicon Nanowire Surround-Gate Field-Effect Transistor Realized.
Heike Riel 1 , Volker Schmidt 2 , Siegfried Karg 1 , Stephan Senz 2 , Heinz Schmidt 1 , Ute Drechsler 1 , Oliver Hayden 1 , Walter Riess 1 , Ulrich Goesele 2 Show Abstract
1 Science & Technology, IBM Research GmbH, Rueschlikon Switzerland, 2 , Max Planck Institute of Microstructure Physics, Halle Germany
Semiconducting nanowires have recently attracted considerable attention as the ongoing miniaturization in microelectronics demands new, innovative fabrication and device concepts. Owing to their potential compatibility with existing CMOS technology, in particular, epitaxially grown silicon (Si) nanowires are considered to be one of the most promising candidates for future logic and memory elements.In this paper a generic process flow for fabricating vertical surround-gate field-effect transistors (VS-FET) from epitaxially grown Si nanowires is described and device characteristics are presented. The catalyst for the nanowire growth was patterned by electron beam lithography resulting in well defined arrays of vertical Si nanowires grown on Si (111) substrates.We demonstrate the fabrication processes using n-type silicon nanowires grown on a p-type substrate in ultra-high vacuum using gold as catalyst and silane as precursor gas. The VS-FET fabrication consists of various deposition and etching steps, and has the advantage that no chemical mechanical polishing is required. Moreover, the process can be used to fabricate individual as well as arrays of nanowire VS-FETs. Electrical characterization was carried out on vertical ungated n-doped and p-doped two-terminal devices and gated nanowire FETs. Single nanowires as well as parallel contacted arrays of about 10^4 nanowires were tested. The measured transistor output and transfer characteristics indicate the behavior of an inversion mode driven FET similar to a conventional p-channel MOSFET. Temperature-dependent measurements are also reported.
12:30 PM - P5.4
Low-Temperature Solid-Phase Epitaxy of Defect-Free Aluminum p+-doped Silicon for Nanoscale Device Applications.
Yann Civale 1 , Lis Nanver 1 , Peter Hadley 2 , Egbert Goudena 1 , Henk van Zeijl 1 , Hugo Schellevis 1 Show Abstract
1 Laboratory of ECTM - DIMES, Delft University of Technology, Delft Netherlands, 2 Kavli Institute of Nanoscience, Delft University of Technology, Delft Netherlands
The growth of semiconducting nanowires sometimes takes place below the eutectic temperature of the catalyst particle . In these cases, a solid-phase epitaxy (SPE) mechanism has been suggested to describe the growth of the nanowires . In SPE, atoms of the semiconductor diffuse through a solid transport metal and attach themselves to crystal at the metal/semiconductor interface. Here we describe the growth of nanoscale silicon islands by SPE using aluminum as the transport metal. Contact windows down to 100 nm in size are opened through a thermally oxidized mono-crystalline <100> Si substrate. A thin layer of aluminum and amorphous silicon is then sputtered in the same vacuum system. This stack is annealed in nitrogen at temperatures between 350°C and 500°C, far below the 577°C eutectic point of the Al/Si alloy. Silicon crystals grow preferably on the exposed silicon rather than on the surrounding oxide. In the initial stages of growth, crystals grow along the edges of the contact windows presumably driven by stress until a single crystal fills the entire contact window. The height of SPE-Si was determined by the initial Al thickness. This material, that is p+-doped due to aluminum, has been used to fabricate ultra-abrupt ultra-shallow p+n diodes, contacts, and p+np bipolar transistors. Despite the low-processing temperature, near-ideal device characteristics were reproducibly obtained, indicating an exceptionally defect-free epitaxial process. The quality of the SPE-Si was extensively investigated by fabricating electrical devices. The contact resistance to both p- and p+-bulk silicon regions was found to be low-ohmic and the total contact resistivity was measured to be at most 10-7 Ω.cm2. On n-Si, nearly-ideal p+n diodes are formed, with an ideality factor of 1.02. A SPE-Si region was used as emitter in p+np bipolar transistors. An analysis of the transistor characteristics indicates near-ideal forward base and collector currents and an Al-doping around 1.2 × 1018 cm-3.In view of the processing temperatures, the quality of the SPE p+-Si presented here is remarkable. The electrical characterization shows clearly that very controllable growth conditions have been found whereby the contact window is entirely filled with an exceptionally low-defect density at the interface with bulk-Si. Ultra-abrupt ultra-shallow junctions with a 25 nm deep p-doped region were obtained. All in all, these properties make this a very versatile fully CMOS compatible module for the integration of nanoscale silicon devices. T. I. Kamins, R. Stanley Williams, D. P. Basile, T. Hesjedal and J. S. Harris, J. Appl. Phys., Vol. 89, pp. 1008-1016, 2001. A. I. Persson, M. W. Larsson, S. Stenström, B. J. Ohlsson, L. Samuelson, and L. R. Wallenberg, Nature Materials, Vol. 3, pp. 677-681, 2004.
12:45 PM - P5.5
1D Hole Gas in Ge/Si Nanowire Heterostructures and Demonstration of High Performance Field Effect Transistors.
Jie Xiang 1 , Wei Lu 1 , Yongjie Hu 1 , Yue Wu 1 , Hao Yan 1 , Charles Lieber 1 2 Show Abstract
1 Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States, 2 Division of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts, United States
Nanowires and nanotubes are promising building blocks for nanoelectronics because their unique 1D electronic structure could yield improved performance compared to conventional planar devices. For example, long carrier mean-free-paths and ballistic transport have been demonstrated in carbon nanotubes. Yet, the fundamental 1D quantum confinement effect on transport in semiconducting nanowires has not been observed before primarily due to poor contacts and dopant scattering. Here we employed the idea of band structure engineering to create a 1D hole gas in undoped epitaxial Ge/Si core/shell nanowire heterostructures. Similar to 2D electron and hole gases in planar semiconductor heterostructures, the valence band offset between Si shell and Ge core confines holes in the Ge channel, forming a quantum well structure. We show that transparent contacts to the hole gas can be made in a reproducible fashion and demonstrate ballistic transport through discrete 1D subbands for the first time in free-standing semiconductor nanowires. To show the potential of these clean 1D quantum well nanostructures for device applications, we further fabricated single Ge/Si nanowire field-effect transistors (FETs) using high-k dielectrics with a metal top gate geometry. The clean hole-gas system and enhanced gate coupling from the high-k dielectric afford very high device performance. Significantly, these results are the best achieved in nanowire FETs, and moreover, the raw performance data is several times better than state-of-the-art planar Si MOSFETs. In addition, studies investigating the scaling of device speed as a function of channel length and the effect of novel gate structures to control ambipolar behavior will also be discussed. Our Ge/Si core/shell nanowire heterostructures exhibit great potential as a new platform for the fundamental study of 1D transport as well as new building blocks for nanoscale electronics.
P6: Nanowire Heterostructures
Wednesday PM, April 19, 2006
Room 2024 (Moscone West)
2:30 PM - **P6.1
Nanowires as Building Blocks in Quantum-based Devices.
Lars Samuelson 1 Show Abstract
1 Solid State Physics / the Nanometer Structure Consortium, Lund University, Lund Sweden
In this talk I will discuss growth of semiconductor nanowires based on epitaxial nucleation of nanowires from lithographically defined nanoparticles, allowing arrays of position- and dimension-controlled nanowires to be formed. Of special value for studies of physics of quantum dot systems and for applications in electronics and photonics is the opportunity to form designed and abrupt heterostructures within nanowires. I will give examples of our studies of electrical and optical properties of nanowire structures as well as devices implemented in this technology, for instance for single-electronics, resonant tunneling and for wrap-gate FET applications. I will conclude with examples of new opportunities offered by nanowires, e.g. in neuroscience and for nanoelectromechanical applications.
3:00 PM - P6.2
Three-dimensional Nanoscale Composition Mapping of Semiconductor Nanowires.
Daniel Perea 1 , Lincoln Lauhon 1 , Jonathan Allen 1 , Steven May 1 , Bruce Wessels 1 2 , David Seidman 1 Show Abstract
1 Materials Science and Engineering, Northwestern University, Evanston, Illinois, United States, 2 Electrical Engineering and Computer Science, Northwestern University, Evanston, Illinois, United States
3:15 PM - P6.3
Nanowire Radial Heterostructures as High Electron Mobility Transistors.
Yat Li 1 , Jie Xiang 1 , Fang Qian 1 , Silvija Gradecak 1 , Yue Wu 1 , Hao Yan 1 , Charles Lieber 1 2 Show Abstract
1 Department of Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States, 2 Division of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts, United States
Semiconductor nanowires are attractive building blocks for nanoscale electronic devices. The ability to assemble, improve and control the properties of these building blocks is critical in moving toward nanoscale integrated electronic circuits. In this regard, we report a general strategy to synthesize GaN/AlN/AlGaN nanowire heterostructures and their implementation as nanoscale high electron mobility transistors (HEMTs). GaN/AlN/AlGaN nanowire heterostructures were synthesized with atomic-level control using metal-organic chemical vapor deposition. Electron microscopy studies revealed that the nanowire heterostructure are dislocation-free single crystals, with radial modulation of composition and thickness well-controlled during synthesis. Electrical transport measurements on undoped GaN/AlN/AlGaN nanowire heterostructures demonstrate the existence of quantum confined electron gas, and moreover, yield high electron mobilities of 3100 cm2/V-s at room temperature and 21,000 cm2/V-s at 5 K. These new nanowire heterostructures have been used to assemble field-effect transistors with high-k dielectrics that exhibit outstanding device performance. GaN/AlN/AlGaN nanowire HEMTs offer great promise as a new building block for nanoscale integrated electronic circuits, high-sensitivity detectors and complementary macroelectronics on unconventional substrates.
3:30 PM - P6.4
Growth and Characterization of InP/InAs/InP Core-multishell Heterostructure Nanowires by Selective-area Metalorganic Vapor Phase Epitaxy.
Junichi Motohisa 1 2 , Premila Mohan 1 , Katsuhiro Tomioka 1 2 , Takashi Fukui 1 2 Show Abstract
1 Research Center for Integrated Quantum Electronics, Hokkaido University, Sapporo Japan, 2 Graduate School of Information Science and Technology, Hokkaido University, Sapporo Japan
3:45 PM - P6.5
MOCVD Synthesis and Characterization of Aligned III-Nitride Nanowire and Heterostructure Nanowire Arrays.
George Wang 1 , J. Randall Creighton 1 , A. Alec Talin 1 , Paula Provencio 1 , Don Werder 2 Show Abstract
1 , Sandia National Laboratories, Albuquerque, New Mexico, United States, 2 , Los Alamos National Laboratory, Los Alamos, New Mexico, United States
Nanowires based on the direct bandgap semiconductor Group III nitride (AlGaInN) materials system are attractive due to their potential in novel optoelectronic applications, including LEDs, lasers, high power transistors, and sensors. We have employed a metal-organic chemical vapor deposition (MOCVD) process to synthesize highly aligned arrays of single-crystalline GaN nanowires in a standard cold-wall rotating disk reactor on 2-inch diameter sapphire wafer substrates without the use of a template. SEM and TEM analysis indicate that the nanowires share a common growth direction and have aligned facets. Interestingly, the majority of the nanowires do not have a catalyst droplet at the tip, suggesting the growth differs from the standard vapor-liquid-solid process. Building on this technique, we have also been able to synthesize radial heterostructure nanowire arrays consisting of a GaN cores and various III-nitride shell materials, including AlN, InN, and AlGaN, and InGaN. In this presentation, several challenges and issues regarding control of the nanowire and heterostructure growth process will be discussed. We have found that the growth conditions, particularly temperature, have a strong effect on the structural, optoelectronic, and electrical properties of the nanowires. Additionally, the choice of substrate and the catalyst preparation play critical roles in the density, uniformity, and alignment of the nanowire arrays. Preliminary data on the use of lithographically patterned templates to control the growth of GaN nanowires will also be presented. The growth processes and reactor environment employed in this study are typical of those used to synthesize device-quality III-nitride films and should be scalable to larger commercial reactors and substrates.
P7: Sensors and Devices
Wednesday PM, April 19, 2006
Room 2024 (Moscone West)
4:30 PM - P7.1
General and Powerful Platform for Large-scale, Label-free, Parallel Electrical Detection of Biomolecules by Ultrasensitive Nanowire Transistor Arrays.
Gengfeng Zheng 1 , Fernando Patolsky 1 , Charles Lieber 1 2 Show Abstract
1 Department of Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States, 2 Division of Engineering and Applied Science, Harvard University, Cambridge, Massachusetts, United States
Nanoscale materials offer unique and powerful opportunities for detection of biological and chemical species central to many areas of healthcare and the life science, ranging from disease diagnosis to the discovery and screening of new drug molecules. Here we demonstrate a general and powerful platform using nanowire transistor arrays for large-scale, label-free, real-time, parallel electrical detection of a variety of biomolecules ranging from proteins, nucleic acids to viruses. Composed of hundreds of individually electrically addressable nanowire devices with highly sensitive and reproducible performances, these nanowire arrays can be controllably modified by solution arrays of antibodies or cell-surface receptors with precise device registration, and show discrete conductance changes characteristic of highly selective binding and unbinding of multiple target biomolecules, thus providing a high-throughput, real-time parallel detection and rapid screening of libraries of biomolecules. Studies show that proteins, nucleic acids and viruses can be simultaneously detected at femtomolar concentrations with high selectivity even in undiluted serum samples, and that simultaneous incorporation of control nanowires in a single array enables discrimination against false positive/negative signals. Moreover, both electrokinetic effects and noise analysis to demonstrate the diversified applications of our nanowire sensor system such as extracting single molecule binding kinetics. The integrated nanowire sensor array platform opens up substantial opportunities for diagnosis and treatment of complex diseases such as cancer, detection of biological threats, and fundamental proteomic and biophysical studies.
4:45 PM - P7.2
Synthesis and Applications of Single-crystalline Indium Oxide Nanowires.
Daihua Zhang 1 , Bo Lei 1 , Koungmin Ryu 1 , Fumiaki Ishikawa 1 , Chongwu Zhou 1 Show Abstract
1 Electrical Engineering, University of Souther California, Los Angeles, California, United States
Single-crystalline indium oxide nanowires were synthesized using a laser ablation method and characterized using various techniques. Precise control over the nanowire diameter down to 7 nm was achieved by using monodispersed gold clusters as catalytic nanoparticles. In addition, field effect transistors with on/off ratios up to 104 were fabricated based on individual nanowires. Detailed electronic measurements revealed that the In2O3 nanowires are n-type semiconductors with a typical electron mobility of ~ 100 cm2/Vs. Furthermore, we studied the chemical sensing properties of our In2O3 nanowire transistors at room temperature. Upon exposure to a small amount of NO2, the nanowire transistors showed a decrease in conductance of up to six orders of magnitude, in addition to substantial shifts in the threshold gate voltage. Our devices exhibit significantly improved chemical sensing performance compared to existing solid-state sensors in many aspects, such as the sensitivity, the selectivity, the response time and the lowest detectable concentrations. We have also demonstrated the use of UV light as a “gas cleanser” for In2O3 nanowire chemical sensors, leading to a recovery time as short as 80 seconds.
5:00 PM - P7.3
Three-Armed Cadmium Sulfide Nanowires
Oliver Hayden 1 3 , David C. Bell 2 , Andrew B. Greytak 1 Show Abstract
1 Department of Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States, 3 , IBM Research Laboratory, Rueschlikon Switzerland, 2 Center for Imaging and Mesoscale Structures, Department of Physics, Harvard University, Cambridge, Massachusetts, United States
Here, we present the synthe