An integrated process has been developed for vapor deposition of all the layers needed to prepare a damascene structure in porous low-k dielectric for electroplating with copper. As a first step, the open pores were sealed with one atomic layer deposition (ALD) cycle that closes the pores with about 6 nm of smooth silica. At the same time, less than 0.4 nm of silica (less than 2 mono-layers) deposited on the copper at via bottoms that had been protected by a self-assembled monolayer (SAM). This residual silica and SAM can be removed from the copper by ion etching methods normally used to clean the copper at via bottoms. Next a diffusion barrier of amorphous tungsten nitride (WN) ~ 2 nm thick was deposited by ALD or by CVD. An adhesion-promoting layer of ruthenium ~ 2 nm thick was formed by ALD or CVD on the WN. Electron microscopy and chemical etch tests demonstrated complete coverage by the ruthenium film. Finally copper seed layers were made by ALD or CVD with a non-fluorine-containing precursor. Quantitative 4-point bend tests showed very strong adhesion (> 20 J m^-2) when the metal layers were deposited without an air break. The resulting completely conformal structure (aspect ratio 4:1) had a sheet resistance less than 50 ohms per square for a copper seed layer thickness of less than 4 nm. Electroplating copper on this structure showed complete trench-filling without voids. The structure also survived chemical-mechanical planarization, forming electrically continuous copper in serpentine trenches.

The integration of low and ultralow-k SiCOH dielectrics in the interconnect structures of VLSI chips involves complex stacks with multiple interfaces. Successful fabrication of reliable chips requires, among other, strong adhesion between the different layers of the stacks. A critical interface in the dielectric stack is the interface between the SiCH(N) diffusion cap and the SiCOH intra- and interlevel dielectric (ILD). It was observed that, due