Symposium Organizers
Srini Chakravarthi Texas Instruments
Reza Arghavani Applied Materials
Gerhard Klimeck Purdue University
G1: Challenges / Directions of Current CMOS
Session Chairs
Reza Arghavani
Srini Chakravarthi
Tuesday PM, April 10, 2007
Room 3005 (Moscone West)
9:00 AM - **G1.1
Future Direction of Strained Si/channel MOSFETs for Advanced 90 to 22nm Logic Technologies
Scott Thompson 1
1 Electrical & Computer Engineering, University of Florida, Gainesville, Florida, United States
Show AbstractAbstract—Experimental data along with a detailed theoretical picture is given for the physics of strain effects in semiconductors and Metal-Oxide-Semiconductor- Field-Effect-Transistors (MOSFETs). MOSFET piezoresistance coefficicents are measured on industrially fabricated 30-100nm gate length Si, SiGe and Ge channel MOSETs with SiO2 and HfO2 gate dielectrics. The data is interpreted considering energy band splitting and warping, subband alignment, effective mass change, and phonon scattering alteration. These effects are investigated by symmetry, tight-binding and kp methods for in-plane biaxial and longitudinal and transverse uniaxial stresses. From these data, we intreprete and project the past and future direction of strained Si for advance 90 to 22nm logic technologies.
9:30 AM - **G1.2
Mobility Engineering in Si CMOS.
Serge Biesemans 1 , Peter Verheyen 1 , Philippe Absil 1 , Thomas Hoffmann 1
1 CMOSDR, IMEC, Leuven Belgium
Show AbstractTuesday, April 10New Presenter - *G1.2 @ 8:30 amMobility Engineering in Si CMOS. Peter Verheyen
10:00 AM - G1.3
Strain-Transfer Structure Beneath the Transistor Channel for Increasing the Strain Effects of Lattice-Mismatched Source and Drain Stressors.
Yee-Chia Yeo 1 , Kah-Wee Ang 1 , Jianqiang Lin 1 , Chee Lam 1
1 Electrical and Computer Engineering, National University of Singapore, Singapore Singapore
Show AbstractStrain-induced mobility enhancement is an attractive way to enhance the performance of metal-oxide-semiconductor field effect transistors. Lattice-mismatched source/drain (S/D) stressors such as silicon-germanium (SiGe) S/D for p-FET and silicon-carbon (Si:C) for n-FET has been investigated. In this paper, we introduce a new concept of incorporating an additional structure beneath the transistor channel region to increase the strain-transfer efficiency of the S/D stressors. The additional structure is lattice-mismatched with respect to the overlying Si-channel and/or with respect to the S/D stressors. For n-FET, a SiGe region integrated beneath the Si-channel enhances the magnitude of the tensile strain due to the Si:C S/D, and this leads to increased strain effects. For p-FET, a Si:C region beneath the Si-channel enhances the strain effect due to the SiGe S/D. This additional structure is called a strain-transfer structure. Extensive numerical simulations were performed using the finite element method to explain how the new strain-transfer structure works. Profiles of the various strain components in the transistor channel were obtained. Dependence of the strain effect on geometrical features of the new transistor structure will also be reported. Experimental realization of the device structures will also be reported. Electrical results from nanoscale transistors confirm the strain enhancement effects due to the strain-transfer structure.
10:15 AM - G1.4
A Theoretical Investigation of Selected Silicides and Germanides.
Alex Demkov 1 , Manish Niranjan 1 , Leonard Kleinman 1
1 Physics, The University of Texas, Austin, Texas, United States
Show Abstract10:30 AM - G1.5
Design Guidelines for High Mobility Channel Bulk n-MOSFETs
Lee Smith 1 , Makoto Fujiwara 2 3 , Krishna Saraswat 2 , Yoshio Nishi 2 , Dipu Pramanik 1
1 , Synopsys, Inc., Mountain View, California, United States, 2 , Stanford University, Stanford, California, United States, 3 , Toshiba Corporation, Yokohama, Kanagawa, Japan
Show AbstractTuesday, April 10Transferred Poster G5.19 to G1.5 @ 9:30 amDesign Guidelines for High Mobility Channel Bulk n-MOSFETs.Lee Smith
10:45 AM - G1.6
Simplified Surface Preparation for GaAs Passivation Using Atomic-layer-deposited High-k dielectrics.
Peide (Peter) Ye 1 , Yi Xuan 1 , Han-Chung Lin 1
1 School of ECE, Purdue University, West Lafayette, Indiana, United States
Show AbstractTuesdday, April 10Transferred Poster G5.5 to G1.6 @ 9:45 amSimplified Surface Preparation for GaAs Passivation Using Atomic-layer-deposited High-k dielectrics. Peide (Peter) Ye
11:00 AM - G1: ChallCMOS
BREAK
G2: Prospective Materials for CMOS Channels
Session Chairs
Reza Arghavani
Srini Chakravarthi
Tuesday PM, April 10, 2007
Room 3005 (Moscone West)
11:30 AM - **G2.1
New Channel Materials and the Ultimate MOSFET
Mark Lundstrom 1
1 School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana, United States
Show AbstractSilicon CMOS transistors continue to be pushed to smaller and smaller dimensions, but the endof silicon scaling is in sight. The original choice of silicon was driven by the properties of itsnative oxide, SiO2. With the development of high-k gate dielectrics, the use of differentsubstrate materials for the channel of a MOSFET is worth considering. This raises somequestions. What are the desired properties of a semiconductor to produce a high performanceMOSFET with the smallest possible dimensions? Of the available semiconductors, which one(s)have the best properties for a MOSFET? What is the maximum benefit in device performancemetrics that could result, and what would be the corresponding improvement in circuitperformance? This talk will address the question: if we could solve the materials and fabricationchallenges and build a high-quality MOSFET with any channel material we choose, whichmaterial would we select and how much would we benefit?
12:00 PM - G2.2
Metal-Oxide-Semiconductor Field Effect Transistors with InGaAs and GaAs/InGaAs Channels and High-k Gate Dielectric.
Sergei Koveshnikov 1 2 , Serge Oktyabrsky 2 , Vadim Tokranov 2 , Michael Yakimov 2 , Richard Moore 2 , Feng Zhu 3 , Wilman Tsai 1 , Jack Lee 3
1 , Intel Corporation, Santa Clara, California, United States, 2 College of Nanoscale Science and Engineering, University at Albany-SUNY, Albany, New York, United States, 3 Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas, United States
Show AbstractIn this work we study the correlations of the III-V-High-k dielectric interface structure and its chemistry with the formation/passivation of interface states and demonstrate good electrical characteristics of InGaAs and GaAs/InGaAs channel MOSFETs. To avoid Fermi level pinning we employed an amorphous arsenic-doped Si interface passivation layer (α-Si IPL) in-situ deposited on top of III-V channels grown by molecular beam epitaxy. High-k gate stack was further fabricated either in-situ using e-beam evaporation of metallic Hf in reduced vacuum (10-6 to 10-5 Torr) without exposure to air, or ex-situ using physical vapor deposition of HfO2. Transmission electron microscopy revealed high quality atomically clean III-V-Si interface which was stable up to 800 °C; the Si layer remained amorphous. Exposure of the III-V wafers with an α-Si layer to air led to its partial or complete oxidation as revealed by TEM/EDX and x-ray photoelectron spectroscopy. Full oxidation of the Si layer resulted in Fermi level pinning as demonstrated by the frequency dependent capacitance-voltage measurements of the TaN-gated MOS capacitors revealing large stretch-out and frequency dispersion of C-V characteristics. A non-pinned Fermi level was demonstrated on both p-type and n-type InGaAs and GaAs/InGaAs wafers when the α-Si IPL was partially oxidized thus preventing excess of oxygen at the III-V surface. The minimum thickness of the α-Si IPL required to prevent Fermi level pinning was ~0.2 nm and ~1.5 nm for in-situ and ex-situ HfO2 deposition, respectively. Good thermal stability of the III-V-α-Si IPL interface was demonstrated for both in-situ and ex-situ gate stacks making it appropriate for Si implant activation within MOSFET technology. Both depletion mode and enhancement mode (inversion channel) N-MOSFETs were demonstrated with transconductance above 100 mS/mm and mobility up to 1500 cm2/Vs.
12:15 PM - G2.3
Electronic Structure of Si/InAs Composite Channels.
Marta Prada 1 2 , Neerav Kharche 1 , Gerhard Klimeck 1
1 School of Electrical and Computer Engineering, Network for Computational Nanotechnology Purdue University, W Lafayette, Indiana, United States, 2 Physics, University of Wisconsin-Madison, Madison, Wisconsin, United States
Show AbstractAlthough pure InAs has a lighter effective mass and higher mobility than Si, an ultra-scaled Si device may still perform better than an ultra-small InAs device [1]. The co-integration of InAs on top of a thin Si body may provide improved device performance [2]. This work models the electronic structure of such composite channels for three different growth directions: (100), (110), (112). The (110) and (112) growth directions are the technically most relevant, since they balance surface charge dipoles. The calculations are performed with NEMO 3-D [3]. Atoms are represented explicitly in the Valence Force Field (VFF) method [4] to minimize the strain and in the sp3d5s* tight-binding model. The bulk material parameters have been calibrated to match the band-offsets according to Van de Walle’s model solid theory [5]. NEMO 3-D enables the calculation of localized states in the quantum well and their dispersion in the quantum well plane. From this dispersion, the bandgap, its direct or indirect character, and the associated effective masses of the valence and conduction band can be determined. Such composite bandstructure calculations are demonstrated here for the first time. The calculations can then be included in empirical device models [1] to estimate device performance. Concretely this work considers a total constant quantum well thickness of 8nm composed of $Si_{1-x}(InAs)_x$ where x is 0,1,2,3,8nm. The data on the three different lattice orientations in terms of direct/indirect gap, gap energy, electron and hole effective masses are summarized in the associated tables.For samples grown along the (001) direction, Si is a direct bandgap material, and deposition of InAs thin layers reduces only slightly the light-hole effective mass, also decreasing the magnitude of the gap. Pure InAs QW appears to be a direct bandgap material, with a relatively small gap and effective masses of about one order of magnitude smaller than for pure Si QW of equivalent thickness.In contrast, along the (110) and (112)-growth direction, a thin layer of InAs (x>=2nm) causes the new material to be direct-bandgap, decreasing significantly the electronic effective mass and increasing the gap.[1] A Rahman, G Klimeck, and M Lundstrom, 2005 IEEE IEDM, 2005[2] private communication, Dr. Alan Seabaugh, Notre Dame.[3] G Klimeck, et al, Computer Modeling in Engineering and Science 3, 601-642 (2002).[4] P N Keating, Phys. Rev. 145, 637–645 (1966). [5] C G Van de Walle, Phys. Rev. B 39, 1871–1883 (1989)
12:30 PM - **G2.4
Building a CMOS technology with Non-Traditional Materials to Satisfy Digital Requirements.
Douglas Barlage 1 , Mark Johnson 2 , David Braddock 3 , Yawei Jin 1 , Lei Ma 1
1 Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina, United States, 2 Material Science and Engineering, North Carolina State University, Raleigh, North Carolina, United States, 3 , OSEMI , Cannon Falls, Minnesota, United States
Show AbstractThe CMOS architecture has largely dominated massive scaled electronic systems because of the incomparable leakage management that it affords. The creation of the minimum dimension (<10nm) devices using non-Si III-V materials is investigated with simulation and experimental techniques. A standard benchmark is proposed to allow the comparison of an array of semiconductor materials using the bulk properties of the semiconductor materials. This benchmark is verified with simulations. Of considerable note from this work is that distinctly different material properties are required for the source and the drain than the channel of the device to exceed the performance of silicon based devices. The source drain requires a high-mobility with relatively low band gap while the channel material requires a wider band gap to successfully manage the leakage that is unavoidable as the gate length continues to shrink. This is expanded in detail and the heterogeneous-source-drain MOSFET, such as already demonstrated in PMOS manufacturing, is extended to include III-V based materials for N and P type MOSFETs. Based on the preliminary assessment this approach is a logical choice for CMOS extension. Simulation data of this device for an array of III-V materials will be presented. In addition to the materials issues in the channel and source drain, a suitable oxide must be created to allow for successful scaling. Building on knowledge from the high-k on silicon work, materials compatibility for oxides on non-Silicon material is explored. Hetero-structure gate stacks are compared with oxides on non-traditional materials and the oxide compatibility is evaluated for III-V compounds. The findings highlight the underlying challenges associated with creating suitable unpinned interfaces in non-silicon materials.Finally, experimental data is presented for MOS devices created in the III-Nitride based system. As part of the analysis in this work, the mobility evaluation for a given III-V gate stack is presented. This mobility analysis will focus on the calculation for the correct field and charge associated with the gate stack when the material changes as well as the underlying mechanisms that govern charge transport in a typical enhancement mode MOS device. Furthermore the relationship between low field mobility and the impact on current-voltage characteristics is presented. These considerations are critical when choosing a channel material to carry the large amount of charge demanded by the high-performance logic circuits to be manufactured beyond 2015.
G3: Advanced Channel Materials I: (110) Si, Ge
Session Chairs
Srini Chakravarthi
Gerhard Klimeck
Tuesday PM, April 10, 2007
Room 3005 (Moscone West)
2:30 PM - **G3.1
Future Channel Materials and Processes for High Performance CMOS
Devendra Sadana 1 , S. Bedell 1 , J. Souza 1 , A. Reznicek 1 , S. Koester 1 , Yanning Sun 1 , E. Kiewra 1 , J. Ott 1 , K. Fogel 1 , D. Webb 2 , J. Fompeyrine 2 , J. Locquet 2 , M. Sousa 2 , R. Germann 2
1 Advanced Substrate Research, IBM, Yorktown Heights, New York, United States, 2 IBM Zurich Research Laboratory, Säumerstrasse 4 / Postfach , Rüschlikon, CH-8803, Switzerland
Show Abstract CMOS scaling is facing a formidable challenge because of a number of factors including increasing gate leakage current, rising active power due to non-scaled voltage, band-to-band tunneling at high body doping levels, and insufficient source-drain doping for series resistance reduction. Meeting performance targets of 32 nm CMOS and beyond will require innovation at all levels, including system architecture, circuit design, integration, device design and new channel materials. This work is focused to address present and future CMOS performance challenges via advanced materials and processes. Some of the options under consideration include (i) local and global strain, (ii) Si surface orientation, and (iii) non-Si materials including Ge and III-Vs. Challenges associated with each of these options will be examined both at fundamental level as well as at manufacturing level. Key fundamental challenges include relaxation of strain in locally and globally strained Si during processing, surface passivation of III-V materials, and high defectivity in Ge and III-V films grown on Si. Key manufacturing challenges include incompatibility of processes integration between Si and non-Si materials, and lack of infrastructure readiness for non-Si materials. A perspective on performance driven scaling will be presented.
3:00 PM - G3.2
Bonded Layer Thickness Optimization for DSB-HOT.
Angelo Pinto 1 , Sachin Joshi 2 , Y. Huang 3 , Rick Wise 1 , Rinn Cleavelin 1 , Mike Seacrist 4 , Mike Ries 4 , Manfred Ramin 2 , Melissa Freeman 5 , Billy Nguyen 5 , Kenneth Matthews 5 , Bruce Wilks 5 , Mike Ma 3 , C. Lin 3 , Sanjay Banerjee 2
1 External Research, SiTD, Texas Instruments Inc., Austin, Texas, United States, 2 Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas, United States, 3 , United Microelectronics Corporation Inc., Hsinchu Taiwan, 4 , MEMC Electronic Materials Inc., St. Peters, Missouri, United States, 5 , Advanced Technology Development Facility Inc., Austin, Texas, United States
Show AbstractThe use of hybrid orientation technology (HOT) with direct silicon bond (DSB) wafers consisting of a (110) Si layer bonded to a bulk Si (100) wafer provides opportunities for migration of bulk CMOS designs to higher performance materials: namely (110) Si for PMOSFETs for higher hole mobility. This has been demonstrated using Silicon-on-Insulator (SOI) substrates with either one or both types of devices on an insulating layer. However, this requires complex selective epitaxial growth. Also, in order to easily reuse bulk CMOS libraries, a “bulk-like” technology is interesting. A 2X performance improvement in the Ion-Ioff behavior for short channel (85 nm) PMOS devices fabricated using a standard polysilicon / nitrided silicon dioxide process was observed on DSB wafers. Performance of NMOS devices fabricated on recrystallized (100) active areas of the wafer was comparable to bulk (100) Si. This report discusses layer thickness optimization necessary to minimize off-state leakage for DSB-HOT.Ultra-thin (110) layers would be ideal for the scheme of amorphization and templated recrystallization (ATR) before shallow trench isolation (STI) proposed by Saenger et al. in order to minimize the triangular morphology observed at the border of the epitaxially regrown region. The morphology results due to competing solid phase (SPE) epitaxial regrowth processes from the bottom (100) and sidewall surface of the (110) layer. The presence of this region near the junction of a device would increase off-state NMOS leakage. It is necessary to minimize this morphology near the device and consume the triangular region by STI in order for the technology to be applicable to SRAM cells at the 45/32 nm nodes. However, there are interesting tradeoffs associated with very thin Si (110) layers. Significant dopant segregation is observed from SIMS profiles after device fabrication at the bond interface between the (110) Si layer and the (100) substrate. This leads to a large source-to-drain leakage for short channel devices with very thin DSB layers. Long channel MOSFETs as well as short channel MOSFETs fabricated on thicker DSB layers show a much lower off-state leakage. IV data indicates that DSB layer thicknesses of 200 nm and higher demonstrate a significant reduction in S-D leakage while thicknesses lower than 100 nm result in electrical shorts between the S/D regions for short channel devices. The corresponding triangular epitaxial regrowth morphology for a 100 nm thick DSB layer was observed to be as large as 110 nm. This presents a significant roadblock for this technology in SRAM cells at the 45/32 nm nodes. Process techniques to reduce the morphology for NMOS devices as well as junction engineering to minimize leakage at the bond interface have been investigated. One order of magnitude improvement in the PMOS DSB junction leakage was demonstrated by optimizing the implant conditions which could enable thinner DSB layers.
3:15 PM - G3.3
Understanding Facet Formation During Solid Phase Epitaxy of Patterned Amorphized Regions in (001) and (011) Silicon: Observations and Model.
Katherine Saenger 1 , Haizhou Yin 2 , Keith Fogel 1 , John Ott 1 , Joel de Souza 1 , Devendra Sadana 1
1 IBM Semiconductor Research and Development Center, IBM T.J. Watson Research Center, Yorktown Heights, New York, United States, 2 IBM Semiconductor Research and Development Center, IBM Microelectronics, Hopewell Junction, New York, United States
Show Abstract3:30 PM - G3.4
Sub 50nm Strained n-FETs formed on Silicon-Germanium-on-Insulator Substrates and the Integration of Silicon Source/Drain Stressors
Huiqi Grace Wang 1 2 , Eng-Huat Toh 1 2 , Keat Mun Hoe 2 , S. Tripathy 3 , Subramanian Balakumar 2 , Guo-Qiang Lo 2 , Ganesh Samudra 1 , Yee-Chia Yeo 1
1 , National University of Singapore, Singapore Singapore, 2 , Institutue of Microelectronics, Singapore Singapore, 3 , Institutue of Materials Research and Engineering, Singapore Singapore
Show AbstractGroup-IV high-mobility semiconductors such as Ge [1] and SiGe [2] have received considerable attention as potential materials for further extension of transistor performance. Exploitation of strained-Ge and SiGe channels would lead to further reduction in carrier effective mass and improve mobility enhancement, paving the way for high mobility transistors with superior speed performance. Existing works on SiGe channel show marginal enhancement in NMOS [3], possibly due to the compressive stress in thin SiGe channel structures. By adopting silicon-germanium-on-insulator (SGOI) substrates fabricated by a novel Ge condensation technique [4], the lateral compressive strain normally present in SGOI substrates can be reduced, enabling n-FET fabrication with excellent performance. We found that the magnitude of the compressive strain can be relaxed by up to 0.7%, according to Raman spectroscopy measurements. In this work, we also report the experimental demonstration of uniaxial tensile strained thin-body silicon-germanium-on-insulator (SGOI) n-FETs with silicon (Si) source and drain (S/D) regions. The selectively grown Si S/D induces uniaxial tensile strain in the SiGe channel, leading to enhancement in electron mobility. The stress distribution in n-FETs formed with Si S/D and Si0.75Ge0.25 or Si0.60Ge0.40 channel region was investigated using numerical simulation. The simulated stress profile shows lateral compression of the SiGe lattice underneath the Si S/D stressors, and lateral tensile stress Sxx induced in the SiGe channel. The tensile stress generated near the channel center increases from 1.2GPa to 1.7GPa, as the Ge content in the channel increased from Si0.75Ge0.25 to Si0.60Ge0.40. Tensile stress developed in the SiGe channel is the key for electron mobility enhancement. Devices with gate length LG down to 50 nm were fabricated. The Si S/D gives rise to 39% higher saturation drive current IDsat for transistors fabricated on Si0.60Ge0.40-on-insulator substrates. For n-FETs fabricated on Si0.75Ge0.25-on-insulator substrates, a 27% IDsat enhancement was observed. Dependence of the transistor performance on channel orientation and device dimensions, e.g. gate length and width, are explored. Appreciable IDsat enhancement was observed. Transistors employing group-IV high mobility channel materials could be promising for realizing very high performance levels.REFERENCES[1]H. Shang et. al., IEDM Tech. Dig., pp. 157, 2004[2]H. C.-H. Wang et al, IEDM Tech. Dig., pp. 161,2004.[3]T. Irisawa et. al., Appl. Phys. Lett. 81, pp.847,2002.[4]G. H. Wang et. al. Appl. Phys. Lett., 89, no.5, pp.3109, 2006.
3:45 PM - G3.5
Characterization of a Multidirectional Condensation Ge Process for Co-integrated SOI/GeOI Substrate Fabrication.
Benjamin Vincent 1 , Jean-Francois Damlencourt 1 , Denis Rouchon 1 , Pierrette Rivallin 1 , Laurent Clavelier 1
1 , CEA-DRT-LETI-CEA/GRE, Grenoble France
Show Abstract4:00 PM - G3: AdvChanMats
BREAK
G4: Advanced Channel Materials II
Session Chairs
Reza Arghavani
Gerhard Klimeck
Tuesday PM, April 10, 2007
Room 3005 (Moscone West)
4:30 PM - **G4.1
Strained Si-Ge Heterostructure Channel Materials for Bulk and Ultra-thin Body MOSFETs.
Judy Hoyt 1 , Cait Chleirigh 1 , Leonardo Gomez 1 , Ingvar Aberg 1 , Guangrui Xia 1
1 Microsystems Technology Laboratories, MIT, Cambridge, Massachusetts, United States
Show AbstractThe materials and device technology of MOSFETs utilizing Si-Ge heterostructure channels are reviewed. Strained Si-strained Ge heterostructures offer the potential for both electron and hole mobility enhancement using Si-compatible gate dielectrics. In strained (100) Ge in particular, the measured hole mobility enhancement is 10x higher than in unstrained Si p-MOSFETs. Strain relaxation limits the SiGe layer thickness to less than 10 nm for high-Ge-content strained SiGe grown on Si, while hole mobility drops for SiGe layer thicknesses in this regime, due to confinement effects. These considerations suggest a design space for the layer composition, thicknesses and strain, which impacts the hole mobility as well as off-state leakage and thermal budget constraints. The combination of these enhanced mobility materials with alternate device architectures, including ultra-thin body and double-gate devices, is of interest for device scaling as a means of improving electrostatics, and progress in heterostructure on insulator materials will be discussed.
5:00 PM - **G4.2
High-κ Material Selection for Realization of High Effective Hole Mobility Ge p-MOSFETs.
Yohiski Kamata 1 , Tsunehiro Ino 1 , Masato Koyama 1 , Akira Nishiyama 1
1 , TOSHIBA CORPORATION, Yokohama Japan
Show AbstractHigh-κ/Ge gate stacks have recently attracted much attention due to their potential for offering high channel mobility and small EOT simultaneously. In particular, p-channel Ge FET is promising since bulk hole mobility of Ge is four times as high as that of Si and it can be further enhanced by strain. High-κ materials studied in Si technology, such as ZrO2 and HfO2, have been widely investigated on Ge substrate. However, it was revealed that Ge diffusion into the high-κ dielectrics during the annealing process, which was widely observed in the case of ZrO2 and HfO2, leads to the degradation of Ge MOSFET characteristics. In order to avoid this Ge diffusion, a thermally stable surface passivation layer is required. Surface passivation techniques using NH3, SiH4 and PH3 before high-k deposition have already been reported, and some of these studies succeeded in suppressing the Ge diffusion, resulting in good device characteristics. We review our different approach for high-κ/Ge p-MOSFETs without an intentional interfacial layer. Using amorphous Zr silicate directly on Ge substrate, Ge diffusion and large CV hysteresis are suppressed and higher effective hole mobility than Si universal curve is accomplished.
5:30 PM - G4.3
Interfacial Composition and Electrical Properties of Hf Oxide Dielectric Films Grown on InxGa1-xAs.
Lyudmila Goncharova 1 , Ozgur Celik 1 , Eric Garfunkel 1 , Torgny Gustafsson 1 , Niti Goel 2 , Safak Sayan 2 , Wilman Tsai 2
1 Physics, and Chemistry and Chemical Biology, Rutgers University, Piscataway, New Jersey, United States, 2 , Intel Corp., Santa Clara, California, United States
Show Abstract5:45 PM - G4.4
Enhancement-Mode (with Channel Inversion) and Depletion-Mode MOSFETs with Ga2O3(Gd2O3)/Si3N4 Dual-Layer Gate Dielectrics on In0.2Ga0.8As
Jun-Fei Zheng 1 , Wilman Tsai 1 , Tsung-Da Lin 2 , Chih-Ping Chen 2 , Minghwei Hong 2 , Raynien Kwo 3 , Sharon Cui 4 , Tso-Ping Ma 4
1 Strategic Technology/External Program, Intel Corporation, Santa Clara, California, United States, 2 Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan, 3 Department of Physics, National Tsing Hua University, Hsinchu Taiwan, 4 Department of Electrical Engineering, Yale University, New Haven, Connecticut, United States
Show AbstractIn this paper, we report a Ga2O3(Gd2O3)/Si3N4 dual-layer gate dielectric approach for enhancement-mode (with channel inversion) and depletion-mode MOSFETs on In0.2Ga0.8As. The dual-layer dielectric is formed by first depositing an nm-thick Ga2O3(Gd2O3) layer in-situ on In0.2Ga0.8As/GaAs. This unpins the In0.2Ga0.8As surface Fermi-level. Then an nm-thick Jet-Vapor-Deposited (JVD) Si3N4 is ex-situ deposited on Ga2O3(Gd2O3), which not only serves to protect Ga2O3(Gd2O3) from moisture during air-exposure and device processing, but also significantly reduces the gate leakage current. We fabricated and characterized n-channel enhancement-mode MOSFETs (with surface channel inversion) and n-channel depletion-mode MOSFETs on In0.2Ga0.8As, with a total dual-layer gate dielectric effective oxide thickness (EOT) of ~5 nm. Enhancement- mode MOSFET with a ring gate of L=10 μm shows excellent electrical characteristics with Id of ~ 0.22 mA/mm at Vds=1V and Vg=4.5V. Depletion-mode MOSFET with a ring gate of L=10 μm and large S/D to gate separation of 12.5 μm exhibits Id of 19.3mA/mm at Vds=4V and Vg=4V. We will discuss the process integration as well as process related device optimization.
G5: Poster Session
Session Chairs
Reza Arghavani
Srini Chakravarthi
Gerhard Klimeck
Wednesday AM, April 11, 2007
Salon Level (Marriott)
9:00 PM - G5.1
Growth and Material Characteristics of Ga2O3(Gd2O3)/Si3N4 Dual-Layer Gate Dielectric for Inversion-Channel and Depletion Mode GaAs-based MOSFET.
T. Lin 1 , C. Chen 1 , M. Hong 1 , J. Kwo 2 , J. Zheng 3 , W. Tsai 3 , S. Cui 4 , T. Ma 4
1 Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan, 2 Department of Physics, National Tsing Hua University, Hsinchu Taiwan, 3 , Intel Corporation, Santa Clara, California, United States, 4 Department of Electrical Engineering, Yale University, New Haven, Connecticut, United States
Show AbstractAlternative channel materials are urgently required to drive the transistor scaling beyond 22nm node. III-V compound semiconductors, which possess much higher mobilities than that of Si, are candidates for the new channels. The interface pinning and/or gate insulator leakage, which has hindered the development of the III-V MOSFETs over the past four decades, have now been solved with the first demonstration of the GaAs surface unpinning using Ga2O3(Gd2O3) in-situ deposited on GaAs [1]. The discovery has led to the first inversion-channel GaAs MOSFETs in both n- and p-configurations [2]. Nonetheless, the strong affinity of the oxide to moisture [3] has posted difficulty in device processing. In this paper, growth and materials characterization of a dual gate dielectric approach using a nano thick Ga2O3(Gd2O3) as the initial dielectric layer in-situ deposited on In0.2Ga0.8As/GaAs and then a Jet Vapor Deposit Si3N4 as the second dielectric layer ex-situ deposited on Ga2O3(Gd2O3) is reported. The initial Ga2O3(Gd2O3) plays an important role in unpinning GaAs. The thermodynamic stability of Ga2O3(Gd2O3)/GaAs up to 780°C [4] allows the subsequent deposition of Si3N4, which serves as a protective layer for Ga2O3(Gd2O3) during air-exposure and device processing. Device structures of Ga2O3(Gd2O3)/In0.2Ga0.8As/GaAs were grown in a multi-functional and multi-chamber UHV system, including GaAs-based and oxide molecular beam epitaxy (MBE) chambers [1].Depletion-mode In0.2Ga0.8As-channel MOSFETs with the dual gate dielectric were fabricated and characterized. Transistors with a 10 μm ring gate exhibit a large drain current density of 19.3 mA/mm at VG of 4V with a large distance of S/D to gate (=12.5 μm). Inversion-channel devices also showed excellent electrical characteristics. The growth of semiconductor channels, in-situ deposited Ga2O3(Gd2O3) and ex-situ deposited Si3N4 will be discussed. The material characteristics using x-ray reflectivity, high-resolution transmission electron microscopy, and medium energy ion scattering will be presented. [1] M. Hong, et al, J. Vac. Sci. Technol. B, 14, 2297, 1996.[2] F. Ren, et al, Solid-State Electron. 41, 1751, 1997.[3] M. Hong, et al, Appl. Phys. Lett. 76, 312, 2000.[4] Y. L. Huang, et al, Appl. Phys. Lett. 86, 191905, 2005.
9:00 PM - G5.10
Strained Si/Si1-xGex/Relaxed Si1-yGey (x>y) Structures: Identifying Roughness Due to Compressed SiGe and Its Impact on High Mobility MOSFETs.
Enrique Escobedo-Cousin 1 , Sarah Olsen 1 , Anthony O'Neill 1 , Olayiwola Alatise 1 , Rouzet Agaiby 1 , Peter Dobrosz 1 , Glyn Braithwaite 2 , Alan Cuthbertson 2 , Tim Grasby 3 , Evan Parker 3
1 , Newcastle University, Newcastle upon Tyne United Kingdom, 2 , Atmel North Tyneside, Newcastle upon Tyne United Kingdom, 3 , University of Warwick, Coventry United Kingdom
Show AbstractFull exploitation of dual channel virtual substrate (VS) MOSFETs requires progress in several technological areas. Ge out-diffusion from the buried strained SiGe layer induces both mobility loss and degraded gate oxide quality. This can be partially alleviated by using a tensile strained Si layer below the strained SiGe since Ge diffusion is retarded in tensile strained Si. A further issue is small-scale roughness due to compressed SiGe. We have recently shown that this roughness severely impacts gate leakage, gate oxide interface trap density and carrier mobility. Surface nMOSFETs are also affected because undulations originating below the surface are transferred to the overlying strained Si electron channel. Until now the effect of the undulations has primarily been evaluated through electrical characterisation. Physical analysis of these undulations is challenging since roughness wavelengths and amplitudes are smaller than those due to VS relaxation. Consequently critical small-scale roughness is often unidentified. In this work we present an efficient and non-destructive technique to extract meaningful roughness data in single channel, dual channel and ‘trilayer’ structures (comprising an additional buried strained Si layer) from AFM measurements using detailed spectral frequency analysis. The extracted roughness parameters correlate well with electrical data from n- and p-MOSFETs in which variations in mobility enhancement, drive current and gate oxide quality result from strain-induced undulations in the buried SiGe. By acquiring very small scale AFM data (1 um2) and implementing wavelength filtering, roughness analysis at lateral scales down to ~20 nm is possible. For the first time AFM is used to show that incorporating a compressively strained SiGe layer below the tensile strained Si surface layer induces roughness with correlation lengths and amplitudes relating to carrier mobility. By studying a matrix of structures we show that roughness in dual and trilayer structures is dominated by compressive strain in the SiGe as opposed to the actual Ge content in either the VS or the compressed SiGe. For structures having identical surface Si strain (0.6%), the rms roughness of wavelength components < 750 nm increases from 0.2 to 2.7 nm for an increase of 0.4% strain in the buried SiGe layer (35% Ge compared with 25% Ge, on a 15% Ge VS). There is a corresponding change of 20% in electron mobility at high fields, where surface roughness scattering dominates. Single channel structures with equivalent strain yield filtered rms roughness < 0.04 nm. The filtered roughness correlation lengths and amplitudes are also found to be highly dependent on compressive strain; in strained Si0.65Ge0.35 the correlation length and amplitude are 200 nm and 12 nm, respectively. Roughness data are confirmed by TEM. Multiple batch runs demonstrate that the results are repeatable and should be considered in the design of high-speed CMOS architectures using SiGe.
9:00 PM - G5.11
Embedded SiGe Source/Drains and Buried SiGe channels: A Successful Combination to Increase Drive Current and to Adjust Threshold Voltage in High k pMOS Devices.
Roger Loo 1 , Haruyuki Sorada 2 , Akira Inoue 2 , Masaaki Niwa 2 , Aude Rothschild 1 , Peter Verheyen 1 , Matty Caymax 1
1 , IMEC, Leuven Belgium, 2 assigned to IMEC, Matsushita Electric Industrial Co., Osaka Japan
Show Abstract9:00 PM - G5.12
Electrical and Physical Characterization of ALD-grown HfO2 Gate Dielectrics on GaAs (100) Substates with Sulfur Passivation.
Eunji Kim 1 , Joseph Chen 1 , Donghun Choi 2 , Niti Goel 3 , Chi On Chui 3 , Wilman Tsai 3 , James Harris 2 , Yoshio Nishi 2 , Krishna Saraswat 2 , Paul McIntyre 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Electrical Engineering, Stanford University, Stanford, California, United States, 3 , Intel Corporation, Santa Clara, California, United States
Show AbstractIIIV semiconductor-based field effect transistors are receiving increased attention among research groups due to their potential for very high electron mobility and low power dissipation. However, achieving IIIV-based metal-oxide-semiconductor devices remains very challenging in part because deposition of high-quality gate dielectrics on the channel may produce subcutaneous oxidation of the IIIV material, leading to a high density of interface defects which are difficult to passivate. We have investigated the electrical and physical properties of W/HfO2/p GaAs MOS capacitors with and without sulfur passivation prior to HfO2 deposition. ALD-grown HfO2 on non-treated epitaxial GaAs shows very promising CV characteristics, including an apparent dielectric constant of 15 (which includes the effects of an interface layer) and low leakage current density. After performing a rapid thermal anneal at 450 degrees for 2mins in N2 ambient, the HfO2 film showed improved film properties, such as reduction in CV hysteresis, recovery of a near-ideal flat band voltage and an increase in gate capacitance density. ALD-HfO2 deposited on S-passivated GaAs showed a decrease in CV hysteresis relative to non-treated GaAs, without sacrificing capacitance. Physical properties of the film such as surface roughness, film thickness, and density were also studied by AFM, XRR, and XPS. The mechanisms for improvements in MOS electrical properties as a result of pre-deposition and S treatment and post-deposition anneals will be discussed.
9:00 PM - G5.15
Ni-germanide Contacts on Ge: Phase Formation and Electrical Characterization.
Karl Opsomer 1 2 , Eddy Simoen 1 , Christophe Detavernier 3 , Anne Lauwers 1 , Christian Lavoie 4 , Roland Vanmeirhaeghe 3 , Karen Maex 1 2
1 , IMEC, Leuven Belgium, 2 Electrical Engineering Department (ESAT), Katholieke Universiteit Leuven, Leuven Belgium, 3 Solid-State Sciences Department, Universiteit Gent, Gent Belgium, 4 , IBM T.J. Watson Research Center, Yorktown Heights, New York, United States
Show AbstractThe interest in using germanium (Ge) as an alternative substrate for ultimate CMOS transistors has been a strong motivation for the recent research activities on germanide formation.[1-3] In particular, Ni germanides are likely put forward as candidates to contact the Ge devices at source, drain and gate, similarly as is done with silicides on Si based devices. In addition, although a considerable understanding on solid-state phase formation and phase stability is relatively well established, still some aspects are less well understood, such as the initial phase formation (selection of the first phase), the influence of texture in the growing film, the evolution of stress during film growth. Therefore studying metal-Ge reactions might contribute to the further understanding of compound formation.In a first part, we present the results on the solid-state reactions between Ni and Ge substrates, studied by a variety of complementary in-situ and ex-situ characterization techniques. In-situ techniques as XRD, sheet resistance, substrate curvature and diffuse light scattering are carried out during the reaction of Ni layers with different thickness, on different Ge-substrates: Ni layers of 10, 30, 90, and 500 nm and Ge substrates of different crystallinity (Ge(100), Ge(111), p-Ge and a-Ge) are investigated. The combination of complementary techniques in our results, show some subtle aspects when compared to ex-situ alternatives. Our results are reflected on the current understanding of both Ni germanide phase formation and stress evolution during solid-state reactions. The relation between initial phase formation and stress development in particular will be addressed.In a second part, and in relation with our findings based on pure materials studies aspects, our results on the use of Ni germanides on devices are discussed for selected stages in the reaction. DLTS and current-voltage (I-V) characteristics of Ni-germanide/n-Ge contacts are studied.[3] Our results reveal that a particular behavior is present, dependent on the measurement temperature (78K – 298K). These results are discussed in the scope of the known I-V-characteristics.[1] S. Gaudet, C. Detavernier, A. J. Kellock, P. Desjardins, and C. Lavoie, J. Vac. Sc. Technol. A 24 (3), 474 (2006).[2] F. Nemouchi, D. Mangelinck, C. Bergman, G. Clugnet, P. Gas, and J. L. Labar, Appl. Phys. Lett. 89 (13), 131920 (2006).[3] E. Simoen, K. Opsomer, C. Detavernier, R.L. Van Meirhaeghe, K. Maex, and P. Clauws, Appl. Phys. Lett. 88 (18), 183506 (2006)
9:00 PM - G5.16
Gate-all-around (GAA) Fully Depleted (FD) Cantilever Channel MOSFET with high-κ Dielectric and Metal Gate.
Sagnik Dey 1 , Sachin Joshi 2 , Se-Hoon Lee 3 , Prashant Majhi 4 , Sanjay Banerjee 5
1 Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, United States, 2 Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, United States, 3 Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, United States, 4 Intel Assignee, Sematech, Austin, Texas, United States, 5 Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, United States
Show Abstract9:00 PM - G5.17
Sub-30 nm FinFETs with Schottky-Barrier Source/Drain Featuring Complementary Metal Silicides and Fully-Silicided Gate for P-FinFETs
Rinus Lee 1 , Kian Ming Tan 1 , Tsung-Yang Liow 1 , Andy Lim 1 , Guo-Qiang Lo 2 , Ganesh Samudra 1 , Dong-Zhi Chi 3 , Yee-Chia Yeo 1
1 Silicon Nano Device Lab, Electrical and Computer Engineering, National University of Singapore, Singapore Singapore, 2 Institute of Microelectronics , Agency of Science Technology and Research , Singapore Singapore, 3 Institute of Materials Research and Engineering, Agency of Science Technology and Research , Singapore Singapore
Show AbstractDimensional scaling has been the main driver for complementary metal-oxide-semiconductor (CMOS) technology and has provided significant improvements in integrated circuit density and device performance. However, continual dimensional scaling into the nanoscale regime has led to immense technological challenges; therefore non-classical transistor structures, e.g. double-gate or triple-gate transistors, are needed to further extend the limits of device performance. In addition, various ‘technology boosters’ such as metal gate electrodes and metallic source/drain regions (e.g. metal silicides) could be implemented in these device structures. In this paper, fin field-effect transistors (FinFETs) with gate-lengths down to 25 nm integrated with Schottky-barrier source/drain were fabricated. Complementary low barrier self-aligned ytterbium and platinum silicides were used to reduce the contact and series resistances. Due to the low electronegativity parameter of ytterbium, a low temperature silicidation process was developed to avoid the reaction of ytterbium with the isolation regions (i.e. SiO2 and SiN). The fabricated minimum gate-length transistors with gate oxide thickness of 30 Å exhibits N-FinFET |IDSAT|= 241 μA/μm and P-FinFET |IDSAT| = 211 μA/μm at VDS = |VGS – VT| = 1V and Ion/Ioff > 104. The integration of fully-silicided (FUSI) metal gate into P-FinFETs was also explored in this work. A novel silicidation process that integrates simultaneously two different phases of platinum silicide with the appropriate work function values for gate electrode and source/drain application was demonstrated. Compared to poly-Si gate P-FinFETs, platinum-rich FUSI gate P-FinFETs exhibit significantly higher IDSAT due to the elimination of poly-Si gate depletion effects.
9:00 PM - G5.2
Formation and Characterization of Pt-Germanide Thin Films on Ge(001) for Schottky Source/Drain Application in Ge pMOSFETs
Haibiao Yao 1 , Dongzhi Chi 1 , Rui Li 2 1 , Sungjoo Lee 2
1 , Institute of materials research & engineering, Singapore Singapore, 2 SNDL, Dept. of ECE, National University of Singapore, Singapore Singapore
Show AbstractThe lack of a stable native germanium oxide has been the main obstacle for the use of Ge in complementary metal oxide-semiconductor devices. However, recent development of next generation deposited high-k gate dielectrics for Si also allows for the fabrication of high performance Ge-based metal-oxide-semiconductor field effect transistors (MOSFETs). For the formation of electrical contacts on Ge-based MOSFETs, transition metal germanides, such as Ni and Pt germanides, appear to be suitable candidates due to their low resistivity, low formation temperatures (as low as 250 °C), and ability to form in self-aligning manner. In this work, we have characterized the material and electrical properties of platinum germanide films which were formed on Ge(001) through solid-state reaction between Pt and Ge(001) via rapid thermal annealing. Formation of sequential phases of PtGe, Pt2Ge3, and PtGe2 with increasing annealing temperature was confirmed by X-ray diffraction measurement: PtGe at 300 oC, Pt2Ge3 at 400 oC and PtGe2 at 500 oC. A minimum resistivity value of ~36 ohm.cm was obtained for PtGe2, while the corresponding values for PtGe and Pt2Ge3 were found to be 52 and 71 ohm.cm, respectively. Scanning electron microscopy revealed that Pt-germanide films exhibit better morphological stability than NiGe, particularly for ultra-thin films. Almost identical effective barrier heights of ~ 0.619-0.626 eV were obtained for PtGe/n-Ge(001), Pt2Ge3/n-Ge(001), and PtGe2/n-Ge(001) Schottky contacts from current-voltage measurements. From the effective barrier height values, actual barrier heights of ~0.653 – 0.663 eV were determined by taking into account image force induced barrier lowering in the presence of strong inversion layers at the interfaces. The actual barrier height values obtained were further validated by the good agreement between experimental and simulation results for capacitance – voltage characterization. The observation of barrier heights of ~0.653 – 0.663 eV on n-Ge(001) means that Pt-germanides have near zero barrier for hole injection into inverted p-channel, thus ideal for the application as Schottky S/D in Ge pMOSFETs.
9:00 PM - G5.21
Fermi Level Position at YbGe/Ge(001) Interface and Schottky Barrier Height Determined by X-ray Photoelectron Spectroscopy
Cheng-Cheh Tan 1 , Haibiao Yao 1 , Jian Wei Chai 1 , Jisheng Pan 1 , Dongzhi Chi 1
1 , Institute of Materials Research & Engineering, Singapore Singapore
Show AbstractRare-earth metal silicides, for example ErSi2 and YbSi2, have been shown to have low contact resistance for n-Si due to its low schottky barrier. It was therefore perceived that rare-earth germanides would also be good candidates as contact materials for Ge nMOSFETs. However, recent studies have shown that it is not the case. For example, though having its Fermi level almost perfectly aligned with the conduction band edge Ec of Ge[1], a relatively high Schottky barrier height has been observed for Er-germanide fromed on n-Ge(001). Expecting a similar behavior with Yb-germanide, in this work, we performed XPS characterization of Yb-germanide formed on Ge(001) in order to extract its Schottky barrier height. For the XPS measurement, we first collected the valence band spectra of pure Ge. Next, using an e-beam evaporator and a heating chuck mounted to the UHV preparation chamber of the XPS, we measured the XPS spectra of YbGe/Ge(001), which was formed by evaporating a thin layer (~6nm) of Yb on Ge(001) followed by annealing at 350°C for 60s. Using Ge3d core-level as reference to correct charge effects, we determined the Fermi-level Ef of YbGe relative to the valence band edge Ev of Ge at YbGe/Ge interface. The XPS result shows that Fermi-level of YbGe is virtually pinned to Ev with Ef - Ev ~ -0.10 eV, which appears to be in agreement with the result of I-V characterization of YbGe/n-Ge(001) diode where an effective barrier height of ~ 0.62 eV was obtained. This surprising finding suggests that, though it is not a suitable contact material for Ge nMOSFETs, YbGe appears to be a good candidate for the use as contact material in Ge pMOSFETs, due to its near zero (or even negative) barrier height to inverted p-channel and also considering its low resistivity which is comparable to that of NiGe.[1] Yoshinori Tsuchiya, Masato Koyama, Junji Koga, and Akira Nishiyama, Extended Abstracts of 2005 International Conference on Solid State Devices and Materials (SSDM), pp.844-845, Sep. 2005, Kobe, Japan
9:00 PM - G5.22
Implications to Work Function Modulation from Metal-Oxide Interface Configurations: Case of Study HfO2 and SiO2.
Blanka Magyari-Kope 1 , Yoshio Nishi 1 , Luigi Colombo 2 , Kyeongjae Cho 3
1 Electrical Engineering, Stanford University, Stanford, California, United States, 2 , Texas Instruments Inc., Dallas, Texas, United States, 3 Physics and Electrical Engineering, University of Texas, Dallas, Texas, United States
Show Abstract9:00 PM - G5.3
Impact of Interfacial Layer Control in high-K Gate Dielectrics on GaAs for Advanced CMOS Devices.
Goutam Dalapati 1 , Yi Tong 1 , Wei Yip Loh 2 , Byung Jin Cho 1
1 Dept. of Electrical & Computer Engineering,, National University of Singapore, Singapore Singapore, 2 , Institute of Microelectronics,, Singapore Singapore
Show Abstract9:00 PM - G5.4
Current-Voltage Measurements and Photoconductance Spectroscopy of Ultrathin InAs Grown on (211) Si.
Bin Wu 1 , Dane Wheeler 1 , Qin Zhang 1 , Patrick Fay 1 , Alan Seabaugh 1 , Changhyun Yi 2 , Inho Yoon 2 , April Brown 2 , T. Kuech 3
1 Electrical Engineering, University of Notre Dame, Notre Dame, Indiana, United States, 2 Electrical and Computer Engineering, Duke University, Durham, North Carolina, United States, 3 Chemical and Biological Engineering, University of Wisconsin-Madison, Madison, Wisconsin, United States
Show AbstractAn approach for forming InAs-channel MOSFETs is being explored in which sub-10-nm thick InAs is grown directly on submicron (211) silicon-on-insulator (SOI) islands. These thin channels are capped with a high-k dielectric consisting of aluminum or hafnium oxide. The (211) orientation is selected to provide a charge neutral growth plane and circumvent the formation of antiphase domains. Since the growth is highly mismatched (11.6 %), submicron device mesas or islands are formed to provide edges to terminate dislocations. The growth is by molecular beam epitaxy (MBE) using growth temperatures under 300 C to suppress islanding. Post-growth annealing is being explored to improve the crystallinity. Gated van der Pauw and FET structures have been designed to explore transport in InAs on Si channels. Current-voltage measurements of Au/Ti/10 nm InAs/p-Si heterostructures show diode characteristics, consistent with the formation of n-InAs/p-Si junctions. Scanning electron microscopy of these first films reveal the formation of islands with an island size ranging from 5 to 25 nm in extent. Current-voltage measurements in the plane of the film show hysteresis and sweep time dependence not present in the vertical transport measurements. Photoconductance spectroscopy measurements at fixed bias and over the spectral range from approximately 1 to 5 microns (1.2 – 0.25 eV) are being used to unravel the transport in these films.
9:00 PM - G5.6
High-performance Inversion-mode InGaAs/InP MOSFETs Using ALD Al2O3 as Gate Dielectrics.
Yi Xuan 1 , Han-Chung Lin 1 , Peide (Peter) Ye 1
1 School of ECE, Purdue University, West Lafayette, Indiana, United States
Show Abstract9:00 PM - G5.7
Material and Electrical Characterization of Nickel Silicide-Carbon as Contact Metal to Silicon-Carbon Source and Drain Stressors
Rinus Lee 1 , Litao Yang 1 , Kah-Wee Ang 1 , Tsung-Yang Liow 1 , Kian-Ming Tan 1 , Andrew Wong 2 , Ganesh Samudra 1 , Dong-Zhi Chi 2 , Yee-Chia Yeo 1
1 Silicon Nano Device Lab, Electrical and Computer Engineering, National University of Singapore, Singapore Singapore, 2 Institute of Materials Research and Engineering, Agency of Science Technology and Research , Singapore Singapore
Show AbstractLattice-mismatched source and drain (S/D) stressors is being actively pursued to enhance carrier mobility and drive current performance of nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). For p-channel MOSFETs, the use of silicon-germanium (SiGe) S/D stressor introduces uniaxial compressive strain in the channel and improves the drive current significantly. Conversely, silicon-carbon (SiC) S/D stressor introduces uniaxial tensile strain in the channel beneficial for n-channel MOSFET drive current enhancement. In order to reap the full benefits of channel strain engineering, it will be imperative to integrate the new materials (i.e. SiGe and SiC) with low resistance silicide technology. Nickel-germanosilicide (NiSiGe) is compatible with SiGe technology and adopted as the contact metal for strained p-channel MOSFETs in high-volume manufacturing. However, literature on the material and electrical characteristics of nickel silicide-carbon (NiSi:C) as contact metal to SiC is currently lacking. In this paper, we present phase analysis of NiSi:C films and electrical characterization of NiSi:C contacts to n+/p SiC junctions formed by selective epitaxy of SiC and ex-situ ion implantation. NiSi:C films investigated in this work were formed by rapid thermal annealing in nitrogen ambient for 60 seconds. The incorporation of carbon shows an increase in sheet resistivity for NiSi:C compared to NiSi films for the temperature range of 200 – 600 oC. However, sheet resistivity is degraded at elevated temperatures (> 650 oC) for NiSi films but suppressed effectively for NiSi:C films. We speculate that carbon segregates into the grain boundaries of NiSi and stabilizes the film morphology/phase. The stabilized NiSi:C film increases the maximum processing temperature available for NiSi by ~ 150 oC. X-ray diffraction analysis further revealed that NiSi:C films are textured with a preferred orientation. Current-voltage measurements of NiSi and NiSi:C n+/p junctions show similar cumulative distribution for the junction leakage, which implies the incorporation of carbon has a negligible impact on the junction integrity of a MOSFET. Our results suggest that NiSi:C is a suitable self-aligned contact metal to n-channel MOSFETs with SiC S/D stressors in a similar manner to the way in which NiSiGe is used for p-channel MOSFETs with SiGe S/D stressors.
9:00 PM - G5.8
A Combinatorial Materials Science Approach to the Ge/HfO2/metal Gate Stack.
Nabil Bassim 1 , Kao-Shuo Chang 1 , Sandrine Rivillon 2 , Min Dai 2 , Peter Schenck 1 , Martin Green 1 , Yves Chabal 2
1 , National Institute of Standards & Technology, Gaithersburg, Maryland, United States, 2 , Rutgers University, Piscataway, New Jersey, United States
Show Abstract9:00 PM - G5.9
Nanoanalytical Electron Microscope Investigations of Etching Processes for III-V MOSFET Devices.
Paolo Longo 1 , Jamie Scott 1 , Alan Craven 1 , Richard Hill 2 , Iain Thayne 2
1 Department of Physics and Astronomy, University of Glasgow, Glasgow United Kingdom, 2 Department of Electronics & Electrical Engineering, University of Glasgow, Glasgow United Kingdom
Show Abstract