Symposium Organizers
Paul C. McIntyre Stanford University
Joan M. Redwing The Pennsylvania State University
Volker Schmidt Max-Planck-Institut für Mikrostrukturphysik
Silvija Gradecak Massachusetts Institute of Technology
Symposium Support
AIXTRON AG
JEOL USA Inc
Park AFM
First Nano, a division of CVD Equipment Corp
AA1: III-V Nanowire Devices
Session Chairs
Erik Bakkers
Paul McIntyre
Tuesday PM, April 14, 2009
Room 3008 (Moscone West)
9:30 AM - **AA1.2
Position Controlled Growth of III-V Semiconductor Core-shell Nanowires Grown by Selective Area MOVPE and Their Device Applications.
Takashi Fukui 1 , Katsuhiro Tomioka 1 , Shinjiro Hara 1 , Kenji Hiruma 1 , Junichi Motohisa 1
1 Research Center for Integrated Quantum Electronics, Hokkaido University, Sapporo, Hokkaido, Japan
Show AbstractSemiconductor nanowires have stimulated extensive interest in recent years because of their unique properties and potential applications as building blocks for nanoscale electronic and photonic devices. Realization of high quality, highly uniform, single-crystalline, reproducibly identical nanowires is a challenging task and one of the key hurdles for future development of nanotechnology. The significance of such controlled growth of nanowires would increase multifold if they were realized using a catalyst-free growth technique.We report on the systematically controlled growth of GaAs and InP and related III-V compound semiconductor nanowire arrays by catalyst-free selective area metalorganic vapor phase epitaxy on partially masked (111) oriented substrates. First we discuss about nanowire growth mechanism for GaAs. GaAs NWs include many twining defects, which are strongly related to the surface reconstructions. Growth modes change from initial tetrahedral growth to NW growth by introducing these defects.The length, diameter, shape and position of the nanowires were precisely controlled by optimization of the growth conditions and mask patterning. Manipulation of the growth conditions also enabled us to deliberately define the nanowire growth along either the axial or the radial direction, which has significant potential for the realization of novel nanostructures.Next, we report the fabrication of InP/InAs/InP core-multishell nanowire arrays. Low temperature photoluminescence measurements indicate successful formation of InAs quantum well tubes with thicknesses of several mono-layers on InP nanowire sidewalls. For device application, we fabricated single InGaAs nanowire-top-gate metal–semiconductor field-effect transistors (MESFETs). The top-gate MESFETs exhibited a peak transconductance of 33mS/mm and a current on–off ratio of 103. Finally, we introduce other applications of nanowires using this technique, such as, optically pumped GaAs/GaAsP core-cell nanowire lasers, fabrication of InP core-shell p-n junction nanowire solar cell, uniform GaAs and InAs nanowire array formation on Si (111) substrates, MuAs/GaInAs heterostructure nano-cluster formations on GaAs and their magnetic domain characterization.
10:00 AM - AA1.3
Optical Anisotropy of Semiconductor Nanowire Ensembles.
Silke Diedenhofen 1 , Otto L. Muskens 1 , Erik P.A.M. Bakkers 2 , Jaime Gomez Rivas 1
1 , FOM Institute for Atomic and Molecular Physics AMOLF, Eindhoven Netherlands, 2 , Philips Research Laboratories Eindhoven, Eindhoven Netherlands
Show AbstractArtificial materials fabricated from anisotropic building blocks like nanowires and nanotubes are of special interest for several applications like optical sensors, broadband antireflection coatings, and nano-photovoltaic devices. Nanowire materials hold merit due to their extreme tuneability by changing their dimensions and alignment. Samples with a high density of aligned nanowires are characterized by a strong optical form birefringence, i.e. different refractive indices for different polarizations of light. Here, we present measurements of the in-plane birefringence of GaP nanowires. The nanowires are grown in the vapor-liquid-solid growth (VLS) mode by metal-organic-vapor phase epitaxy (MOVPE) on a (100) GaP substrate. Scanning electron microscopy (SEM) images show that most of the wires are grown under an angle of 35 ° with respect to the substrate surface. Ensembles of semiconductor nanowires form a birefringent material consisting of two different in-plane refractive indices. The birefringence parameter Δn, defined as the difference between these two indices, of the nanowire layer was determined using transmission measurements. Linearly polarized light from a diode laser emitting at a wavelength of 690 nm transmitting through the nanowire layer is measured under normal incidence for crossed and parallel polarization. From these measurements, we determine the retardation as a function of the azimuthal angle of the nanowire sample. The birefringence in the nanowire layer is shown to depend on the GaP filling fraction of the wires, and accordingly to the wire diameter. Strongest birefringence was observed for a sample with a filling fraction of around 35 ± 5 % being 0.209 with an error of 10 %.1Nanowires can be grown of any semiconductor of groups IV, III/V, and II/VI on any crystalline surface, which allows the synthesis of birefringent media from visible to infrared wavelengths.1 O. L. Muskens, S. L. Diedenhofen, M. H. M. Van Weert, M. T. Borgström, E. P. A. M. Bakkers, and J. Gómez Rivas, Adv. Funct. Mater., (2008), 18, 7, 1039
10:15 AM - AA1.4
Optical Properties and Carrier Dynamics of Ensembles of InP Nanowires Grown on Non-single-crystal Platforms.
Takehiro Onishi 1 2 , Andrew Lohn 1 2 , Nobuhiko Kobayashi 1 2
1 Electrical Engineering, University of California, Santa Cruz, Santa Cruz, California, United States, 2 Advanced Studies Laboratories, NASA Ames Research Center, Moffett Field, California, United States
Show AbstractOptically active InP nanowires were grown on a quartz substrate covered with a layer (100 nm) of hydrogenated amorphous silicon (a-Si:H) by metalorganic chemical vapor deposition (MOCVD), demonstrating that single-crystal semiconductor nanowires can be formed on non-single-crystal surfaces. Scanning electron microscopy (SEM), X-ray diffraction (XRD), Raman spectroscopy, cathodeluminescence (CL) were used to characterize the structural and optical properties of the nanowires. The nanowires on a-Si:H grew in random directions with high density. The XRD profile suggests that nanowires having either hexagonal-close-packed or face-centered cubic lattices are present. Two distinct cross sectional geomotries of nanowires are observed amongst each other which is further evidence for the separate crystallographic habits found in the XRD profile. The Raman spectrum shows peaks associated with transverse optical (TO) and longitudinal optical (LO) branches of InP. The TO Raman peak closely matches that of bulk InP and the slightly larger shift in the LO mode could be caused by thermal expansion due to the green probe (514 nm) laser excitation. CL of a single InP nanowire was used to study the variations in luminescence along the long axis of the tapered nanowire from the base (~250 nm in diameter) to the tip (~10 nm in diameter). The luminescence intensity does not vary significantly in the growth direction of the nanowire. When probed at various positions along their length the wires emit from the entirety of their structure and without substantial variation along the long axis. This data suggests that recombination is slow enough to allow the carriers to diffuse the complete length of the nanowires (~2 µm) before recombining. Microscopic carrier recombination dynamics of the nanowires will be discussed with the view towards nanowire-based optical sensors using InP and other materials.[1] Kobayashi N. P., Wang S. Y., Santori C., Williams R. S., “Growth and characterization of indium phosphide single-crystal nanoneedles on microcrystalline silicon surfaces,” Applied Physics A 85 1-6 (2006).
10:30 AM - AA1.5
Electrical Characterization of Single GaSb Nanowire Field Effect Transistor.
Wei Xu 1 , Alan Chin 2 , Laura Ye 2 , Cun-Zheng Ning 1 2 , Hongbin Yu 1
1 Center for Solid State Electronics Research & Department of Electrical Engineering, Arizona State University, Tempe, Arizona, United States, 2 Center for Nanotechnology, NASA Ames Research Center, Moffett Field, California, United States
Show AbstractAmong III–V compound semiconductors, GaSb has the potential to be a promising candidate for high speed electronic and long wavelength photonic devices, due to its high mobility and low band gap.[1] In this work, we present the fabrication and electrical characterization of GaSb nanowire Field Effect Transistor (FET). The GaSb nanowires are synthesized using the self-catalyzed vapor-liquid-solid approach [2] and are unintentionally doped. Following the growth, the wires are removed from the growth substrate, suspended in alcohol, and dispersed onto SiO2 substrates for device fabrication. The Au/Cr contacts are fabricated using Electron Beam Lithography (EBL), followed by thermal evaporation and lift-off. Charge transport in unintentionally doped nanowires can have different regimes of operation, and these regions can be distinguished through voltage and temperature dependent study. The temperature dependent current-voltage characteristic shows asymmetric current through the device due to asymmetric back to back Schottky contacts at the two ends of the wire. By applying the Arrhenius plot, the Schottky barriers can be estimated to be 0.49eV and 0.53eV, which are close to reported values measured from the bulk material.[1] Due to the unintentionally doped nature and the presence of trap states of the wire, a transition from linear IV curve at small bias to the Space-Charge-Limited Current (SCLC) at higher bias was clearly observed. Analysis of the voltage and temperature dependencies of the SCLC showed that the nanowire surface traps are distributed in energy with a characteristic depth of ~0.12eV after annealing. The gate response results indicate the unintentionally doped nanowire to be n-type. This work provides a method on analyzing the nanowire Schottky current-voltage characteristics and the space-charge-limited current behavior, which can be commonly observed on characterizing the unintentionally doped nanowire devices. Further details of this approach and additional experimental and simulation results will be presented.[1]. P. S. Dutta and H. L. Bhat, J. Appl. Phys. 81 (9), 1 May 1997[2].S. Vaddiraju, M. K. Sunkara, A. H. Chin, C. Z. Ning,G. R. Dholakia, and M. Meyyappan, J. Phys. Chem C111(2007)7339
10:45 AM - AA1.6
Extracting Carrier Concentration and Mobility from Space-Charge-Limited Transport in InAs Nanowires.
Aaron Katzenmeyer 1 3 , M. Eugenia Toimil-Molares 1 , Jeffrey Cederberg 2 , Francois Leonard 1 , A. Alec Talin 1
1 , Sandia National Laboratores, Livermore, California, United States, 3 Electrical and Computer Engineering, University of California, Davis, California, United States, 2 , Sandia National Laboratores, Albuquerque, New Mexico, United States
Show AbstractSemiconductor nanowires continue to fascinate researchers, who are often motivated by the combination of high crystalline quality and nanoscale dimensions not easily accessible by ‘top-down’ lithographic means. In order for these nanostructures to have technological impact, their basic electrical characteristics have to be measured accurately and reproducibly; however, bulk techniques such as Hall measurements, cannot be easily implemented with nanowires due to small dimensions. Frequently, carrier type, concentration and mobility are determined from the transfer characteristics of a nanowire FET device. The results, however, can be strongly affected by the nanowire and the dielectric/nanowire surface and interface states, respectively. Here, we report on electrical characterization of VLS grown InAs nanowires using two distinct methods and compare their results. In the first approach, we fabricate nanowire FETs using Si/SiO
2 substrates and Au/Ti source-drain contacts using standard processing techniques. In the second approach we contact individual nanowires directly on the growth substrate using a W microprobe inside of a SEM. The transport for these in-situ contacted nanowires is initially ohmic, but becomes space-charge-limited at higher bias. Using a recently developed theory for space-charge-limited transport in nanowires,
1 we extract the mobility and carrier concentration. Both methods indicate that the carrier concentration increases with decreasing nanowire diameter, while the mobility is reduced. Effective carrier concentration ranged from 5 x 10
16 – 10
18 cm
-3 and mobility from 2400 – 3 cm
2/Vs for wires of radius 110 – 20 nm respectively.
1. A. A. Talin, F. Leonard, B. S. Swartzentruber, X.Wang, S. D. Hersee, Phys. Rev. Lett., 101, 076802 (2008)
11:30 AM - AA1.7
High-Speed and Low-Power Performance of n-type InSb/InP and InAs/InP Core/Shell Nanowire Field Effect Transistors for CMOS Logic Applications.
Mohammad Khayer 1 , Roger Lake 1
1 Electrical Engineering, University of California Riverside, Riverside, California, United States
Show AbstractInSb and InAs are being considered as attractive candidates for the channel of next generation field effect transistors (FETs). Intel and Qinetiq report that InSb-based FETs can achieve equivalent high performance with lower dynamic power dissipation to complement scaled Si-based devices (Intel and Qinetiq, IEEE IEDM, 2005). Although there are several reports in literature on the experimental realizations of these nanowire (NW) FETs, there are few attempts to theoretically model them. In this work, we model and theoretically investigate the performance metrics of highly scaled n-type InSb/InP and InAs/InP core/shell NWFETs using an 8-band k●p model and a semiclassical ballistic transport model. We present the ON-current, intrinsic cut-off frequency, gate-delay time, power-delay product, and energy-delay product of NWFETs with two NW diameters of 10 nm and 12 nm, which operate in the quantum capacitance limit. For all devices, drain bias voltage is fixed at 0.5 V and the gate bias voltage has been taken where the flat-band condition is met. A gate length of 10 nm is considered for each NWFET. The NWs simulated in this work are all [001] oriented. We find that the power-delay product values of 2x10-20-4x10-20 J of the NWFETs at source Fermi energy of 0.1 eV are all closely matched to the reported value of 5x10-20 J for a 3 nm NW diameter Si NWFET with a 10 nm gate length (J. Knoch, et al., IEEE EDL, 2008). The corresponding gate-delay times of 3-5 fs are also closely matched to the reported value of 5 fs for the 3 nm NW diameter Si NWFET with a 10 nm gate length. However, the ultra-small diameters of 3 nm necessary for Si NWFETs to obtain the reduced power-delay product and gate-delay time are not required for InSb and InAs NWFETs. Moreover, the energy-delay product values of 4x10-33-6x10-33 Js for these NWFETs with a source Fermi energy of 0.2 eV are found to be closely matched to the projected experimental curve for III-V planar n-channel HEMTs (R. Chau, et al., IEEE TNT, 2005) with 10 nm channel width. The energy-delay product values of 1x10-32-2x10-32 Js with 12 nm diameter InSb and InAs NWFETs with a source Fermi level of 0.3 eV are found to be 10 times smaller than the projected experimental curve for planar n-channel Si MOSFETs (R. Chau, et al., IEEE TNT, 2005). The ON-current varies from 7-58 μA with a source Fermi energy range of 0.1-0.3 eV. With higher Fermi energy, multiple conduction modes are occupied and larger ON-current is obtained. The intrinsic cut-off frequency ranges from 8-15 THz with source Fermi energy ranging from 0.1-0.3 eV, which is good for RF application. For all devices, with a source Fermi energy range of 0.1-0.3 eV, the power-delay product varies from 2x10-20-97x10-20 J, gate delay time ranges from 2-19 fs, and the energy-delay product varies from 7x10-35-1x10-32 Js. These NWFETs provide both ultra low-power switching and high speed.
11:45 AM - AA1.8
Growth and Optical Properties of GaN Nanodisks in GaN/AlGaN Nanowires.
Florian Furtmayr 1 , Christoph Stark 1 , Martin Stutzmann 1 , Sonia Conesa-Boj 2 , Francesca Peio 2 , Jordi Arbiol 2 , Joan Ramon Morante 2 , Martin Eickhoff 3
1 Walter-Schottky-Institut, Technische Universität München, Garching Germany, 2 EME/XaRMAE/IN2UB, Dept. d'Electrònica, Universitat de Barcelona, Barcelona Spain, 3 I. Physikalisches Institut, Justus-Liebig-Universität, Giessen Germany
Show AbstractWe report on the growth of self assembled GaN/AlGaN and GaN/AlN nanowires with embedded GaN nanodisks by plasma assisted molecular beam epitaxy (PAMBE) on Si(111) substrates. Due to their low density of structural defects, they present a promising approach for the realization of improved optoelectronic devices for light emission or for chemical sensors using the high surface to volume ratio of nanowires.For the formation of nanodisks (NDs), GaN nanowires (NWs) with a length of 400 nm and diameter of 25 nm were grown, directly followed by the quantum well structure. In the investigated samples, GaN multi quantum wells with different thicknesses (1.5 nm – 4 nm) were formed between barriers of 8 nm AlN or AlxGax-1N in different Al-compositions. The samples were analyzed by high resolution transmission electron microscopy (HRTEM) and low temperature photoluminescence (PL).The PL emission energy from the ND part can be influenced by variation of the Al-content in the barrier, i.e. the Al flux during growth. In this work an increase of the beam equivalent pressure (BEPAl) from 1.5 x 10-8 mbar to 6 x 10-8 mbar results in an increase of the emission energy from 3.53 eV to 3.70 eV. Its intensity exceeds the emission from the GaN NW itself (3.40 eV – 3.47 eV) by about a factor of ten. The full width at half maximum is as low as 21 meV (at 4K) for the sample with the smallest Al-concentration and rises with increasing Al-concentration up to 77 meV. Due to the presence of polarization fields, the emission shows a red shift with increasing well-thickness. The temperature-dependent quenching of the QD emission is found to be less pronounced than that of the GaN NWs.HRTEM analysis of the GaN/AlN nanowires reveals well defined flat GaN disks with sharp interfaces embedded in AlN and shows a slight reduction of the ND diameter towards the top. The c lattice parameter (which is 0.518 nm for unstrained GaN) is found to be 0.500 nm for the GaN NDs and 0.495 nm for the AlN barriers, showing that GaN is under tensile strain inside the NDs and pseudomorphically adapted to the AlN barriers. Whereas the radial growth rate of the GaN part is almost zero, we find a radial growth of the AlN region with a rate of 11% of the axial growth, leading to the formation of an AlN shell around the whole NW and, due to the enlarged NW diameter, to an increase of the diameters of the following NDs. However, the thicknesses of the individual wells are constant.As a radial growth of GaN depends on the incoming Ga-flux, these results open up the possibility to form core shell structures with quantum wells on the non polar side facets of the nanowires.
12:00 PM - AA1.9
Spatially-Resolved Cathodoluminescence Study of GaN, GaN/AlGaN, and GaN/InGaN Core-Shell Nanowires
George Wang 1 , Qiming Li 1 , A. Alec Talin 2 , Andrew Armstrong 1 , M. Eugenia Toimil Molares 2
1 , Sandia National Laboratories, Albuquerque, New Mexico, United States, 2 , Sandia National Laboratories, Livermore, California, United States
Show AbstractGaN, GaN/AlGaN, and GaN/InGaN core-shell nanowires grown by Ni-catalyzed metal-organic chemical vapor deposition were studied by spatially-resolved cathodoluminescence (CL). For GaN nanowires, band-to-band luminescence at 362 nm and defect-related yellow luminescence at 550 nm are observed. Point defects, which lead to the yellow luminescence, possibly deplete free carriers near the nanowire surface. This depletion is evidenced by the existence of a critical GaN nanowire radius, below which yellow luminescence dominates. The thickness of the surface depletion layer is estimated to be ~15 nm based on an analysis of the 362 and 550 nm luminescence intensities as a function of nanowire diameter. GaN/AlGaN and GaN/AlN core-shell nanowires are observed to exhibit stronger band-to-band emission at 362 nm as compared with GaN nanowire without an AlGaN shell. The enhanced band-to-band emission is attributed to the passivation of the surface states of GaN nanowires. Electrical measurements further suggest an improvement in the conductivity related to the presence of an AlGaN or AlN shell layer. GaN/InGaN multi-quantum well core/shell nanowires were also investigated by spatially resolved CL, the results of which reveal a strong dependence of shell layer growth rate on the GaN nanowire facet orientation. The morphology revealed by the spatially resolved CL results is confirmed by cross-sectional scanning TEM studies. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy under contract DE-AC04-94AL85000.
12:15 PM - AA1.10
Modeling and Design of Dislocation-Free Nanostructured InGaN-Based Light Emitting Devices
Zhiwen Liang 1 3 , Robert Colby 1 3 , Dmitri Zakharov 1 3 , Isaac Wildeson 2 3 , R. Edwin Garcia 1 3 , Eric Stach 1 3 , Tim Sands 1 2 3
1 Materials Engineering, Purdue University, West Lafayette, Indiana, United States, 3 Birck Center for Nanotechnology, Purdue University, West Lafayette, Indiana, United States, 2 School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana, United States
Show AbstractThe production of InGaN-based Light Emitting Diodes (LEDs) of low dimensionality constitutes a radical departure from conventional thin-film LED fabrication approaches, for it has the potential of delivering dramatically improved efficiencies. Through the careful incorporation of indium into a gallium nitride nano-pyramidal structure base, the band gap (the color) of the device can be engineered, and thus light emission over the entire visible spectrum can become possible. The main advantage of this approach is the suppression of dislocation formation, particularly in the region where electron-hole pair recombination takes place. The aforementioned processing technique favors the introduction of a significantly large fraction of surfaces that greatly relaxes the processing stresses on the LED structure and diminishes the possibility of nucleating defects. Kinetic and thermodynamic factors such as spinodal decomposition of the InGaN system limits indium incorporation, which combined with the underlying thermal and piezoelectric stresses can lead to a potential decrease in the quantum efficiency of the overall structure. In the present paper, by carefully exploring the effect of topology and thermal annealing, the nucleation of dislocations in GaN-based nanostructures is investigated to provide conditions that favor the emission of light at a tailored frequency. A computational analysis based on the finite volume method is used to implement a phase field description that couples the effect of strain and spinodal decomposition as the pyramids attempt to relax. Simulations show preferential segregation of InN in those regions that are stress-free. The effect of annealing temperature is summarized in time-temperature transformation (TTT) diagrams. Comparisons against bulk, thin film behavior, and experimental data are made. Improved designs that will lead to an optimal InN distribution are proposed. This material is based on work supported by the Department of Energy under Award No. DE-FC26-06NT42862
12:30 PM - AA1.11
Deep Level Optical Spectroscopy of GaN Nanowires.
Andrew Armstrong 1 , Qiming Li 1 , A. Alec Talin 2 , George Wang 1
1 , Sandia National Laboratories, Albuquerque, New Mexico, United States, 2 , Sandia National Laboratories, Livermore, California, United States
Show AbstractGaN nanowires (NWs) are attractive elements for nanoscale electronic and optoelectronic application, but currently little is known about the physical origin of defects in these nanomaterials. Here, we have used photoconductivity deep level optical spectroscopy (DLOS) to measure the optical ionization energy (Eo) and Franck-Condon shift (dFC) of band gap states in vapor-liquid-solid grown GaN NWs. Unintentionally doped, n-type NWs were individually contacted for DLOS analysis at 300K, and photoluminescence (PL) spectra of single NWs were also taken. DLOS revealed a minority carrier deep level near Ec - 0.8 eV (where Ec is the conduction band minimum) that is near a surface state predicted to pin the Fermi level for n-type, c-plane GaN surfaces [1]. DLOS spectra of GaN and AlGaN/GaN core-shell NWs will be compared to investigate the possible surface nature of this defect. In addition, a band gap state at Ec – 2.81 eV (dFC = 0.28 eV) was observed via DLOS, and a broad defect band centered at 2.25 eV was detected by PL. The associated defects are not particular to the surface based on their similarity to previous reports for thin film GaN. Further, their strong degree of phonon-coupling suggests that the Ec - 2.81 eV level and the 2.25 eV PL band stem from the same defect, which is likely related to either carbon impurities [2] or gallium vacancies [3].1 Van de Walle et al., J. Appl. Phys. 101 081704 (2008).2 Klein et al., Appl. Phys. Lett. 79, 3527 (2001).3 Reshchikov et al., MRS Symp. Proc. 93, I6.19 (2002).
12:45 PM - AA1.12
Controlled Growth and Characterization of Non-tapered InN Nanowires on Si(111) Substrates by Molecular Beam Epitaxy.
Yi-Lu Chang 1 , Arya Fatehi 1 , Zetian Mi 1
1 , McGill University, Montreal, Quebec, Canada
Show AbstractInN nanowires self-catalytically grown on Si substrates, with emission wavelengths at ~ 1.6 µm, promise a new generation of on-chip nanoscale lasers, in addition to their growing importance for the development of future nanoscale electronic and biosensing devices. However, there still lacks a fundamental understanding of the growth mechanisms of InN nanowires on Si. The resulting nanowires generally exhibit tapered morphology, leading to uncontrolled electrical and optical properties. In this context, we have performed a detailed investigation of the molecular beam epitaxial (MBE) growth and characteristics of InN nanowires directly on Si(111) substrates. With the use of an in situ deposited indium seeding layer, we have achieved superior quality InN nanowires with completely eliminated tapered morphology, which exhibit an extremely narrow photoluminescence linewidth of ~ 25 meV at room temperature. The wire densities can also be controllably varied from ~ 5/µm2 to ~ 500/µm2. InN nanowires are grown on Si(111) substrates using radio-frequency plasma-assisted MBE in the temperature range of 440 – 520 °C under N-rich conditions. The indium flux was varied in the range of 0.3 – 1.0 ×107 Torr. A nitrogen flux of 1.6 sccm and a plasma forward power of 425 W were used. A thin (~ 1 – 6 monolayer) indium layer is first deposited on Si substrates, which serves as seeds for the nucleation of InN nanowires. Such an indium layer also minimizes the formation of a SiNx interface between the Si and InN nanowires. InN nanowires are characterized by field emission scanning electron microscopy, transmission electron microscopy, and photoluminescence measurements. The wires are of wurtzite structure and well separated, with the c-axis oriented vertically to the Si(111) substrate. Compared to the commonly observed tapered morphology of InN nanowires on Si, such nanowires are straight, with identical top and bottom sizes. The InN/Si interface also contains very low defect densities and few stacking faults. By varying the thickness of the indium seeding layer as well as the growth conditions, InN nanowires with diameters in the range of 20 – 200 nm, heights from ~ 0.5 to 2 µm, and areal densities from ~ 5/µm2 to ~ 500 µm2, can be achieved. Additionally, such InN nanowires exhibit strong photoluminescence emission, with a peak wavelength at ~ 0.75 eV. An extremely narrow linewidth of ~ 25 meV is also measured from an InN nanowire ensemble at room temperature, compared to the commonly observed 50 – 100 meV, which further confirms the extremely high quality and significantly reduced tapering and broadening. The temperature-dependent bandgap, electron concentration, and transport properties of such high quality, nontapered InN nanowires on Si are being investigated. These results, together with the achievement of InN/InGaN core-shell and well-in-a-wire nanoscale heterostructures, will be presented.
Symposium Organizers
Paul C. McIntyre Stanford University
Joan M. Redwing The Pennsylvania State University
Volker Schmidt Max-Planck-Institut für Mikrostrukturphysik
Silvija Gradecak Massachusetts Institute of Technology
AA6: Poster Session: Semiconductor Nanowires II
Session Chairs
Wednesday PM, April 15, 2009
Salon Level (Marriott)
9:00 PM - AA6.1
Reduced Thermal Conductivity in Large-area Vertically-aligned Silicon Nanowires.
Ting-Kang Chen 1 , Min-An Tsai 1 , Peichen Yu 1
1 Photonics, National Chiao-Tung University, Hsinchu Taiwan
Show Abstract Since silicon is widely used in the integrated circuit (IC) industry, the ability to tailor the thermoelectric properties of bulk silicon using its nanostructures can enable a variety of exciting applications, such as efficient thermo-photovoltaic devices, and monolithically- integrated electronic and optoelectronic device cooling. In late 2007, scientists have reported that a single silicon nanowire (Si NW) with a diameter less than 52nm exhibits a low thermal conductivity ~1.6 W/mk and ZT ~1 at room temperature, suggesting the potential of using Si NWs for efficient thermoelectric energy conversion. In order to realize a practical thermoelectric device based on Si NWs, it is essential to fabricate large-area and highly-oriented Si NW arrays on silicon substrates. In this paper, we demonstrate the preparation of vertically-aligned Si NWs with diameters of tens of nanometers, heights ranging from tens of micrometers to over 100 μm, and most importantly, an area over 5x5 cm^2. Characterizations using a hot-disk slab-module system show the thermal conductivity reduced by 13.4% for the fabricated Si NW samples, compared to that of bulk silicon. Two-dimensional microscale heat-transfer analyses of Si NWs based on the equation of phonon radiative transfer are in progress and will be presented. The high-aspect-ratio and vertically-aligned Si NW arrays were fabricated using a silver-induced wet deposition and wet chemical etching method. The surface morphology and the etching length depend on the concentration of both AgNO3 and HF solution, the etching temperature, and etching time. The concentration of AgNO3 affects the structure of the nanowire arrays because the porosity is determined by the density of deposited Ag particles. A Hot Disk 2500 slab-module system was then employed to measure the thermal conductivity of the fabricated NWs. During the measurement, the sensor was sandwiched between two samples, while the other side of samples was insulated by a material with a low thermal conductivity in order to reduce the heat losses to the surroundings. We measured the increment in temperature versus time for two uniformly-distributed Si NW samples with heights of 32 μm and 43 μm fabricated on 650-μm-thick Si substrates, while two pieces of bare 650-μm-thick Si substrates were used for control experiments. Preliminary characterizations show that the Si NW samples exhibit a reduced thermal conductivity of 116 W/mK, compared to that of bulk Si, ~134 W/mK. Moreover, the thermal conductivities and thermal diffusivities obtained from Si NW samples were lower than bare Si substrates for all nine individual experiments. In summary, we have successfully fabricated large-area, high-aspect-ratio Si NW arrays, and measured their thermal properties using a Hot Disk system. The Si NW samples exhibit a reduced thermal conductivity, compared to that of bulk Si, showing great potential for next-generation thermoelectric devices.
9:00 PM - AA6.10
Enhancement-Mode Si Nanowire Field Effect Transistors on a Flexible Plastic Substrate
Eun-Ae Chung 1 2 , Jamin Koo 1 , Myeongwon Lee 1 , Dong-Young Jeong 1 , Sangsig Kim 1
1 Department of Electrical Engineering and Institute for Nano Science, Korea university, Seoul Korea (the Republic of), 2 Process Development Team, Memory R&D Center, Samsung Electronics Co., Ltd, Hwasung, Gyeonggi-Do, Korea (the Republic of)
Show AbstractSilicon (Si) nanowire field-effect transistors (NWFETs) with channels of the n+-p-n+ segments of single-crystalline Si nanowires (NWs) were fabricated on a flexible plastic substrate, and their electrical characteristics were investigated. P-type Si NWs utilized in this study were manufactured by the conventional top-down approach, and arsenic implantation was performed subsequently for the formation of the n-type region in these p-type Si NWs. The implanted NWs were transferred onto a plastic substrate for large scale integration. Si NWFETs fabricated by this approach exhibited outstanding controllability and reproducibility of doping and reliable ohmic contacts.The Si NWFETs formed on a plastic substrate revealed their excellent enhancement-mode characteristics and high on/off current ratios. Strong inversion and clear saturation were observed in the NWFETs. These characteristics of geometrically well-defined and doped Si NWs make it possible to manufacture integrated nanoscale electronics in mass production at low cost without any additional alignment processes of NWs.
9:00 PM - AA6.12
Control of Growth Mechanisms and Orientation in Epitaxial Si Nanowires Grown by Electron Beam Evaporation.
Alessia Irrera 1 , Emanuele Pecora 1 2 , Francesco Priolo 1 2
1 , MATIS CNR-INFM, Catania Italy, 2 , Physics and Astronomy Department , University of Catania, Catania Italy
Show AbstractThe growth mechanisms of epitaxial Si nanowires (NWs) grown by electron beam evaporation (EBE) and catalyzed through gold droplets are identified. Electron beam evaporation (EBE) is a quite important physical method, as opposed to CVD, much less expensive than MBE, well diffused, and, being a non-UHV technique, with a much higher throughput, which makes it interesting for industrial applications. NWs are seen to grow both from adsorbed Si atoms diffusing from the substrate and forming a dip around them, and from directly impinging atoms. The growth of a 2D planar layer competing with the axial growth of the NWs is also observed and the experimental parameters determining which of the two processes prevails are identified. NWs with (111), (100) and (110) orientation have been found and the growth rate is observed to have a strong orientation dependence suggesting a microscopic growth mechanism based on the atomic ordering along (110) ledges onto (111)-oriented terraces. By properly changing the range of experimental conditions we demonstrate how it is possible to favor the axial growth of the NWs, define their length in a wide range between 100 nm and 1400 nm. Finally we demonstrate how to control the crystallographic orientation ((111), (100) or (110)) of the NWs by properly varying the deposition conditions. In particular we show how the (111)-oriented NWs can be transformed from being the 90% of the total population to being only the 20%.
9:00 PM - AA6.13
HWCVD-grown Silicon Nanocrystals : A Study of the Effect of Annealing on Structures Evolved with Varying Growth Rates.
Prantik Mahajan 1 , Tarkeshwar Patil 1 , Subhananda Chakrabarti 1
1 Centre for Nanoelectronics, Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, Powai, Mumbai - 400076, Maharashtra, India
Show AbstractIn the past few decades, silicon nanocrystals fabricated using different processes such as PECVD, LPCVD and Laser Ablation have received considerable attention mainly because of their potential application in devices such as semiconductor memories, photodetectors, solar cells, far infrared sensors and Thin Film Transistors (TFTs). But no effort has been made to tailor the size and shape of the nanocrystals which may ultimately be useful in achieving tunable devices. Hence, the novel approach of growing silicon nanocrystals by depositing thin films at low temperature using Hot Wire Chemical Vapor Deposition (HWCVD) process has been studied. The primary advantage of this HWCVD technique is that it allows deposition at low temperatures, which on one hand is economical and on the other ensures a controlled growth. In HWCVD, the deposition rate can be regulated by controlling the hot wire filament power as well as the gas flow rate. We tried to investigate the effect of variation in deposition rate of amorphous silicon and subsequent annealing in formation of silicon nanocrystals using HWCVD technique. HWCVD was used to deposit a Si3N4/nc-Si/Si3N4/nc-Si structure on n-type (100) Silicon at low temperature (i.e., at 350°C). Our aim was to study the variation in evolution of the nanocrystals, if any, with varying growth rates. In our experiments, we varied the deposition rate of amorphous silicon by cracking Silane for different times as well as varying the gas flow rate, keeping the thickness of the amorphous silicon layer constant. The samples were then annealed at temperatures of 800°C and 900°C respectively in a quartz tube furnace in Ar ambient for 30 mins. AFM studies revealed a tendency of formation of silicon nanocrystals after annealing of the as-deposited samples, particularly in those with higher deposition rates. RMS surface roughness was found to increase with increasing annealing temperature (ranging from 0.316 nm in the as-deposited one to 0.617 nm in its annealed version at 900°C for the sample with the highest deposition rate i.e. 1.5 Å/sec). The vertical and horizontal dimensions of the nanostructures range from 0.366 nm to 4.382 nm and 7.813 nm to 204.832 nm respectively, across the different samples. With progressive annealing the nature of the nanocrystals changed from wires to clustered dots which were nearly spherical in shape, an interesting feature on which no reports have been made as yet. The sample was also characterized by Confocal Micro Raman and XRD techniques. The FWHM from the Micro Raman data at room temperature and at liquid nitrogen temperature (77K) were found to be 2.4 cm-1 and 3.4 cm-1 respectively (which are the lowest reported FWHMs till date), with the amorphous silicon peak at 520 cm-1. XRD analysis also corroborates our findings and testifies to the presence of silicon nanocrystals. The above results will be presented and discussed.
9:00 PM - AA6.15
Synthesis and Magnetic Properties of (Fe, Co):Si Nanowires.
Han-Kyu Seong 1 , Tae-Eon Park 1 , Myoung-Ha Kim 1 , Il-Soo Kim 1 , So-Jing Shim 1 , Heon-Jin Choi 1
1 Department of Materials Science and Engineering, Yonsei University , Seoul Korea (the Republic of)
Show AbstractSpintronic devices, which simultaneously manipulating both charge and spin in a single semiconductor medium, are one of the possible candidates for substituting current silicon-based complementary metal-oxide-semiconductor (CMOS) devices. Among these, Si-based spintronics is much less developed compared with those based on the diluted magnetic semiconductor (DMS) in III-V group, due to limitation in Si-based magnetic materials. In the present work, we studied the synthesis and magnetic properties of transition metal (Fe, Co):Si nanowires. We fabricated single crystalline Si nanowires on Si substrate in a chemical vapor transport system. After treated in BOE to remove the native oxide layer of the as-grown Si nanowires, the substrate and metal sources (FeCl3 and/or CoCl2) were placed in a reactor, respectively. The transition metal doped M1-xSix (M : Fe or Co, x = 0 ~ 4) nanwoires were synthesized by transporting metal sources onto the as-grown substrate under pressure of 200 torr at 600 ~ 800 0C. The diameter and length of these nanowires were from 50 nm to 150 nm and tens of micrometers, respectively, while holding the single crystallinity. We also synthesized single crystalline MSi silicide nanwoires and FeSi/Si longitudinal heterostructure nanowires by controlling the processing conditions. Magnetic characterization of the nanowires using a superconducting quantum interference device (SQUID) and x-ray magnetic circular dichroisn (XMCD) showed that transition metal have local magnetic moments.
9:00 PM - AA6.16
Non-catalytic CVD Growth of Single-crystal Germanium Nanowires.
Byung-Sung Kim 1 , Jong Woon Lee 1 , Tae Woong Koo 2 , Jae Hyun Lee 1 , Jae Hyun Ahn 3 , Young Chai Jung 3 , Sung Woo Hwang 3 , Dongmok Whang 1 2
1 SKKU Advanced Institute of Nanotechnology (SAINT), Sungkyunkwan University, Suwon Korea (the Republic of), 2 School of Advanced Materials Science and Engineering , Sungkyunkwan University, Suwon Korea (the Republic of), 3 Research Center for Time Domain Nano-functional Devices (TiNa) & School of Electrical Engineering, Korea University, Seoul Korea (the Republic of)
Show AbstractGermanium nanowires (GeNWs) are promising building blocks for high-speed switching devices and optoelectronic applications. Additionally, the excitonic Bohr radius of bulk (24.3 nm) Ge is significantly larger than that of Si (4.9 nm), hence resulting in more prominent quantum size effects. GeNWs have been usually synthesized by metal-catalyzed growth methods based on the vapor-liquid-solid (VLS) mechanism. However, a metal-free approach for controlled nanowire growth is highly desired since unavoidable metal impurities in metal-catalyzed nanowires may be detrimental to their commercial devices. Here, we report non-catalytic growth of metal-free single crystalline GeNWs by low-pressure chemical vapor deposition (LPCVD) process. In addition, carrier doping of the GeNWs was also performed using dopant gas during CVD growth and field effect behavior of the metal-free GeNWs with different doping levels was also investigated.
9:00 PM - AA6.17
Synthesis and Characteristic of Si Nanowires with sub < 5 nm
Myoung-Ha Kim 1 , Ungkil Kim 1 , Il-Soo Kim 1 , So-Jung Shim 1 , Han-Kyu Seong 1 , Heon-Jin Choi 1
1 Materials Science and Engineering, Yonsei university, Seoul Korea (the Republic of)
Show AbstractThe downscaling of electronic devices is critical issue in modern information industries. In this regard, semiconductor nanowires have drawn considerable attention as the building blocks for electronic devices on a nanometer scale with superior performance. Especially, Si nanowires are attractive due to their compatibility with CMOS semiconductor technology. Meanwhile, quantum sized nanowires (i.e., the nanowires having comparable size to their Bohr exciton radius) are attractive since they may have novel physical and chemical properties. In this work, we synthesized the quantum-sized Si nanowires by vapor-liquid-solid (VLS) growth process using Al and Ti as a catalyst. The average diameter of Si nanowires is 5 nm with narrow size distribution. Transmission electron microscopy analysis indicated that the Si nanowires are single crystalline with growth direction of [311] while that of Si nanowires having the diameter > 100 nm was [111] or [100]. The surface of nanowires was flat with the thickness of native oxide layer of under 1 nm. The optical and electrochemical properties of Si nanowires were investigated and the results will be discussed toward development of novel Si based nano devices.
9:00 PM - AA6.18
Controlled diameter of Silicon Nanowires Using CVD
Jun-Hyoung Chang 1 , Woo-Jin Lee 1 , Suk-In Hong 1
1 Chemical and Biological Engineering, Korea Univ., Seoul Korea (the Republic of)
Show AbstractSilicon nanowires were grown on the gold deposited silicon wafer by thermal evaporation of SiO + BO powders at 1300 celsius degrees. The changes of pressure in alumina tube has influence upon diameter of silicon nanowires which were synthesized. it were linear dependence between the diameter of nanowire which were synthesized on the substrates and changes of pressure.for 15min under flowing gas mixture of 5% H2-Ar The SiO + BO powders and were placed inside of alumina tube, which were heated by the tube furnace. Prior to observe relationship between the growth of silicon nanowires and process pressure at changes in vacuum pressure, grown silicon nanowires at different vacuum pressure for 300, 450, 600, 750, 900 mTorr and 1atm. The changes of pressure in alumina tube has influence upon diameter of silicon nanowires which were synthesized on alumina plate and gold deposited Si wafer. it were linear dependence between the diameter of nanowire which were synthesized on the both substrates and changes of pressure.
9:00 PM - AA6.19
Time and Temperature Dependence of the Growth of Ge Nanowires.
Joon-Shik Park 1 2 , Duck-Jin Kim 3 , James Groves 2 , Nae-Eung Lee 3 , Woo-Kyeong Seong 1 , Hyo-Derk Park 1 , Bruce Clemens 2
1 , Korea Electronics Technology Institute, Seongnam Korea (the Republic of), 2 Dept. Materials Science and Engineering, Stanford University, Stanford, California, United States, 3 , Sungkyunkwan University, Suwon Korea (the Republic of)
Show AbstractDespite significant recent activity, there remains a need for clarification of interplay between various growth parameters resulting in favorable Ge nanowire growth conditions. In particular, the growth rate as a function of time and temperature has not been widely explored and, unlike the case for Si nanowire growth, the growth activation energy has not been reported. To address this need, Ge nanowires were grown at different temperatures and times to illuminate the growth rate behavior. We use scanning electron microscopy (SEM) and x-ray diffraction to examine the resulting nanowires. Nanowires were grown in a pressure of 30 Torr of a mixture of 10.4 % GeH4 in Ar, at temperatures ranging from 250 °C to 300 °C. A 3 nm thick Au film catalyst deposited on a (111) p-type Si wafer was used as a growth substrate. For all temperatures, the growth rate was observed to decrease with time, with the largest growth rate decrease occurring for the highest growth temperatures. Over the temperature range studied, the growth rate increases with temperature, with a maximum growth rate of over 35 nm/s observed for short times (~ 2 minutes) at 300 °C. The activation energy extracted from these measurements is compared to the gas decomposition and growth processes to illuminate the growth-limiting step. From these results, we find that copious quantities of Ge nanowires can be reproducibly produced at growth times of the order of 2 to 20 minutes at growth temperatures of 280 °C to 300 °C. These process conditions for growth of Ge NWs could be used for fabrications of boron doped Ge nanowires and Ge/Si hetero-structure nanowires for nanowire field effect transistors applications. *Corresponding authors: jspark@keti.re.kr and bmc@stanford.edu< Acknowledgements >This work was supported by “International Semiconductor Collaboration Research” of "System IC 2010" project of Korea Ministry of Knowledge Economy. The authors thank government for financial supports. Also, we thank Linyou Cao of Prof. Brongersma Group of Stanford University for helpful discussion about nanowire synthesis.
9:00 PM - AA6.2
Fabrication of Highly-Textured Polycrystalline Silicon TFTs Using Single-Crystalline Si Nanowire Seed Templates
Donghun Lee 1 , Hyun-Seung Lee 1 , Gil-Sung Kim 1 , Geunhee Lee 1 , Moon-Ho Jo 1
1 Materials Science and Engineering, Pohang University of Science and Technology (POSTECH), Pohang Korea (the Republic of)
Show AbstractCrystallization of amorphous Si thin films at low temperature is important due to their applications into Si solar cells and Si thin-film transistors. Among a number of growth processes to achieve large-grained polycrystalline Si thin films, crystallization of amorphous Si using the local nucleation seeds is of particular interest, because it can offer advantageous solid-phase crystallization at the controlled sites at low temperatures. In this study, we report solid-phase epitaxial growth of amorphous Si thin films using single-crystalline Si nanowires as seed templates. We have synthesized the arrays of vertically-aligned single-crystalline Si nanowires using Au-catalyst assisted chemical vapor deposition, followed by amorphous Si thin film deposition on the synthesized nanowire templates. Upon thermal annealing processes, we observed that amorphous Si thin films crystallize into highly textured polycrystalline Si thin films in excellent epitaxial relations with single-crystalline Si nanowires in a layer-by-layer fashion. We also discuss the electrical characteristics observed from Si thin-film transistors based on these highly-textured polycrystalline Si channels.
9:00 PM - AA6.20
Synthesis and Characterization of SnO2 Nanowires by Thermal Evaporation
Won-Sik Kim 1 2 , Daihong Kim 1 2 , Myung Yang 1 2 , Seong-Hyeon Hong 1 2
1 Department of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 Nano Systems Institute- National Core Research Center, Seoul National University, Seoul Korea (the Republic of)
Show AbstractSemiconductor-type metal oxide nanowire sensors are the most promising devices among the solid state chemical sensors, because they have many advantages such as a large surface to volume ratio, a Debye length comparable to the nanowires radius, and low power consumption. Therefore, the synthesis of one-dimensional nanostructures has been widely explored in the semiconductor-type metal oxide systems such as SnO2, ZnO, In2O3, Ga2O3, etc. Among those materials, SnO2 nanowires as a wide band gap semiconductor (3.6 eV at 300 K) have been extensively studied because of its high gas sensitivity.Among the various nanostructures, a vertical and epitaxial nanowire growth has been studied in the systems such as Ge on Si, In2O3 on YSZ, ZnO on GaN or sapphire. However, a vertical and epitaxial grown SnO2 nanowire is very limited. In case of ZnO nanowires, the growth direction was [001] in most of cases, but S. Bubak et al. recently reported that SnO2 nanowires showed the different morphologies depending on the substrate and substrate orientations.In this study, SnO2 nanowires were synthesized using a thermal evaporation method and the various oriented TiO2 single crystal were used as the substrate because they have the same crystal structure with SnO2. In the thermal evaporation process, a high process temperature (>1123 K) generated too high Sn vapor and resulted in a randomly grown nanowires. Furthermore, it is difficult to control the growth rate. Thus, we decreased process temperature to 1073 K and adjusted the other factors (gas flow and pressure) to provide an appropriate quantity of Sn vapor. The phase and morphology of the obtained SnO2 nanowires were characterized by using XRD and FE-SEM. Moreover, a pole figure analysis was performed to confirm the in-plane relationship, and growth direction of nanowire was investigated by HR-TEM. The synthesized nanowires showed different orientations depending on the substrate orientations. A jungle gym like-structure was observed on the (001) and (110) TiO2 substrate. On the other hand, SnO2 nanowires were vertically grown on the (101) TiO2 substrate. XRD (θ-2θ) analysis showed that SnO2 nanowire on (101) TiO2 substrate has (101) preferred orientation (out-of-plane). The in-plane orientation between SnO2 nanowire and (101) TiO2 was also well matched. The detailed microstructure and growth mechanism will be discussed in this presentation.
9:00 PM - AA6.21
Seeded ZnO Nanostructures Epitaxially Grown on Si (100) Substrates by Chemical Vapor Deposition.
Zhuo Chen 1 , Tom Salagaj 2 , Christopher Jensen 2 , Karlheinz Strobl 2 , Mim Nakarmi 1 , Kai Shum 1
1 Physics, Brooklyn College - CUNY, Brooklyn, New York, United States, 2 , First Nano, a Division of CVD Equipment Corp., Ronkonkoma, New York, United States
Show AbstractVarious ZnO nanostructures such as nanowire-networks and vertical nanorods were epitaxially grown on pre-seeded Si (100) substrates by Chemical Vapor Deposition (CVD) method with a mixed ZnO-powder/C-powder solid source. Crystalline ZnO seeds were prepared and controlled by the rapid thermal annealing (RTA) treatment of e-beam deposited amorphous ZnO thin films with various thicknesses. Both epitaxial film and pre-deposited ZnO seeds were characterized by Atomic Force Microscopy (AFM), Scanning Electron Microscopy (SEM), and photoluminescence (PL) spectroscopy. Excellent optical characteristics of these nanostructures such as PL line width, linearity of PL intensity as a function of excitation power density were obtained.
9:00 PM - AA6.22
Rapid Flame Synthesis of Dense, Aligned α-Fe2O3 Nanoneedle Arrays.
Pratap Rao 1 , Xiaolin Zheng 1
1 Mechanical Engineering, Stanford University, Stanford, California, United States
Show AbstractOne-dimensional iron oxides (α-Fe2O3 and Fe3O4) are of practical interest because of their potential application as recording media due to their magnetic properties and anisotropy, and in chemical looping combustion as oxygen carriers to facilitate the sequestration of CO2.α-Fe2O3 nanoneedles have been synthesized by the oxidation of solid elemental iron in air or other oxidizing atmospheres. These experiments were carried out on hotplates or in tube furnaces between the temperatures of 700 and 900°C and yielded axial growth rates of α-Fe2O3 nanoneedles that were on the order of 1 μm per hour. Herein, we report a new flame synthesis method for producing dense, aligned arrays of crystalline α-Fe2O3 nanoneedles with an axial growth rate of approximately 1 μm per minute, almost two orders of magnitude larger than those demonstrated previously. Specifically, the α-Fe2O3 nanoneedles are synthesized by the oxidation of untreated Fe foils and wires in the post-flame region of a methane-hydrogen-