Bill Taylor Sematech, Inc.
Rusty Harris Texas A&M University
Jeff Butterbaugh FSI International
Alex Demkov University of Texas-Austin
Willy Rachmady Intel Corporation
C1: Dielectrics I: Advanced Doped and Epitaxial Oxides
Tuesday PM, April 14, 2009
Room 2006 (Moscone West)
9:00 AM - **C1.1
Epitaxial Lanthanide Oxide based Gate Dielectrics.
H. Joerg Osten 1 , Arpuba Laha 1 , Andreas Fissel 2 Show Abstract
1 Institute of Electronic Materials and Devices, Leibniz University, Hannover Germany, 2 Information Technology Laboratory, Leibniz University, Hannover Germany
The ability to integrate crystalline metal oxide dielectric layers into silicon structures can open the way for a variety of novel applications which enhances the functionality and flexibility ranging from high-K replacements in future MOS devices to oxide/silicon/oxide heterostructures for nanoelectronic application in quantum-effect devices. We present results for crystalline gadolinium oxides on silicon in the cubic bixbyite structure grown by solid source molecular beam epitaxy (MBE). On Si(100), crystalline Gd2O3 grows usually as (110)-oriented domains, with two orthogonal in-plane orientations. Layers grown under best vacuum conditions often exhibit poor dielectric properties due to the formation of crystalline interfacial silicide inclusions. Additional oxygen supply during growth improves the dielectric properties significantly. Layers grown by an optimized MBE process display a sufficiently high-K value to achieve equivalent oxide thickness values < 1 nm, combined with ultra-low leakage current densities, good reliability, and high electrical breakdown voltage. A variety of MOS capacitors and field effect transistors has been fabricated based on these layers. The intrinsic potential of Gd2O3 is investigated on MOS caps using in vacuo capping of the films with Pt and silicon and subsequent full nickel silicidation. Low thermal budget MOSFET integration of epitaxial Gd2O3 has been achieved with a replacement gate approach with a “gentle” tungsten damascene process.Epitaxial growth of lanthanide oxides on silicon without any interfacial layer has the advantage of enabling defined interfaces engineering. We will show that the electrical properties of epitaxial Gd2O3 thin films on Si substrates can further be improved significantly by an atomic control of interfacial structures. Further, we investigate the effect of post-growth annealing on layer properties. Standard forming gas anneal can eliminate flatband instabilities and hysteresis as well as reduce leakage currents by saturating dangling bond caused by the bonding mismatch. In addition, we investigated the impact of rapid thermal anneals on structural and electrical properties of crystalline Gd2O3 layers grown on Si.Efficient manipulation of Si(001) 4° miscut substrate surfaces can lead to two different microstructures of epitaxially grown Gd2O3 layers. Preparation of a surface with terraces of biatomic steps height is the key point to achieve single domain epitaxial Gd2O3 layer. Such epi-Gd2O3 layers exhibited significant lower leakage currents compared to the commonly obtained epitaxial layers with two orthogonal domains. For capacitance equivalent thicknesses below 1 nm, this differences disappear, indicating that for ultrathin layers direct tunneling becomes dominating. However, after a forming gas annealing, the electrical properties of both single and double domain layers became comparable to each others accompanied by few orders of magnitude reduction in leakage current.
9:30 AM - C1.2
Optimization of La- doped HfO2 by Atomic Layer Deposition.
Paul Jamison 1 , Hemanth Jagannathan 1 , Lisa Edge 1 , Ryosuke Iijima 3 , Robert Clark 4 , Steven Consiglio 4 , Cory Wajda 4 , Gert Leusink 4 , Vamsi Paruchuri 1 , Vijay Narayanan 2 Show Abstract
1 , IBM @ Albany Nanotech, Albany, New York, United States, 3 , Toshiba America Electronic Components, Inc. @ T.J. Watson Research Center, Yorktown Heights, New York, United States, 4 , TEL Technology Center, America, Albany, New York, United States, 2 , IBM Research Division, T.J. Watson Research Center, Yorktown Heights, New York, United States
High-k dielectrics such as HfO2 are being used to replace SiO2 as the gate dielectric in CMOS transistors to enable continued channel length scaling and to reduce power consumption. Obtaining suitable threshold voltages for CMOS in high-k device remains a challenge to be overcome. The use of cap layers to dope the dielectric layer has been shown to be a simple technique to enable tuning of the threshold voltage1. Group II-A and III-B elements such as La, Mg, Ba have been reported to provide shifts towards the nFET band edge1. In this work we focus on optimizing the incorporation of La2O3 into HfO2 by atomic layer deposition (ALD). By in-situ doping of La2O3 into HfO2 using ALD, we are able to precisely vary both position and amount of La in the dielectric layer. ALD films were grown using TEMAH and La(THD)3 tetraglyme adduct as Hf and La precursors. Either water or ozone was used as the oxidant. We observe modulation of the electrical characteristics of nMOS devices by both the variation of the concentration and position of La2O3 within the HfO2 layer, and the choice of oxidants. We find that we are able to modulate the threshold voltage (Vt) toward nFET band edge (negative Vt shift) as the La2O3 layer is shifted from a cap on top of the HfO2 to the bottom interface between the HfO2 and the interfacial SiO2. This observation further confirms dipole formation to be the origin of Vt shift due to the presence of La at the SiO2 interface layer below the HfO22,3. We observe a reduction in gate leakage by increasing the proximity of La to the SiO2 interfacial layer. However, the water based process results in devices with thinner Tinv compared to the ozone based process. To investigate the impact of the oxidant on the scalability of the gate stack, devices were fabricated by depositing a single ALD cycle of La2O3 with each type of oxidant along with samples that had no oxidant prior to deposition of the HfO2 layer. The devices with ozone oxidation during La2O3 deposition were found to have significantly higher Tinv compared to other devices in which the La precursor was un-oxidized or oxidized with water. However the use of water as the oxidant results in a lower overall Vt shift compared to ozone. We have performed detailed investigation in the dependencies of position and incorporation of La in HfO2 and have highlighted these as important parameters to be considered during the optimization of device characteristics. The water process is best for Tinv scaling, but the ozone process results in larger Vt shifts and lower leakage,. Additionally, by placing a La2O3 layer at or near the HfO2/SiO2 interface, the largest nFET Vt shifts may be obtained.This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.1. V. Narayanan et al., Symp. VLSI Tech.. p. 224 (2006)2. J.K. Schaeffer et al., INFOS p. 2196 (2007)3. H. Jagannathan et al., ECS Transactions, 16 (5) 19-26 (2008)
9:45 AM - C1.3
Sr and Ti Precursor’s Development for Next Generation Thin Films Applications.
Rajesh Katamreddy 1 , Vincent Omarjee 1 , Benjamin Feist 1 , Christian Dussarrat 1 Show Abstract
1 Delaware Research and Technology Center, Air Liquide Inc, Newark, Delaware, United States
Titanium dioxide is an attractive candidate for several thin films applications, such as high dielectric constant material for electronic devices, antireflection optical coatings, biocompatible coatings, photocatalysis and solar cells. In addition, TiO2 is also a constituent of several important multimetal oxide systems, such as strontium titanates (STO), barium strontium titanates (BST), and lead zirconium titanates (PZT), for dielectric and ferroelectric applications. Regarding strontium oxide, it is an attractive material for incorporation in STO and BST thin films as well as for buffer layer for STO and BST depositions for dielectric applications, or capping layer over Hf-based films for transistor applications.Atomic layer deposition (ALD) is the preferred technique for the growth of uniform and conformal ultrathin titanium based oxide films. Selection of appropriate Ti and Sr precursors plays a critical role in the success of final ALD process. There are several criteria such as the growth rate, the process temperature window range and upper limit, the precursor’s volatility, the adequate chemistry with the desired oxidizer, etc. that are needed to be considered before the selection of the precursor. In addition to the above mentioned criteria, the final selection will be based on the material and electrical properties of the resulting films. Most of the standard homoleptic Ti molecules such as titanium tetrakis(isopropoxide) (TTIP), tetrakis(dimethylamino) titanium (TDMAT), tetrakis(diethylamino) titanium (TDEAT), tetrakis(ethylmethylamino) titanium (TEMAT) have been observed to have limited ALD process temperature window. However, high temperature process is desired to generate high quality TiO2 and STO films. In this work, we study the influence of heteroleptic chemistry (ligand mixing) on the TiO2 ALD temperature window. For example, using a mono cyclopentadienyl ligand substituted titanium methoxide precursor, StarTi, TiO2 ALD was achieved at temperatures up to 400°C. A highly volatile strontium precursor, HyperSr, which has a low melting point, good thermal stability and good reactivity, was used for the ALD of SrO. Higher strontium carbonate formation is observed in the case of O3 chemistry as compared to moisture based chemistry. There is the potential that this carbonate species is inherent to the ALD process; however, it has been reported that SrCO3 forms when SrO films are exposed to atmospheric CO2. To isolate the effects of atmospheric exposure on the carbonate formation in the film, a TiO2 capping layer was generated in-situ on the surface of SrO films deposited by ALD. The resulting capped films were sputter etched and analyzed by photoelectron spectroscopy to analyze the as-deposited SrO films.Finally, compatibility of HyperSr and StarTi in terms of composition tunability and material properties for STO ALD will be discussed.
10:00 AM - C1.4
Highly Conformal ALD LaOx and La-based High-k Dielectric Films Using Novel Vaporizer Technology.
Carl Barelli 1 , H. Kim 1 , Gi Kim 1 , Yoshihide Senzaki 1 , Johannes Lindner 1 , Brian Lu 1 , Zia Karim 1 , Sasangan Ramanathan 1 Show Abstract
1 , AIXTRON, Sunnyvale, California, United States
Lanthanum oxide and lanthanum-based dielectric have been of keen interest for a cap layer or dielectric layer for advanced metal/high-k gate stacks. Conformal thin film deposition of these advanced materials will also be needed as the future transistors require 3-dimensional structures.In this study, highly conformal LaOx and La-based dielectric films were deposited on nonplanar substrates by atomic layer deposition (ALD) using volatile liquid metal-organic sources and our novel vaporization technology. Conformal step coverage of ALD films in high aspect ratio structures require a sufficient precursor vapor to be delivered to the wafer with a short exposure time. In particular, for advanced high k materials, such as LaOx and rare earth elements, precursors have low vapor pressures (below 0.01 Torr at 100°C), which makes the precursor delivery into the reactor challenging. Our vaporizer technology provides reduction in time to reach saturation for these low volatile liquid precursors. ALD LaOx film growth saturation against injector opening time was evaluated using a single-wafer 300mm ALD reactor with vertical gas injection. Film growth rate saturates typically in times of 60 msec or less. Excellent step coverage of over 90% of ALD LaOx has been achieved in 40:1 aspect ratio structures. Characterization of LaOx and La-based multicomponent dielectric films against process conditions including capacitance-voltage and leakage current-voltage measurements, crystallinity, composition, impurities, film density, film roughness, film conformality will be discussed.For a production-worthy process/system development, chamber design, gas distribution (showehead), and reactor volume optimization are critical to achieve shorter ALD cycle times while maintaining good step coverage and high throughput. Our ALD reactors were placed in a compact configuration with a capability of processing multiple wafers in parallel. For example, a 10,000 wafer marathon of ALD ZrO2 obtained by the parallel single-wafer processing mode combined with the vaporizer achieved average within-wafer non-uniformity of 1.3% (1σ) and wafer-to-wafer non-uniformity of 1.4% (1σ) with average particle adders of 59 above 0.1μm in diameter. These results exhibit highly reproducible and high productivity capabilities of the ALD systems for high-k film deposition.
10:15 AM - C1.5
Interaction of Hf Precursor with H2O-terminated Si(100): First Principles Study.
Dae-Hyun Kim 1 , Dae-Hee Kim 1 , Hwa-Il Seo 2 , Yeong-Cheol Kim 1 Show Abstract
1 Department of Materials Engineering, Korea University of Technology and Education, Chonan Korea (the Republic of), 2 School of Information Technology, Korea University of Technology and Education, Chonan Korea (the Republic of)
We have performed a first principles density functional theory study to investigate the reaction of the HfCl4 molecules on H2O terminated Si(100)-(2×1) surface that is the initial stage of atomic layer deposition(ALD). The Si(100) surface reconstructs by forming dimers which are buckled at low temperature. H2O molecules are attached to down-buckled Si atoms below dissociation temperature and are dissociated into H’s and OH’s above dissociation temperature. This process can make a Si(100) substrate which is regularly covered with H’s and OH’s. The reaction of the HfCl4 molecule is more favorable on OH-terminated site than H-terminated site. When the HfCl4 molecule is adsorbed on OH-terminated site, an HCl molecule is generated and the remaining HfCl3 bonds to the O atom. The first HfCl4 molecule is adsorbed on the OH-terminated site with 0.21 eV energy benefit. The second HfCl4 molecule is adsorbed on the most adjacent OH-terminated site of the first molecule and the energy benefit is 0.28 eV. The third and forth molecules have same tendency with the first and second ones. The adsorption energies of the fifth and sixth HfCl4 molecules are 0.01 eV, -0.06 eV respectively. Therefore, we find that the saturation Hf coverage is approximately 4/8 of the available OH sites, which is 1.67 × 1014/cm2. The result is well matched with an experimental study by B. G. Willis et al.
10:30 AM - C1.6
Terbium Scandate as a Higher-k Dielectric.
Martin Roeckerath 1 2 , Marcelo Lopes 1 2 , Eylem Durgun Oezben 1 2 , Yunfa Jia 3 , Juergen Schubert 1 2 , Siegfried Mantl 1 2 , Darrell Schlom 3 Show Abstract
1 Institute of Bio- and Nanosystems IBN1-IT, Research Centre Juelich, Juelich Germany, 2 , JARA – Fundamentals of Future Information Technologies, Juelich Germany, 3 Department of Materials Science and Engineering, The Pennsylvania State University, University Park, Pennsylvania, United States
Since the first hafnium based high-k dielectric was introduced in large-scale industrial production of integrated circuits, research has concentrated on materials with even higher dielectric constants for the next generation of microelectronics. These so-called higher-k dielectrics should have k-values above 26 and a bandgap larger than 5 eV to fulfill the requirements for future technology generations (Lee et al., Trans. Electron Devices 55, 8 (2008)). Rare earth scandates are a promising class of materials as alternative higher-k gate dielectrics for future CMOS applications since they exhibit promising morphological and electrical properties (D. G. Schlom et. al., MRS Bull. 27, 198 (2002)) and some of them reach k-values exceeding 25 (H.M. Christen et al., Appl. Phys. Lett. 88, 262906 (2006)). In this work terbium scandate (TbScO3) thin films with thicknesses ranging from 6 to 80 nm were deposited on Si (100) substrates in high vacuum conditions from a stoichiometric ceramic target in a conventional electron beam evaporation system (Leybold Univex 450). The as deposited films were found to be amorphous according to XRD measurements. After deposition of platinum top contacts through a shadow mask and Al backside contact formation the resulting MOS capacitors were electrically characterized with an impedance analyzer (HP 4192A). The C-V curves show no irregularities and exhibit a hysteresis below 50 mV. Interface state densities in the lower 1011 (eVcm2)-1-range were determined using Termans’ method. A k-value for the TbScO3 of 26 was extracted from an EOT plot.In addition to the capacitors, long channel n-metal-oxide-semiconductor field-effect transistors (nMOSFETs) on thin SOI (30 nm) have been prepared in a gate last process with a ~6 nm thick TbScO3 gate dielectric. The samples were annealed in oxygen after terbium scandate deposition to compensate for a possible lack of oxygen in the film. Readily fabricated devices were electrically characterized by DC-measurements using an HP 4155B semiconductor parameter analyzer. The measurements revealed well behaved IV-output and transfer characteristics. For devices with different gate lengths an evaluation with the Id/sqrt(gm)-method resulted in an electron mobility of ~225 cm2/Vs.
10:45 AM - C1.7
The Role of Strontium in Oxide Epitaxy on Silicon (001).
James Reiner 1 , Kevin Garrity 2 , Fred Walker 1 , Sohrab Ismail-Beigi 1 2 , Charles Ahn 1 2 Show Abstract
1 Applied Physics, Yale University, New Haven, Connecticut, United States, 2 Physics, Yale University, Berkeley, California, United States
The ability to grow crystalline SrTiO3 on the silicon (001) surface, developed in the last decade, enables the integration of crystalline oxides and semiconductors for both technological applications and fundamental scientific inquiries. This promise is related to the wide range of behavior exhibited by crystalline oxides, including magnetism, ferroelectricity, superconductivity, and colossal magnetoresistance. The most successful approach to realizing these epitaxial oxide-silicon (001) heterostructures requires manipulating substrate temperature and oxygen pressure on a layer by layer basis during the deposition of the metal-oxide layers. The transition layer between the semiconductor and crystalline oxide is an alkaline earth metal, most often strontium, that is deposited on the silicon surface at around 650°C. This strontium sub-monolayer forms ordered surface structures that have been extensively studied, both experimentally and theoretically. Despite this attention, inconsistencies remain between experimental results and theoretical predictions for this surface structure . Motivated by a desire to resolve these questions and develop a fundamental understanding of this important transition layer between silicon and oxide, we have studied the surface structures formed by strontium on miscut silicon wafers, which, unlike the regular silicon wafers, have a unique surface termination. These experiments avoid ambiguities in surface symmetry and reveal an unexpected reaction of strontium with the silicon surface. At high temperatures, this reaction rearranges the top layer of silicon to replace the original top layer with strontium. At low temperatures, this reaction is suppressed, leading to a different, but symmetry related, surface structure. Although all previous approaches to oxide epitaxy on silicon have required high temperature, we find that crystalline oxides can be grown on a clean silicon surface without the need to heat the wafer above 100°C.
11:00 AM - C1:Diel1
C3: Electrodes for Advanced Gate Stacks
Tuesday PM, April 14, 2009
Room 2006 (Moscone West)
2:30 PM - **C3.1
Understanding Work Function Control for Metal Gate / high K Oxide Gate Stacks.
John Robertson 1 Show Abstract
1 , Cambridge University, Cambridge United Kingdom
The talk will review the experimental methods and our mechanistic understanding of how to control the effective work function (EWF) of metal gates on HfO2 based gate stacks. The experimental problem is called Fermi level pinning and Vt roll-off, which was first found for poly-Si gates and later found for metal gates . It begins with the metal induced gap state (MIGS) model of Schottky barrier heights , which gives the intrinsic EWF value. However, it turns out that this model is too simple and full theoretical calculations show it over-estimates the degree of pinning . The pinning is recognised to be extrinsic, because it depends on temperature and can be reversibly shifted . This led to models based on oxygen vacancies, and more generally on defects in the oxide, whose behaviour must be controlled to remove their effect, especially for noble metals and pFETs . The third step is to recognise the strange role of some oxides (La, Al) of introducing dipole shifts. This ‘problem’ is reversed and used to create dipole layers to shift EWFs and threshold voltages in the desired direction. A functional understanding of this is known . But a full atomic scale understanding is now only just being found.1 C Hobbs et al, Tech Digest VLSI (2003); IEEE Trans ED 51 971 (2004)2 J Robertson, J Vac Sci Technol B 18 1785 (2000)3 K Tse, J Robertson, Phys Rev Lett 99 086805 (2007)4 E Cartier et al, VLSI (2005) p15; IEDM (2006)5 Y Akasaka et al, Jpn J App Phys 45 L1289 (2006)6 A Toriumi et al, IEDM (2007)
3:00 PM - C3.2
Exploration of the Ta(C,N)x/HfO2 Advanced Gate Stack Using Combinatorial Methodology
Kao-Shuo Chang 1 2 , Martin Green 1 , Hilary Lane 2 , Peter Schenck 1 , Jason Hattrick-Simpers 1 , Ichiro Takeuchi 2 , Cherno Jaye 3 , Daniel Fischer 1 , Stefan De Gendt 4 Show Abstract
1 Materials Science and Engineering, NIST, Gaithersburg, Maryland, United States, 2 Department of Materials Science & Engineering, U. of Maryland, College Park, Maryland, United States, 3 National Synchrotron Light Source, Brookhaven National Laboratory, Upton, New York, United States, 4 , IMEC, Leuven Belgium
Traditional materials used in the metal-oxide-semiconductor (MOS) gate stack (SiO2 dielectrics, and poly-Si metal gate) have been pushed to their fundamental limits due to aggressive scaling. HfO2, among others, has been identified as a promising dielectric layer to replace SiO2. However, the selection of appropriate metal gates on top of HfO2 is not yet settled, in terms of interfacial stability and suitable electrical properties.Ta(C,N)x is an encouraging metal gate due to its low resistivity, high thermal stability, chemical inertness, and work function (Φm) tunability. However, the study of a wide composition range of Ta(C,N)x based on a traditional one-composition-at-a-time strategy is too time consuming. Combinatorial methodologies enable efficient generation of a comprehensive and uniform set of samples (in “libraries”), and allows rapid screening as well. The goal of this research is to rapidly map the physical and electrical properties of Ta(C,N)x as a function of composition, through the deposition of composition spread libraries.Using reactive sputtering, we have obtained a wide composition variation in C and N content, as evidenced by near-edge x-ray absorption fine structure spectroscopy (NEXAFS). A scanning x-ray microdiffractometer was used to determine the microstructures in the film; a solid solution of Ta(C,N)x was suggested. X-ray photoemission spectroscopy (XPS) was used to study the Ta(C,N)x/HfO2 and HfO2/SiO2 interfaces. A semi-automatic probe station was used to measure capacitance-voltage (C-V) characteristics from hundreds of MOS capacitors. A standard program was used to fit C-V characteristics to extract equivalent oxide thickness (EOT) and flat band voltage (Vfb), which allows for the systematic extraction of Φm. Φm of Ta(C,N)x was found to range from 4.6 eV to 4.8 eV after a forming gas anneal (FGA). Thermal stability was also investigated through rapid thermal anneals (RTA) up to 1000 °C. We found that Φm of Ta(C,N)x can be tuned up to 5 eV after a 900 °C RTA, suggesting it may be a promising p-type gate metal for the CMOS applications.
3:15 PM - C3.3
The Effect Of Heat Treatments And Enviroment On The Dipole Formation At Metal/High-Κ Dielectric Interface Studied By XPS.
Andrei Zenkevich 1 , Yuri Lebedinskii 1 , Yuri Matveyev 1 , Vladimir Tronin 2 Show Abstract
1 Solid state physics and Nanosystems, Moscow Engineering Physics Institute (state university), Moscow Russian Federation, 2 Molecular Physics, Moscow Engineering Physics Institute (state university), Moscow Russian Federation
In the selection of metal gate materials for advanced CMOS applications, an assumption that the work function of a metal on a gate dielectric is the same as that in vacuum has been experimentally observed to be incorrect. The reason is the dipole formed at the interface which drives band alignment so that the effective work function (WF) of metal in contact with dielectric differs from vacuum WF values. The dipole depends on chemical reactions and/or defects at the interface which can result from heat treatments in different environments.For the particular case of p-channel field-effect transistor (p-FET) with HfO2 gate dielectric it was found that metals with high WF deposited at room temperature had no or small dipole formed at the interface (weakly pinned Fermi level, EF). However, these metals show an instability when annealed above T=500C in oxygen-deficient conditions, and their EF moves toward midgap presumably due to oxygen vacancies generated in HfO2, the latter suggestion confirmed by recent calculations . In this work, we present the modified version of x-ray photoelectron spectroscopy (XPS) based method  to measure the changes of electrical dipole built up at the metal/dielectric interface (effective WF) following different treatments of the structure. The method is based on the deposition of an ultrathin (1–5 nm) discontinuous metal layer on high-k dielectric surface by Pulsed Laser Deposition and in situ measurement by XPS of the dielectric core level lines shifts with respect to metal ones following the formation of electrical dipole at the metal/high-k dielectric interface. Theoretical modeling confirmed the dipole formed by the array of metallic nanoclusters (ncs) on dielectric surface at our experimental conditions is equivalent to the continuous metal layer. Therefore, an open dielectric surface between the metallic ncs makes the nc-metal/high-k dielectric/Si stack sensitive to different treatments as observed XPS line shifts. The developed method was tested on Au/HfO2 system. It was found that the vacuum annealing of as grown nc-Au/HfO2 interface results in the build-up of the interface dipole of U=+0.5 V driving metal EF towards Si midgap. On the contrary, the annealing of nc-Au/HfO2/Si stack in O2 (P~10-2 Torr) atmosphere as well as its exposure to the atmospheric air results in the dipole formation U= –0.2 V with respect to as grown value. It is worth noting that the cyclic treatment results in the cyclic changes in interface dipole. For Ni/HfO2 system, the similar experiments reveal U=0.25 V dipole formation for UHV annealing in comparison to U= –0.2 V following exposure in atmospheric air. These values are in general agreement with those obtained from C-V measurements performed ex situ on the same material system.The experiments are under way on more relevant material systems, particularly, on TaN/LaAlO3. 1. J. Robertson et al., APL 91 132912 (2007). 2. Yu. Lebedinskii et al. JAP 101 074504 (2007).
3:30 PM - C3.4
Variability of Metal Grain Orientation and the Effects on Electrical Characteristics of Nanoscale MOSFETs
Xiao Zhang 1 , Melody Grubbs 2 , Michael Deal 1 , Bruce Clemens 2 , Yoshio Nishi 1 Show Abstract
1 Electrical Engineering, Stanford University, Stanford, California, United States, 2 Materials Science and Engineering, Stanford University, Stanford, California, United States
Metal gates have been introduced in the 45 nm technology node for VLSI devices. Variability issues related to line edge roughness (LER), random dopant variation, and high-k surface morphology have been addressed before. However, for nanoscale MOSFETs, the effects of variability of the work function due to different orientations of the metal grains on their electrical characteristics have not been systematically evaluated. First the variability of metal grain orientation deposited on dielectrics was experimentally demonstrated by sputtering 11 nm thin tungsten films on thermal SiO2. X-Ray Diffraction (XRD), selective area electron diffraction (SAP) and convergent beam electron diffraction (CBED) were used to obtain orientations of different grains of this W film. W grain orientations of (110), (100), (111), (211) and (321) were found and the statistics on the percentage of number of grains with different orientations was extracted.For this W film and as well as other types of metal gates, a generic device model was constructed to determine the effects in device characteristics due to work function variability of different grain orientations. The input parameters to this model are: the work function variation among different grains, average grain size, gate length and width. Statistics of electrical characteristics such as threshold voltage (Vth) and sub-threshold slope (SS) are obtained for both NMOS and PMOS for a range of the input parameters. For example, by tuning these parameters, we can find that in the worst case, the maximum Vth variability induced by grain work function variability for 45 nm NMOS with 1um gate width is as large as 0.19V. This is about 3 times the Vth variability induced by random dopant variation. However, the simulation shows that the SS is virtually not affected by the work function variability due to different grain orientations. Finally, the scaling effects of these device characteristics were investigated and will be reported.
3:45 PM - C3.5
Chemical and Structural Stability of High-Temperature-Stable Amorphous Ta-W-Si-B Gates on HfO2
Melody Grubbs 1 , Xiao Zhang 2 , Michael Deal 2 , Yoshio Nishi 2 , Bruce Clemens 1 Show Abstract
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Electrical Engineering, Stanford University, Stanford, California, United States
A rising concern with polycrystalline gates is that device variability could become a problem as the gate dimensions become comparable to the grain size. A reason for this concern is illustrated by work from C. Fall, et al. which shows that the tungsten work function ranges from 4.44 eV to 5.26 eV depending on the crystallographic orientation of the grain. Amorphous metal alloy gates are being investigated here in order to determine whether workfunction variability can be reduced in nano-scale MOS devices if the different grain orientations are eliminated. Also, since integration via gate-first processing is desirable, refractory transition metal-metalloid glasses of the form (TaxW(1-x))80Si10B10 were chosen as the gate materials to be developed in this study. Some metallic glasses with this compositional form have been shown to crystallize well above 1000°C. We deposited Ta-W-Si-B alloys by four-target, dc co-sputtering using W, W2B, Ta, and Si targets. The desired compositions were Ta60W20Si10B10, Ta40W40Si10B10, Ta30W50Si10B10, and Ta20W60Si10B10 although these exact compositions may not have been achieved by sputter deposition using multiple targets. The ratio of tantalum to tungsten was adjusted by varying the power supplied to the W, Ta, and W2B targets. Through x-ray diffraction and capacitance-voltage measurements, we have demonstrated that MOS capacitors made with Ta-W-Si-B alloys are stable and that the gate electrodes remain amorphous on terraced SiO2 after a 5s, 1000°C rapid thermal anneal (RTA). Also, the resistivities of these films are only 2-3 times as high as that of a pure tungsten gate electrode. Additionally, the effective work functions (EWFs) of these alloys on SiO2 range from 3.95 – 4.32 eV after the RTA, with higher Ta concentration films having the lower work functions. The stability and performance of these alloys on thin high-k dielectrics will also be discussed. In particular, we will report on gate-last compatibility, and on whether these alloys are stable and remain amorphous after a 1000°C activation anneal for gate-first applications on HfO2. Additionally, we will report on the effective work functions and their tunability, and whether any Fermi level pinning occurs when Ta-W-Si-B alloys are integrated with thin gate oxides. Backside SIMS will also be employed in order to determine whether or not there is any boron penetration into the channel. . C. J. Fall, et al. Theoretical Maps of Work-Function Anisotropies. The American Physical Society. Physical Review B, Volume 65 (2001) 045401-1 – 045401-6. T. Yoshitake, et al. Preparation of Refractory Transition Metal-Metalloid Amorphous Alloys and Their Thermal Stability. Materials Science and Engineering, 97 (1988) 269-271
4:00 PM - C3: Electrodes
Bill Taylor Sematech, Inc.
Rusty Harris Texas A&M University
Jeff Butterbaugh FSI International
Alex Demkov University of Texas-Austin
Willy Rachmady Intel Corporation
C7: Devices III: Dielectric Engineering
Wednesday PM, April 15, 2009
Room 2006 (Moscone West)
2:30 PM - **C7.1
High-k/Metal Gate Device and Integration Challenges.
Michael Hargrove 1 Show Abstract
1 , AMD, Hopewell Junction, New York, United States
High-k/metal gate is the catalyst required for gate length scaling and continued power-performance optimization in 32 nm CMOS technology and beyond. The physically thicker high-k gate dielectric results in lower gate leakage current compared to Poly-Si/SiO2 gate stack. The metal gate eliminates gate poly depletion resulting in thinner equivalent electrical oxide thickness (Tinv) which enhances gate control of the channel resulting in improved electrostatics and maximized current drive. Overall circuit level performance improvement is determined by the aforementioned attributes in addition to careful gate stack optimization to achieve band edge work function for both NFET and PFET devices. Achieving band edge work function requires the proper choice of gate metal in conjunction with the proper choice of metal/metal oxide capping layer material and thickness. The integration of these layers with a well controlled interface layer and optimized anneal cycles determine the final overall device performance and reliability. This paper reviews the process integration and device tradeoffs required to achieve optimal CMOS performance in a high-k/metal gate technology. The attributes of both a gate-first and gate-last approach will be reviewed, with careful attention paid to the process complexity and scaling limitations of each. The device variability components of each approach will also be reviewed. Ultimately, this paper hopes to carefully elucidate the merits and complexity of high-k/metal gate technology with respect to process integration and device performance.
3:00 PM - C7.2
Molecular Dynamics Simulations of Strained HfO2
Travis Kemper 1 , Susan Sinnott 1 , Simon Phillpot 1 Show Abstract
1 , University of Florida, Gainesville, Florida, United States
Considering the application of compressive and tensile strain to increase hole and electron mobility in the channel regions of metal oxide semiconductor (MOS) devices; the effects of strain on the high-κ dielectric material HfO2 was elucidated by means of a molecular dynamics simulation. An empirical potential was developed based on density functional calculations to model the structural and dielectric properties of the cubic and tetragonal phases of HfO2. Positive and negative uniaxial and biaxial stresses were applied to pure, effectively doped, and defective HfO2 systems at various temperatures in order to elucidate these systems dielectric dependence on stress and temperature. Defects included point defects as well as dislocations. Exponential increases in relative permittivity where found to for both compressive and tensile stresses. We acknowledge the support of the National Science Foundation through grant number DMR-0426870.
3:15 PM - C7.3
Role of Arsenic-defect Complexes During Arsenic Uphill Diffusion.
Ning Kong 1 , Taras Kirichenko 2 , Gyeong Hwang 3 , Sanjay Banerjee 1 Show Abstract
1 Electrical and computer Engineering, University of Texas at Austin, Austin, Texas, United States, 2 , Freescale Semiconductor Inc. , Austin, Texas, United States, 3 Department of Chemical Engineering, University of Texas at Austin , Austin, Texas, United States
As the size of Si transistors shrinks to sub-40nm region, the doping issue in the ultra shallow junction area becomes more and more important for device performance. High levels of dopant concentration and activation in shallow junctions are often required to alleviate short channel effects. However, challenges can be posed by a recently identified arsenic uphill diffusion effect.1-3 The uphill diffusion refers to the phenomenon that As has a tendency to pileup in the first few monolayers in proximity of the Si/SiO2 interface during post-implant annealing. The understanding of this phenomenon becomes imperative in that the pileup portion of the dopant profile may contribute a significant part to the non-activated part of the extension junction, which has shrunk to sub-15 nm range as the transistor scales down. This phenomenon is recently addressed by several experimental papers. However, most of the studies have focused more on the characterization of the As profiles and trapped doses in the interface region than the investigation of mechanisms. There are few detailed, atomistic-level theoretical studies for an uphill diffusion mechanism. In this work, we seek to identify the arsenic-defect complex structures, dynamics and their activation properties at the Si/SiO2 interface. Based on this structural/dynamics understanding, physical models are constructed and implemented in a kinetic Monte Carlo (KMC) simulator to reveal the kinetics of As uphill diffusion. In this talk, we will first present our density functional theory calculation results of the arsenic-defect complexes at the Si/a-SiO2 interface. First, As cluster configurations found in bulk Si are excluded from uphill species of the interface due to negligible energy gains. Then, we will show that Asi and As2I2 have very stable configurations at the Si/SiO2 interface, with energy gain 1.7eV and 0.9eV, compared with their structures in bulk Si, respectively. They are the most likely As pileup species during uphill diffusion. The interface Asi structure is even more stable than interface interstitials so that it may retard the interstitial out-diffusion into SiO2. On the other hand, AsV is not stable at the interface. We also studied the migration/annihilation behavior of these arsenic-defect complexes near Si/SiO2 interfaces. The stabilization of Asi and As2I2, as well as their activation properties, are analyzed based on electron density and electron localization function topologies. Finally we implemented the arsenic-defect complex model into KMC simulator for verification with experimental data. Using KMC simulation, we further revealed the kinetics of arsenic uphill diffusion. Reference: M. Ferri, et al. Journal of Applied Physics 99, 113508 (2006) C. Steen, et al. Journal of Applied Physics 104, 023518 (2008) A. Parisini, et al. Applied Physics Letters 92, 261907 (2008)
3:30 PM - C7.4
Nb2O5 High-k Dielectric Thin Films for Gigabit DRAM Capacitor Technology.
Masaki Yamato 1 , Hikaru Hara 1 , Takamaro Kikkawa 1 Show Abstract
1 , Hiroshima Univ., Higashi-hiroshima Japan
For future Gigabit DRAM capacitor application, it is necessary to reduce capacitor cell area and increase its dielectric constant. The physical thickness can not be reduced less than 7 nm due to the increase of leakage current. The requirements of DRAM capacitors are higher dielectric constant k > 30, larger energy band gap Eg > 3.5 eV, lower leakage current density j < 10-8 A/cm2 and lower equivalent oxide thickness (EOT) < 0.8 nm. It has been reported that Nb2O5 has large dielectric constant (k=60) but the leakage current was large due to the small energy band gap (Eg=3.3 eV). In this study, we investigated the Nb2O5 films The leakage current property was improved by long time annealing. Nb2O5 thin films were deposited on a platinum electrode on an oxidized silicon (100) substrate by RF magnetron sputtering. The sputtering power was 50 W, sputtering gas pressure was 2.5 Pa (Ar / O2 = 35 / 35 sccm), and substrate temperature was 300-450 °C. The films are annealed in a furnace at the temperature ranging from 500 to 800 °C in O2 ambient for 10 min. As deposited Nb2O5 film was crystallized at substrate temperature of 350°C. Crystallized Nb2O5 film oriented to (001) and (002) having hexagonal structure. By using XPS energy loss spectra, the energy band gap of Nb2O5 film was determined as 3.2 eV. The energy band gap was constant for various film thicknesses from 2.1 to 21 nm. The optical band gap was determined by using spectroscopic ellipsometry and Tauz-Lorentz equation as 3.4 eV. The optical band gap was also determined by indirect model of band-to-band transition as 3.4 eV. The influence of film thickness on the Nb 3d peak position which was calibrated by Pt 4f peak position measured by using XPS was investigated. The Nb 3d peak having 1.2 nm film thickness shifted to lower energy side. Thus, the positive charge exists at the Nb2O5/Pt interface. The Pt 4f peak of as deposited Nb2O5/Pt stacked film has an oxidation peak at 76 eV. Giving the chemical shift position, the Pt2O3 was formed at the surface of Pt bottom electrode. On the other hand, the Pt 4f peak of Nb2O5/Pt stacked film annealed at 600 °C for 10 min did not show oxidation peak. The oxidation of Pt bottom electrode occurred during RF plasma of sputtering deposition, but the Nb atom reduced Pt2O3 due to the large ionization potential. The depth profile of elemental ratio of Nb2O5 film was investigated by using take-off-angle of XPS measurement. The ratio of O/Nb was constant at 2.5 for escape depth from 10 nm to 5 nm. The Nb2O5 film shows the dielectric constant larger than 100. The dielectric constant decreased with decreasing film thickness. The electric field at leakage current density of 10-8 A/cm2 was decreased with increasing the film thickness. The electric field at leakage current density of 10-8 A/cm2 was improved 25% by increasing annealing time with an equal dielectric constant maintained.
3:45 PM - C7.5
Impact of Post Deposition Annealing on Characteristics of HfxZr1-xO2.
Dina Triyoso 1 , R. Hedge 1 , R. Gregory 1 , G. Spencer 1 , W. Taylor 1 Show Abstract
1 Technology Solutions Organization, Freescale Semiconductor, Inc., Austin, Texas, United States
Hafnium based high-k dielectrics have recently been implemented by a few companies for 45nm technology node. Most companies, however, have pushed back high-k implementation until 32 nm technology node. For successful implementation at 32 nm and beyond, extending scalability of hafnium based high-k dielectrics is needed. We have recently reported stabilization of tetragonal phase of HfO2 by zirconium addition resulting in improved scalability of hafnium-based dielectrics.1-5 This paper reports the impact of post deposition annealing in various ambients on electrical properties of hafnium zirconate high-k dielectrics. ALD HfxZr1-xO2 films are annealed in a nitrogen and/or ambient at temperatures ranging from 500°C to 1000°C. A significant reduction in equivalent oxide thickness is observed when annealing ambient changed from oxygen to nitrogen. A 1.5Å reduction is EOT is obtained by annealing at 700°C N2 vs. 500°C O2. While EOT is reduced, gate leakage did not increase significantly. A slight decrease in transconductance (Gm) values is observed on devices annealed in nitrogen ambient. For devices annealed in nitrogen, increasing annealing temperature up to 800°C result in further reduction in EOT with a slight increase in leakage. Of all the nitrogen and oxygen annealing conditions studied, the best result is obtained by annealing at 500°C in N2 ambient. At this temperature, lower EOT (1 nm) is achieved without significant increase in Jg, Vt and only a slight decrease in Gm values compared to 500°C O2 annealed devices. In addition to oxidizing anneal, the impact of annealing in a reducing ambient is studied. ALD HfxZr1-xO2 films with varying thickness are annealed in NH3. A significant reduction in CET is observed due to NH3 anneal as long as the HfxZr1-xO2 physical thickness is 15Å or thicker. When the dielectric is very thin, an increase in overall CET is observed due to an increase in interfacial layer. Optimized NH3 anneal on HfxZr1-xO2 results in lower CET, improved PBTI, low sub-threshold swing values, comparable high-field Gm with only a minor degradation in peak Gm compared to control HfxZr1-xO2.Furthermore, the impact of laser annealing vs. RTP annealed HfxZr1-xO2 films are studied. Laser annealing was done at 1275-1325°C on the order of one millisecond and RTP annealing was done at 1000°C for 5s in nitrogen ambient. Laser annealing helped further stabilize tetragonal phase of HfxZr1-xO2 without inducing void formation. Good devices with low leakage, low equivalent oxide thickness (EOT) and high mobility are obtained for laser annealed HfxZr1-xO2. RTP annealed devices are leaky, most likely due to void formation induced by high temperature annealing.
4:00 PM - C7:Device3
C8: Characterization I: Characterization of Advanced Gate Stacks
Wednesday PM, April 15, 2009
Room 2006 (Moscone West)
4:15 PM - *C8.1
Atomic Rearrangement of Substrate Atoms During Four Different Methods of Gate Oxide Deposition on Compound Semiconductors.
Jon Clemens 1 , Jian Shen 1 , Wil Melitz 1 , Darby Winn 1 , Evgueni Chagarov 1 , Tao Song 1 , Andrew Kummel 1 Show Abstract
1 Chemistry/Biochemistry and Materials Science, University of California at San Diego, La Jolla, California, United States
Scanning tunneling microscopy (STM) has been employed to study the atomic surface rearrangements for gate oxide deposition on compound semiconductors using four deposition methods: (a) molecular beam epitaxy (MBE) of a suboxide (SiO, In2O), (b) electron beam evaporation of a refractory oxide (HfO2), (c) oxidation of a metal film (Hf + O2), and (d) atomic layer deposition (ALD) using metal or oxidation-first reactions (Al2O3). Fermi level pinning can be caused by the deposition technique or it can be due to the intrinsic oxide/semiconductor bonding. Even when the oxide/semiconductor interface is thermodynamically stable, the oxide deposition technique can displace substrate atoms because the molecules used in oxide deposition may be more reactive than the stable oxide. Displacement of substrate atoms will almost always create partially filled dangling bonds which can pin the Fermi level.Investigation of multiple oxide/compound semiconductor interfaces along with DFT calculations has enabled some tentative principles to be formulated. (1) Even when no substrate atoms are displaced, Fermi level pinning can occur due to the elimination of substrate surface dimer bonds and the subsequent formation of new, partially-filled dangling bonds (SiO/GaAs(100)-(2×4)). (2) The weakest possible interface between the oxide and semiconductor is favorable for forming an unpinned interface since the oxide will not displace surface atoms and may only weakly perturb the electronic structure of the semiconductor (In2O/InGaAs(100)-(4×2)). (3) Most oxides evaporate incongruently. Therefore, electron beam deposition of an oxide exposes the surface to oxygen. This will readily displace group V atoms to form metal-oxygen bonds, which tend to pin the Fermi level either directly or indirectly. (4) Deposition of a metal film tends to displace group V atoms since the metal atoms bond to group V atoms very strongly. (5) ALD is more promising since OH termination of group III surface atoms is stable and ligated metal atoms have low reactivity, making them less likely to displace substrate atoms. STM was employed to compare the passivation of the In-rich surface of InAs(100)-(4×2) by trimethyl aluminum (TMA) and three possible ALD oxidants: H2O, HOOH (hydrogen peroxide), and (CH3)2CHOH (isopropyl alcohol, IPA). H2O has low reactivity which limits As displacement. Upon heating the H2O-dosed InAs(100)-(4×2) surface to 200° C, ordered OH-terminated structures are observed. HOOH has high reactivity, which tends to result in As displacement at high coverage. (CH3)2CHOH has low reactivity which limits As displacement even at high coverage. Dosing with TMA at 25° C and annealing to 250° C induces TMA decomposition and desorption of the weakly bound reaction products such as ethane or CHX groups. STM imaging after a high TMA dose shows the reacted surface has a conformal adsorbate layer, no metallic islands, and no clear signs of As displacement.
5:00 PM - C8.2
High-k Band Alignment on High-mobility Substrates by Means of X-ray Photoelectron Spectroscopy.
Michele Perego 1 , Gabriele Seguini 1 , Marco Fanciulli 1 2 Show Abstract
1 , Laboratorio Nazionale MDM, CNR-INFM, Agrate Brianza Italy, 2 Dipartimento di Scienza dei Materiali, Università degli studi di Milano Bicocca, Milano Italy
High dielectric constant (k) materials are expected to replace conventional SiO2 gate oxide to continue the scaling down of metal-oxide-semiconductor (MOS) based devices. The replacement of SiO2 with different high-k materials in MOS based devices allows the substitution of Si channel with high-mobility substrates, such as Ge and GaAs. A key issue for the implementation of these materials in high performance devices is the formation of suitable conduction and valence band offsets at the oxide/semiconductor interface. Therefore accurate measurements of the band structure of the high-k/semiconductor heterojunction are required. The determination of the valence band offset (VBO) by X-ray photoelectron spectroscopy (XPS) is commonly performed using the so-called Kraut’s methodology. This methodology has been developed for VBO determination in semiconductor/semiconductor heterojunctions. Although the physical model, which is the basis of this methodology, can be safely extended to dielectric/semiconductor heterojunctions, in these systems a careful evaluation of the experimental results is required. In a recent paper we have shown that differential charging phenomenon originates at the HfO2/GaAs heterojunction during XPS measurements. Photoelectrons emitted from the bulk GaAs are compensated by electrons supplied from the ground connection of the sample holder, while those originated in the ultrathin oxide cannot be fully compensated by electrons from the substrate. As a consequence, precise determination of the VBO requires a proper recalibration of the energy scale in order to remove artifacts induced by the X-ray bombardment. On the contrary very limited differential charging effects have been observed in HfO2/Ge heterojunctions.In this work a detailed analysis of the band alignment between e-beam evaporated amorphous HfO2 films and various semiconductor substrates (Si, Ge, GaAs) is reported. A clear dependence of the binding energy shift on the thickness of the HfO2 film has been identified. The time evolution of this shift indicates that different steady states are reached after prolonged x-ray bombardment depending on the thickness of the HfO2 films and on the semiconductor substrate. The results obtained on different semiconductors are compared in order to identify the mechanism governing the charge accumulation in the different high-k/semiconductor heterojunctions. Finally artifacts induced by differential charging phenomena are quantified and removed by properly recalibrating the energy scale. The accuracy of the recalibration procedure is evaluated by comparison with internal photoemission spectroscopy data..E. Kraut et al., Phys. Rev. B 28, 1965 (1983)..G. Seguini et al., Appl. Phys. Lett. 91, 192902 (2007).J. L. Alay, M. Hirose, J. Appl. Phys. 81, 1606 (1997).M. Perego et al., Mater. Sci. Semicond. Proc. B, in press
5:15 PM - C8.3
Growth and Layer Characterization of SrTiO3 by Atomic Layer Deposition using Sr(tBu3Cp)2 and Ti(OMe)4.
Mihaela Popovici 1 , Sven Van Elshocht 1 , Johan Swerts 2 , Dieter Pierreux 2 , Nicolas Menou 1 , Annelies Delabie 1 , Karl Opsomer 1 , Bert Brijs 1 , Gerrit Faelens 1 , Alexis Franquet 1 , Thierry Conard 1 , Jan Willem Maes 2 , Dirk Wouters 1 , Jorge Kittl 1 Show Abstract
1 , IMEC vzw, Leuven Belgium, 2 , ASM Belgium, Leuven Belgium
Strontium titanate (SrTiO3) is highly attractive as dielectric due to its ultra high-k value for future generation complementary metal oxide semiconductor (CMOS) and dynamic random access memory (DRAM) applications in Metal-Insulator-Metal (MIM) capacitors. In view of the aggressive scaling for CMOS and since 3-D structures with high aspect ratio are envisaged for DRAM to achieve ultra-high storage density, the most suitable technique is atomic layer deposition (ALD), which through its self-limiting growth mechanism ensures conformal coverage. SrTiO3 was deposited from Sr(tBu3Cp)2 and Ti(OMe)4 in an ASM Pulsar® 8300 cross-flow ALD reactor at 250oC using H2O as oxidizing agent. The films were grown on 300 mm silicon (100) substrates. Excellent within wafer non uniformities were obtained and impurity levels, such as carbon, in the STO layers are below XPS detection limit. The ALD pulse sequence for the various strontium titanate (STO) compositions was (Sr(tBu3Cp)2/H2O)a(Ti(OMe)4/H2O)b, where a and b denote the number of deposited Sr and Ti subcycles, respectively. A linear growth was observed for all compositions. Rutherford backscattering (RBS) showed the Sr/(Sr+Ti) content of the layers is well-controlled by the precursor pulse ratio. Based on RBS measurements, the amount of deposited metal per precursor pulse was found to depend on the composition of the layer. Growth of STO thin films was investigated by RBS and TOFSIMS for various starting surfaces including SiO2, HfO2 and TiN. Grazing incidence X-ray diffraction (GIXRD) performed on samples annealed at 600oC indicates that the diffraction lines characteristic to crystalline phase correspond to cubic SrTiO3 with perovskite structure. For Sr - richer STO compositions, the peak positions are shifted to lower angles with incorporation of Sr, which correspond to an expansion of the cubic lattice constant. Density evaluated from X-ray reflectometry (XRR) measurements and refractive index of STO films show a similar trend, the highest values being obtained for the compositions closer to stoichiometric SrTiO3. The electrical performances of strontium titanates with different compositions were investigated via C-V and I-V measurements in MIS (with Pt-top electrode) and MIM (with TiN bottom and Pt top electrode) capacitor stacks. The dielectric constant (extracted from film thickness series) and leakage current strongly depends both on the Sr/(Sr+Ti) content and on the crystalline state of the films. The highest k-values, up to ~ 200, are obtained for crystallized stoichiometric STO films. Therefore careful tuning of the process conditions is required to fulfill the requirements for device applications.
5:30 PM - C8.4
Dielectric Tensor of Single Crystals of the Alternative Gate Oxide Candidate LaLuO3.
Tassilo Heeg 1 2 , Klaus Wiedenmann 3 , Martin Roeckerath 4 , Darrell Schlom 1 2 Show Abstract
1 Materials Science and Engineering, Penn State University, University Park, Pennsylvania, United States, 2 Department of Materials Science and Engineering, Cornell University, Ithaca, New York, United States, 3 Experimentalphysik VI, Elektronische Korrelationen und Magnetismus, Institut für Physik, Universität Augsburg, Augsburg Germany, 4 Institute of Bio- and Nanosystems IBN1-IT, and JARA-FIT, Research Centre Jülich, Jülich Germany
In the ongoing search for Si-compatible high- and higher-K dielectrics, LaLuO3 is being studied as a possible candidate material [1,2,3] because of its predicted stability in contact with silicon , high optical bandgap (5.6 eV) , and its high, but not fully established K value . These existing studies on amorphous and crystalline thin films of LaLuO3 have observed a significant variation in the dielectric constant of LaLuO3, ranging from 17 to 45. To put these values into context and to distinguish between intrinsic material properties and the influence of the specific thin film fabrication route, we have investigated the dielectric properties of bulk LaLuO3.
Single crystals of the congruently melting composition, La0.94Lu1.06O3, were grown using the floating-zone technique. Subsequently, slices were cut from these crystals. Since the crystals were rather small (around 5 mm diameter) and heavily cracked, the slices were cut in such orientation that the slices were free of cracks and as big as possible, generally resulting in a random crystallographic orientation. Laue- and four-circle x-ray diffraction were employed to determine the orientation of each piece to enable the full dielectric constant tensor (Kij) of LaLuO3 to be established. Pt electrodes were deposited onto the slices to form parallel plate capacitors and K of each slice was determined using an HP4284A precision LCR meter. Due to the orthorhombic symmetry of La0.94Lu1.06O3 (Pbnm, #62), its dielectric tensor has three non-zero components. Using a least-square fitting approach, these components were determined from the measured values. Kij of LaLuO3 varies as a function of direction from a minimum of 25±3 to a maximum of 51±3, making LaLuO3 the highest K alternative gate dielectric material known that is Si-compatible with high bandgap.
 J.M.J. Lopes, M. Roeckerath, T. Heeg, E. Rije, J. Schubert, S. Mantl, V.V. Afanas'ev, S. Shamuilia, A. Stesmans, Y. Jia, D.G. Schlom, Appl. Phys. Lett. 89, 222902 (2006).
 J.M.J. Lopes, M. Roeckerath, T. Heeg, J. Schubert, S. Mantl, Y. Jia, D.G. Schlom, Microel. Eng. 84, 1890 (2007).
 J. Schubert, O. Trithaveesak, W. Zander, M. Roeckerath, T. Heeg, H.Y. Chen, C.L. Jia, P. Meuffels, Y. Jia, D.G. Schlom, Appl. Phys. A 90, 577 (2008).
 D.G. Schlom, J.H. Haeni, MRS Bull. 27, 198 (2002).
 K.L. Ovanesyan, A.G. Petrosyan, G.O. Shirinyan, C. Pedrini, L. Zhang, Opt. Mater. 10, 291 (1998).
5:45 PM - C8.5
Structural and Chemical Studies using XPD and Synchrotron Radiation Photoemission of Epitaxial γ-Al2O3 Thin Films Grown on Si(111) and Si(001).
Mario El Kazzi 1 3 , Clement Merckling 2 3 , Genevieve Grenet 3 , Guillaume Saint-Girons 3 , Mathieu Silly 1 , Fausto Sirroti 1 , Guy Hollinger 3 Show Abstract
1 , Synchrotron SOLEIL, L'orme des Merisiers, 91192 Gif-sur-Yvette France, 3 , INL (UMR 5270), Ecole centrale de Lyon, 69134 Ecully France, 2 , IMEC, Kapeldreef 75, B-3001 Leuven Belgium
Nowadays, growing well-crystallised oxide thin films on silicon is the subject of intense activity due to numerous promising applications in nanotechnologies. Among these oxides, Al2O3 is very interesting and promising for interface engineering on silicon. Al2O3 is stable on silicon for temperatures and oxygen pressures up to 850°C and 10-5 Torr, respectively. If combined with some high-κ oxides, it could provide an interesting way to reach small equivalent oxide thickness (EOT) in CMOS devices. However, the interest of studying and controlling the growth of alumina on silicon goes far beyond because it could be part of complex oxide/semiconductor heterostructures and as a result, open the way to the integration of high performance micro-optoelectronic functionalities on Si wafers.In this context, we grew γ-Al2O3 thin films on either Si(111) or Si(001) substrates by molecular beam epitaxy (MBE). Our previous studies using reflection high-energy electron diffraction (RHEED), X-ray photoelectron spectroscopy (XPS), Transmission Electronic Microscopy (TEM), and X-ray Diffraction (XRD) have shown the following. The growth of γ-Al2O3 films on Si(111) substrates is along the  direction, as expected. In contrast, for Si(001), only the two first monolayers are (001) oriented, while for larger thicknesses, a growth transition occurs with the growth direction changing from  to . In both cases the interface is abrupt without formation of SiO2 or Al silicate. (J. of Appl. Phys. 102, 024101 (2007)), (Appl. Phys. Lett. 89, 232907 (2006))In this work, we present new results on the microscopic description of the γ-Al2O3/Si system.First, using X-ray photoelectron diffraction (XPD), azimuthal curves for Al2p, O1s, and Si2p photoelectrons show that, on Si(111), two in-plane Al2O3(111) orientations exist : a "direct" one i.e. [-1-12]Al2O3(111)//[-1-12]Si(111) and a "mirror" [-1-12]Al2O3(111)//[11-2]Si(111), with the presence of slight in-plane misorientation of Al2O3 with respect to Si. These behaviours can be explained by the bonding between Al2O3 (111) and Si(111) via an O-plane.Surprisely, for Si(001), azimutal curves, recorded on oxide layers with thickness of 0.4 nm, 0.6 nm, 0.8 nm, 1 nm and 3 nm, do not shown any (001) oriented Al2O3 layers in contrast to previous RHEED and TEM observations. The Al atomic local order is the same for all thicknesses and corresponds to an Al2O3 oriented  out of plane, while in plane 4 orientations exist. A microscopic model is presented to reconciliate XPD, TEM and RHEED data.Second, synchrotron radiation (from SOLEIL) photoemission measurements were combined with X-ray absorption at the Si, Al and O -K edges to study the Al2O3 interfaces with Si(111) or Si(001). Results show that two different kinds of connection via the oxygen sub-lattice can exist between Al2O3 and Si.
Bill Taylor Sematech, Inc.
Rusty Harris Texas A&M University
Jeff Butterbaugh FSI International
Alex Demkov University of Texas-Austin
Willy Rachmady Intel Corporation
C10: Interface II: III-V Substrates
Thursday AM, April 16, 2009
Room 2006 (Moscone West)
9:00 AM - **C10.1
Interface Formation Mechanisms for high-k Layers Deposited on III-V Substrates.
Anthony Muscat 1 , Fee Li Lie 1 , Babak Imangholi 1 Show Abstract
1 Department of Chemical and Environmental Engineering, University of Arizona, Tucson, Arizona, United States
Many III-V compound semiconductors have higher electron mobilities than either Si or Ge and direct band gaps. These properties could enable the fabrication of low power, high-speed n-channel metal oxide semiconductor field effect transistors (MOSFETs) and optoelectronics combining MOS technology with photonics. A key to incorporating these materials into advanced devices is the development of processing steps that form stable interfaces with dielectric layers. Understanding the reaction mechanisms of these processes could provide the means of controlling composition and structure, yielding a desired electronic behavior. Recent studies in the literature link the reaction mechanism for interface formation to surface composition and ALD precursor when oxides are deposited on III-V substrates. In particular, interface reactions occur in which the ALD precursor removes surface oxides. These reactions have been explained by the relative bond strength of surface and precursor metal atoms with O as well as structural similarities between reactants and products. This study investigated the formation of high-k/III-V interfaces after ALD of Al2O3 on InGaAs and InAlAs(100) cleaned using HF chemistries. The deposition was conducted at 170°C utilizing TMA and water, yielding growth rates of ∼1.1 Å/cycle. A 10-15 Å thick Al2O3 layer was deposited after either liquid or gas phase surface preparation as well as on native oxide covered samples. A 10-15 Å layer was thick enough to support surface reactions during ALD, but thin enough to probe the Al2O3/III-V interface by XPS. After gas phase HF etching of InGaAs, the O coverage was significantly reduced and all three surface atoms were terminated primarily by F; Ga fluorides dominated. Subsequent Al2O3 ALD completely removed surface oxides and fluorides producing a chemically sharp Al2O3/InGaAs interface. On native oxide covered InGaAs, Al2O3 ALD thinned but did not completely remove the oxide layer, which acted as an O source for film growth. Surface reactions between the oxides and fluorides on the surface and the TMA precursor occurred in the first pulse. O and F were transferred from substrate atoms to Al, and CH3 groups were transferred from Al to substrate atoms; these reactions formed Al-O bonding that remained on the surface, Al-F bonding that remained or desorbed as AlF3, and trimethyl species containing substrate atoms that desorbed. These processes compete with one another, since Al-O moieties block reaction of substrate oxide surface sites, effectively burying them. Thermodynamics and bond strengths provide the driving force, but kinetics and surface coverage determines the extent of reaction. Similar results were obtained on the InAlAs(100) surface, except Al fluorides retarded the Al2O3 growth rate. Both gas and liquid phase HF chemistries thinned native oxide layers to near monolayer coverages, allowing TMA to react with and remove residual oxides before Al2O3 was deposited blocking reaction sites.
9:30 AM - C10.2
Surface Preparation of Ternary III-V Compound Semiconductors for Atomic Layer Deposition of High-k Films
Fee Li Lie 1 , Willy Rachmady 2 , Anthony Muscat 1 Show Abstract
1 Department of Chemical and Environmental Engineering, University of Arizona, Tucson, Arizona, United States, 2 Components Research, Intel Corporation, Hillsboro, Oregon, United States
Direct deposition of high-k dielectrics on III-V surfaces could spur the development of advanced CMOS devices. The surface must be free of the oxides of group III and V atoms, which produce defects and create energy states in the band gap of the semiconductor. The controlled removal of the native oxide layer as well as surface passivation and activation prior to high-k deposition are key processing steps. Chemical etching, thermal desorption, and ion bombardment of III-V’s can partially remove oxides, roughen surfaces, and etch components at different rates leading to changes in surface stoichiometry. This study compares native oxide removal and surface termination of InGaAs(100) and InAlAs(100) with liquid and gas phase HF chemistries. Gas phase HF processing was done in situ to prevent reoxidation of the surface after cleaning. Samples were immersed in 49% aqueous HF solutions for 5 min at room temperature or exposed to mixtures of anhydrous HF and water vapor at molar ratios from 0.3 to 2.3 for 30 s at 100 Torr and 29°C. Al2O3 films were subsequently grown by ALD at 170°C. Both liquid and gas phase HF etching showed comparable oxide removal based on O 1s XPS peak areas; the stoichiometry and surface termination, however, differed significantly. Liquid phase HF etching resulted in complete removal of In2O3 and As2O5, yielding a highly As-rich surface with an overall In:Ga:As ratio of 0.3:0.2:1 and In:Al:As ratio of 0.1:0.1:1. Residual As2O3 observed on both InGaAs and InAlAs, and residual Ga2O3 on InGaAs, could be due to reoxidation in atmosphere. F-termination was only observed on Al atoms of InAlAs. In contrast, gas phase HF etching resulted in complete removal of As2O3 and significant F-termination of InGaAs and InAlAs. The overall In:Ga:As ratio ranged from 0.5:0.5:1 to 0.6:0.7:1 due to preferential fluorination of In and Ga atoms at higher HF:H2O molar ratios. The overall In:Al:As ratio was 0.7:0.5:1 with no significant dependence on the HF:H2O ratio. When oxides were removed, preferential fluorination of group III atoms occurred because of the higher thermodynamic stability. Although the bond strength of group III fluorides increases from In to Al, there was no observed preference for Al-fluoride on InAlAs, in contrast to Ga-fluoride formation on InGaAs. This is attributed to the Al-deficient starting surface, where In:Al:As ~0.5:0.2:1. These results show that oxide removal is sensitive to the stoichiometry of the starting surface. Subsequent Al2O3 ALD on InGaAs prepared using a gas phase HF process resulted in complete removal of residual oxides and the Ga-fluoride rich overlayer, producing a chemically sharp Al2O3/InGaAs interface. Similar results were obtained on InAlAs, except thermodynamically stable Al-fluoride remained. This study highlights the versatility of gas phase processing in controlling the surface termination and preserving a starting surface stoichiometry to facilitate subsequent high-k layer deposition.
9:45 AM - C10.3
Interface of ALD dielectrics on GaAs.
Theodosia Gougousi 1 , Justin Hackley 1 , John Lacis 1 , J. Derek Demaree 2 Show Abstract
1 Physics, UMBC, Baltimore , Maryland, United States, 2 , Army Research Laboratory, Aberdeen Proving Ground, Maryland, United States
The atomic layer deposition of HfO2 thin films is studied on GaAs(100) surfaces. Several GaAs starting surfaces are investigated, including native oxide and HF or NH4OH-treated substrates. Wet chemical etching in either HF or NH4OH solutions are shown to remove most of the Ga and As native oxides. The HfO2 films are grown using two different but similar ALD chemistries based on the reaction of the metal amide precursors tetrakis(dimethyl)amino hafnium (TDMAHf) and tetrakis(ethylmethyl)amino hafnium (TEMAHf) with H2O. Rutherford backscattering spectrometry (RBS) shows that steady-state growth comparable to that achieved on SiO2 is reached after 10-20 ALD cycles for all GaAs surfaces; however the NH4OH treated surface displays high initial hafnium surface coverage for both processes. The interface of the films deposited on GaAs surfaces is probed by X-ray photoelectron spectroscopy. Both the HF and NH4OH treatments passivate the surface and prevent the oxidation of the interface during the deposition of coalesced films. During the deposition of HfO2 films on native oxide GaAs surfaces we observe consumption of the native oxides for both processes; the As-oxide and most of the Ga-oxide is completely removed after 20-25 ALD cycles. The presence of As oxides is not detected for films as thick as ~100Å (100 cycles) deposited on native oxide substrates. This observation corroborates the presence of an “interfacial cleaning” mechanism comparable to that observed for other ALD processes.[1-5]  M.M. Frank, G.D. Wilk, D. Starodub, T. Gustafsson, E. Garfunkel, Y.J. Chabal, J. Grazul, D.A. Muller, Appl. Phys. Lett. 86, 152904 (2005) M.L. Huang, Y.C. Chang, C.H. Chang, Y.J. Lee, P. Chang, J. Kwo, T.B. Wu, M. Hong, Appl. Phys. Lett. 87, 252104 (2005). C.-H. Chang, Y.-K. Chiou, Y.-C. Chang, K.-Y. Lee, T.-D. Lin, T.-B. Wu, M. Hong, J. Kwo, Appl. Phys. Lett. 89, 242911 (2006). D. Shahrjerdi, D. I. Garcia-Gutierrez, E. Tutuc, S.K. Banerjee, Appl. Phys. Lett. 92, 223501 (2008). C. L. Hinkle A. M. Sonnet, E. M. Vogel, S. McDonnell, G. J. Hughes, M. Milojevic, B. Lee, F. S. Aguirre-Tostado, K. J. Choi, H. C. Kim, J. Kim, and R. M. Wallace. Applied Physics Letters 92, 071901 (2008).
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Molecular Beam Deposition of Gd2O3 Films on GeO2/Ge Passivated III-V Compound Substrates (GaAs, In0.15Ga0.85As) Prepared by Atomic Hydrogen Cleaning.
Alessandro Molle 1 , Sabina Spiga 1 , Andrea Andreozzi 1 , Marco Fanciulli 1 2 , Guy Brammertz 3 , Marc Meuris 3 Show Abstract
1 Laboratorio Nazionale MDM, CNR-INFM, Agrate Brianza, Milano, Italy, 2 Dipartimento di Scienza dei Materiali, Università degli Studi di Milano Bicocca, Milano, Milano, Italy, 3 , IMEC, Leuven Belgium
The continued scaling of metal-oxide-semiconductor (MOS) devices will next demand for coupling high-k materials as gate oxides with high mobility III-V compounds as channel substrates . To this respect, molecular beam deposition of Gd2O3 films was performed on III-V compound semiconductor substrates (GaAs and In0.15Ga0.85As) by separate use of atomic oxygen and molecular oxygen as oxidizing agents during growth, in order to fabricate III-V based MOS capacitors. The substrates were initially prepared by in situ exposure to atomic hydrogen radicals and then covered by an ultra thin GeO2/Ge double layer (total thickness 3 nm) aiming at the III-V surface passivation. The combined effect of atomic H cleaning and deposition of the GeO2/Ge passivation stack was investigated in terms of the interfacial semiconductor-oxygen bonding which can presumably act as a source of electrically charged traps . The chemical details of the GeO2/Ge/III-V interfaces were carefully unravelled by in situ spectroscopic techniques. Subsequently, differently grown Gd2O3 stacks were deposited on top of the GeO2/Ge passivated III-V substrates. The compositional integrity of the multistacked Gd2O3/GeO2/Ge/III-V heterostructures is preserved during the multiple growth processes as results from depth profiling analysis. Capacitance-voltage measurements of the Gd2O3/GeO2/Ge/III-V heterostructures were performed at several temperatures in order to account for the density of interface traps all along the upper half of the substrate energy gap . A comparative study between multistacked heterostructures fabricated on different III-V substrates of GaAs and In0.15Ga0.85As and with different Gd2O3 growth methods is then discussed. The International Technology Roadmap for Semiconductor, Semiconductor Industry Association, 2007. Available at: http://www.itrs.net  A. Molle, S. Spiga, A. Andreozzi, M. Fanciulli, G. Brammertz, M. Meuris, Appl. Phys. Lett. 93, 133504 (2008) G. Brammertz, K. Martens, S. Sioncke, A. Delabie, M. Caymax, M. Meuris, and M. Heyns, Appl. Phys. Lett. 91, 133510 (2007)
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Control of Interfacial Oxide Formation for Dielectrics in Direct Contact with III-V Channels.
Marko Milojevic 1 , Rocio Contreras-Guerrero 2 , Hyun Chul Kim 1 , Maximo Lopez Lopez 2 , Jiyoung Kim 1 , Robert Wallace 1 Show Abstract
1 Materials Science and Engineering, University of Texas at Dallas, Richardson, Texas, United States, 2 Department of Physics, CINVESTAV-IPN, Mexico City Mexico
Recent results have demonstrated that deposition of high-κ dielectrics on III-V substrates requires careful control interfacial oxide species. Promising results have been obtained using Atomic Layer Deposition (ALD) of Al2O3 and the use of silicon interface passivation layers (IPL). These IPLs are intended to react with residual interfacial oxides present as well as prevent subsequent oxidation of the substrate during dielectric deposition. In this study we investigate the effect of insertion of thin metallic (Lanthanum and Aluminum) layers in the gate stack on substrate oxidation. ALD Al2O3 is used as the dielectric, while La and Al are deposited from effusion and e-beam sources respectively. In-situ monochromatic X-Ray Photoelectron Spectroscopy (XPS) was used in order to study the chemical changes that occur following each individual precursor pulse as well as the deposition of the metallic layers. This approach permits the direct observation of the effect of each deposition step without serious contamination associated with ex-situ analysis. Surfaces prepared using several common chemical pretreatments, such as NH4OH, HCl, (NH4)2S as well as oxide free surfaces, are studied. The control of channel constituent oxidation states in conjunction with dielectric formation is presented. This work is supported by the FCRP MSD Center, the System 2010 (COSAR-MKE) Project, and Sematech.
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Interface and Electrical Properties of Atomic-layer-deposited HfAlO Gate Dielectric for n-channel GaAs MOSFETs.
Rahul Suri 1 , Daniel Lichtenwalner 2 , Veena Misra 1 Show Abstract
1 Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina, United States, 2 Materials Science and Engineering, North Carolina State University, Raleigh, North Carolina, United States
In an effort to identify the most suitable gatestack for n-channel MOSFETs on high mobility III-V substrates, the approach of passivating the III-V semiconductor (mainly GaAs and InGaAs) surface with Si or Ge interface passivation layer (IPL) prior to dielectric deposition has shown promising results. However, in addition to added processing complexities, the approach of using an IPL also poses an EOT scaling limitation. Therefore, it is of practical importance to understand and resolve the issues associated with high-K gate dielectric/GaAs interface and establish a suitable gate dielectric without requiring an additional interface layer.1,2 With regards to this goal, the interface condition as well as electrical characteristics of atomic-layer-deposited (ALD) HfAlO gate dielectric on sulfur-passivated GaAs were investigated, using x-ray photoelectron spectroscopy (XPS) and capacitance-voltage and current-voltage techniques respectively. By optimizing the a) sulfur-based pre-ALD clean, b) dielectric growth, and c) post-deposition annealing (PDA) conditions, an equivalent oxide thickness (EOT) of < 2 nm with a gate leakage current density (Jg) of the order of 10-3A/cm2 or less have been achieved. The resulting frequency dispersion and hysteresis values are comparable to the data published for HfO2 gate dielectric on GaAs with Si or Ge IPL. Arsenic oxides, which are considered as a potential cause of Fermi Level pinning, were not detected by XPS neither after pre-ALD clean nor after post deposition annealing. These results suggest a good quality high-K dielectric interface on GaAs and provoke interest in further optimization of HfAlO as the high-K gate dielectric material for n-channel III-V MOSFETs. Results from physical and electrical characterization of the HfAlO/GaAs MOS devices will be presented. The impact of post metallization anneal on the dielectric properties will also be discussed with respect to the optimum source/drain activation anneal temperature for n-channel MOSFET fabrication.1 R. Suri, D. J. Lichtenwalner, and V. Misra, Appl. Phys. Lett. 92, 243506 (2008)2 R. Suri, B. Lee, D. J. Lichtenwalner, N. Biswas, and V. Misra, Appl. Phys. Lett. 93 (2008)
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