Alfred Grill IBM T. J. Watson Research Center
Martin Gall Freescale Semiconductor
Francesca Iacopi IMEC
Junichi Koiki Tohoku University
Takamasi Usui Toshiba America Electronic Components, Inc
D1: Low-k Dielectrics 1
Tuesday PM, April 14, 2009
Room 2003 (Moscone West)
9:30 AM - **D1.1
Photo-Patternable Low-κ Dielectrics: New Materials for ``Greener" Semiconductor Manufacturing.
Qinghuang Lin 1 , A. Nelson 2 , P. Brock 2 , S. Cohen 1 , B. Davis 2 , J. Gambino 3 , E. Liniger 1 , D. Neumayer 1 , Y. Ostrovski 1 , J. Patel 1 , E. Simonyi 1 , R. Sooriyakumaran 1 , S. Purushothaman 1 , R. Miller 2 , R. Wisnieff 1 Show Abstract
1 , IBM Watson Research Center, Yorktown Heights, New York, United States, 2 , IBM Almaden Research, San Jose, California, United States, 3 , IBM Systems &Technology Group, Essex Junction, Vermont, United States
The introduction of low dielectric constant (low-κ, κ≤3.0) and ultra low-κ (κ≤2.5) dielectric materials into sub-90 nm node semiconductor Back-End-Of-the-Line (BEOL) has significantly increased process complexity due to the need for several sacrificial layers to form dual-damascene BEOL structures. The need for these sacrificial layers has resulted in considerable added process complexity, additional equipment as well as increased material and process costs. These additional processes also consume valuable resources (water and energy). This trend is expected to continue in the future generations of integrated circuits as even lower-κ BEOL options are implemented. In this paper, we demonstrate a novel photo-patternable low-κ dielectric material concept that offers a “greener” way for semiconductor manufacturing. It also significantly reduces semiconductor BEOL integration complexity and hence fabrication costs. A photo-patternable low-κ material combines the functions of a traditional resist and a dielectric material into one single material. It acts as a photoresist during optical lithography patterning and is subsequently converted into a low-κ dielectric material during a post-patterning curing process. With a photo-patternable low-κ material, sacrificial materials and their related film deposition, etch, and removal processes are not required for BEOL dual-damascene patterning. As a result, dual-damascene structures for Cu/low-κ integration can be patterned with remarkable simplicity and efficiency using this novel approach. Moreover, etch-induced dielectric material damage in the traditional Cu dual-damascene integration is significantly reduced in this new photo-patternable low-κ integration. We have developed a photo-patternable low-κ material for 248 nm optical lithography. This photo-patternable low-κ material is based on a SiCOH material platform with a κ=2.7 and an elastic modulus of 6.1 GPa. It offers sub-200 nm resolution capability with a 0.63NA 248 nm optical lithographic tool. We have also demonstrated Cu/patternable low-κ dual-damascene integration at the 45 nm node BEOL fat-wire levels with very high electrical yields using the current semiconductor manufacturing infrastructure. Acknowledgments: The authors would like to thank valuable assistance from numerous IBM colleagues, including the IBM Science and Technology Research Laboratories at IBM Watson Research Center, IBM Almaden Research Center, and the IBM Resist Group in Fishkill, New York. We are also grateful for insightful discussions with Drs. Robert Allen, Matthew Angyal, Glenn Biery, Dan Edelstein, Thomas Ivers, William Landers, Terry Spooner, and Theodorus Standaert. We also would like to thank valuable assistance from JSR Corp. in providing component and material scale-up, particularly Drs. Terukazu Kokubo and Kyouyuu Yasuda.
10:00 AM - D1.2
Photo-definition of UV-cured Epoxy Siloxane Polymers.
Pei-I Wang 1 , Dexian Ye 1 , Toh-Ming Lu 1 , Ram Ghoshal 2 , Rajat Ghoshal 2 Show Abstract
1 Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York, United States, 2 , Polyset Co. Inc., Mechanicville, New York, United States
In this presentation we report the study of the photo-definition characteristics of the Polyset epoxy siloxane polymers (PES) using ultraviolet (UV) cure and imprint lithography. The novel PES polymer is a low dielectric constant (low-κ) polymer with dielectric constant of 2.8. The polymer is thermally stable to > 350 °C and has Young’s modulus of ~ 5 GPa, dielectric strength of > 5 MV/cm, leakage current density in 10-9 A/cm2 range at the applied field of 1 MV/cm, and low moisture uptake (.2% (85 °C/85%RH)). In addition, PES exhibits excellent adhesion and workability. It is UV-curable with photoinitiator chemistry based on cationic polymerization. The scanning electron microscopic images of the UV-cured patterns exhibit appealing resolution of micrometer scale features, particularly down to 15 micron vias with tunable sidewall slope for 20 micron thick films. We also show that we are able to use the PES polymers as an imprint material to replicate patterns with feature size below 100 nm. Good dielectric properties and the ease of patterning using UV and imprint lithography make PES a potential material for redistribution layer applications.
10:15 AM - D1.3
Chemistry Effects on Properties and Integrability of Porous SiCOH Dielectrics for 45nm to 22 nm Technology Nodes.
Alfred Grill 1 , S. Gates 1 , C. Dimitrakopoulos 1 , V. Patel 1 , S. Chen 2 , E. Ryan 3 , S. Cohen 1 , E. Simonyi 1 , E. Liniger 1 , Y. Ostrovski 1 Show Abstract
1 , IBM - T.J.Watson Res.Ctr., Yorktown Heights, New York, United States, 2 , IBM at Albany Nanotech, Albany, New York, United States, 3 , Advanced Micro Devices, Albany, New York, United States
ULSI interconnects based on a porous SiCOH (pSiCOH) dielectric with dielectric constant k = 2.4 entered production in IBM’s 45 nm technology node and will be used at the 32 nm node as well. Dielectrics with lower k values will be required at following technology nodes. We have compared two chemistries for the deposition of pSiCOH by PECVD targeting the extension of k to lower values, engineering the pore structure of the dielectric, and optimizing its integration compatibility. One chemistry produced V1 type films with a skeleton of O-Si-O bonds, with nm scale pores stabilized by Si-CH3 groups. The second chemistry produced V2 type films whose skeleton comprised Si-CH2-Si bonds in addition to the Si-O-Si bonds. We compared films with k=2.4 and 2.2 prepared from both chemistries.The porosity of the films was investigated by ellipsometric porosimetry (EP) and positron annihilation lifetime spectroscopy (PALS). The mechanical properties were measured by nanoindentation measurements and the electrical properties were characterized on MIS structures. The resistance of the films to plasma damage and their patternability was further investigated.It was found that the V2 type films reached k values similar to the V1 films at lower degrees of porosity and had lower levels of pore interconnectivity than V1 films at each k value. The modulus of the V2 films was lower than that of the V1 films due to the replacement of some Si-O-Si bonds by Si-CH2-Si bonds. However, the V2 films have better resistance to plasma damage and provide improved patternability and better control of critical dimension that V1 films of same k=2.2.This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities
10:30 AM - D1.4
Effect Of Trapping On Dielectric Conduction Mechanisms Of ULK/Cu Interconnects.
Virginie Verriere 1 2 , Cyril Guedj 2 , David Roy 1 , Alain Sylvestre 3 Show Abstract
1 , STMicroelectronics, Crolles France, 2 , CEA, Grenoble France, 3 , CNRS, Grenoble France
The drastic reduction of intra-level Metal-Metal spacing in advanced interconnects poses concern for reliability linked to the dielectric integrity. The characterization of leakage currents conduction mechanisms at nominal conditions is a major concern for dielectric reliability, to extract defect density and understand aging mechanisms at low field. Tests structures were fabricated with an advanced Cu/low-k process with 45 nm nodes processes. Prior to all measurements, samples were annealed at 120 degrees Celsius in nitrogen environment to remove moisture. Measurements were performed on comb-comb test structures with a total length of 14 mm and different spacing from 66 nm to 88 nm. The leakage currents were measured with a HP B1500 parameter analyzer. Trapping has been put in evidence by a shift in voltage between the first measurement on virgin structures and the second one . With a density of about 5.1011 cm-2, these filled traps create a space charge that deforms the band diagram and reduce the current flow across the dielectric stack. The impact of trapping on I(V) curves and the determination of the conduction mechanisms have been studied. The conduction mechanisms may be identified based on the variation of the current exponent factor with the calculation of the parameter α=dlnJ/dlnE by Savitzky Golay method. For electric field high enough, in the case of a Poole-Frenkel conduction, α can be approximated by α~E1/2 that is easily recognized in a logarithmic representation. Thus, a Poole-Frenkel conduction is well identified in the virgin curve I(V) before trapping. A permittivity of 2,89 is obtained by a fit of α against E1/2/kBT. After trapping, the leakage current measurements have been performed for other temperatures. It is observed the same slope for the plot of α against E1/2/kBT with an increasing of the intercept, not on the whole range of fields. It has been evidenced that the conduction after trapping does not exclusively correspond to Poole-Frenkel conduction, and that the intercept is linked to the filled traps density. Nevertheless, a Poole-Frenkel activation energy of 1 eV is obtained . Successive current-voltage measurements have been performed with a continuous increase on the maximum voltage. It has been observed a progressive shift of curves traducing the evolution of the trapping, and in parallel an increase of the intercept in the slope of α against E1/2/kBT. Nevertheless, the plot of the parameters α against E1/2/kBT allows to extract a permittivity of 2,63 in this case.A complementary method of characterization of the leakage currents allowed extraction of additional parameters that are directly linked to the filled traps density. From these observations, the goal is to obtain a refined comprehension of the conduction mechanisms and to deduce directly from them both filled traps density and traps density that participate to the conduction. M. Vilmay et al., Microelectron. Eng., 85, 2075 (2008).
10:45 AM - D1.5
X-ray Photoelectron Spectroscopy used to Characterize Reactive Ion Etch polymer for 65/45nm Copper Interconnects.
Samuel Choi 1 , Chester Dziobkowski 2 , Tsong Lin Leo Tai 2 Show Abstract
1 Research, IBM, Hopewell Junction, New York, United States, 2 SRDC, IBM, Hopewell Junction, New York, United States
At 65nm and beyond technology nodes, copper interconnect formation in the dual damascene integration is continually challenged from a polymer management perspective. The polymer generating plasma chemistries are required to maintain line edge roughness, physical profile, and critical dimension control across a 300mm silicon wafer. The undesired but necessary by-product of flourocarbon polymer can lead to poor defects performance which is costly for a 300mm wafer.This paper proposes the use of X-ray photoelectron spectroscopy (XPS) analytical characterization technique to diagnose and to optimize reactive ion etch by-products to reduce process generated defects. A reduction of 2 at.% in carbon mass from a baseline RIE process resulted in a Do (defects/cm2) improvement from > 2.0 to less than 1.0. A RIE process can be optimize to minimize fluorocarbon content to reduce defects while maintaining physical and critical dimension requirements. Moreover, due to the shorter turnaround time of XPS characterization compared to running electrical hardware splits, a shorter yield learning cycle is realized for both RIE process and module integration.
11:30 AM - D1.6
Recombination of Oxygen and Hydrogen Atoms on the Surface of low-k Materials.
O. Braginsky 1 , A. Kovalev 1 , D. Lopaev 1 , E. Malykhin 1 , Yu Mankelevich 1 , T. Rakhimova 1 , A. Rakhimov 1 , A. Vasilieva 1 , S. Zyryanov 1 , Mikhail Baklanov 2 Show Abstract
1 , Skobeltsyn Institute of Nuclear Physics of Moscow State University, Moscow Russian Federation, 2 AMPS, IMEC, Leuven Belgium
Plasma damage is an important challenge for integration of low-k materials. The degree of plasma damage is defined by chemical interaction of active radicals with hydrophobic groups (Si-CH3 groups), ion and VUV radiations from the etch/strip plasmas. Therefore, it is important to carry out a separate study of each of these factors to understand mechanisms of plasma damage and to find ways for the damage reduction. For the chemical damage, it is important to evaluate the depth of radicals penetration, which depends on their recombination coefficients and consumption in reaction with SiCH3 groups. In this work, recombination of H and O atoms on low-K surface is studied. The experiments were carried out with CVD SiCOH low-k films with various porosity and pore size in both pure hydrogen and oxygen and in their mixture with helium and nitrogen in the far plasma afterglow conditions. In this case we were able to exclude influence of ions and VUV photons. Atomic recombination was measured by plasma induced fluorescence technique based on the Ar actinometry method. The measured values of the recombination coefficients are compared with the results obtained by numerical modeling of gas-surface reactions on surfaces with different roughness (depending on porosity). Probabilities of occupation of various surface sites from weakly bonded physisorbed atoms to chemisorbed atoms are estimated. For a given flux of radicals X (X = H, O or N atoms) the kinetics of the surface sites filling (physisorbed atoms PX, quasi-chemisorbed atoms QX and chemisorbed atoms SX), and non-occupied surface sites (P*, Q* and S*) is calculated numerically. It is concluded that the recombination reactions in our conditions are described by Langmuir-Hinshelwood mechanism that involves processes of atomic adsorption and desorption, surface diffusion and recombination. The calculated results are in good agreement with the experimental results and show that the concentration profile of the radicals inside low-k films are determined mainly by recombination of PX and SX atoms. The rate of radicals consumption in the reaction with Si-CH3 groups is for several orders of magnitude lower than the recombination rates. Therefore, the depth and profile of plasma damage is defined by the recombination rate of active radicals. The effect of nitrogen atoms and helium metastable states on H and O recombination probability is discussed. It is speculated that He metastable atoms are able to create surface active centers for chemisorption of O and H atoms (SX), which increase the probability of Langmuir-Hinshelwood recombination coefficients. As a result, the depth and degree of plasma damage can be significantly reduced.
11:45 AM - D1.7
Role of Ion, Photon, and Radical on Plasma Damage of Low-k Dielectrics.
Hualiang Shi 1 , Huai Huang 1 , Junjing Bao 1 , Ryan Smith 1 , Jay Im 1 , Paul Ho 1 , Yifeng Zhou 2 , Jeremiah Pender 2 , Michael Armacost 2 , David Kyser 2 Show Abstract
1 Laboratory for Interconnect and Packaging, The University of Texas at Austin, Austin, Texas, United States, 2 , Applied Materials, Sunnyvale, California, United States
The role of ion, photon, and radical on plasma damage of porous low-k dielectrics was investigated using a gap structure, which had a tunnel-like configuration with two parallel rectangular Si spacers and the top mask and the low-k dielectric film (thinner than the Si spacers) placed inside the tunnel, leaving a gap between the film and the mask. Here, the dielectrics, k~2.2, had a different carbon doping level: normal and high. The plasma experiments were performed in an inductively coupled plasma (ICP) etcher. Ion energy was tuned by bias power applied to the bottom electrode. Photon intensity was controlled by varying mask thickness from 0.5 mm to 2.0 mm and process parameters such as plasma source power and chamber pressure. Photon energy impinging on low-k dielectrics was filtered by masks with different cut-off wavelengths including MgF2 (112 nm), CaF2 (122 nm), fused Silica (160 nm), and Si (1.5 um). Radical concentration was adjusted by gap height and mask length. In addition, the substrate temperature was considered as another variable. The results showed that the extent of plasma-induced damage depended on the radical concentration, photon energy, ion energy, and low-k structure. The CO2 and O2 plasma-induced damages such as film shrinkage, methyl depletion, and moisture uptake were found to be proportional to oxygen radical concentration and enhanced by Vacuum Ultraviolet (VUV) radiation. Comparison between ICP plasma with and without bias power indicated that the ion bombardment can induce surface densification to block the diffusion of oxygen radical and further reduce the extent of damage. The role of VUV radiation on plasma damage was further studied by using pure Ar plasma. Under this condition, VUV radiation can degrade porous low-k dielectrics directly. In terms of carbon doping, the material with the high doping level exhibited better resistance to plasma damage. On the basis of the kinetics of radical diffusion, reaction, and recombination, a model was developed to describe the oxygen radical concentration inside the gap and interpret the plasma damage characteristics.
12:00 PM - D1.8
Characterization of Plasma Damage in Low-k Films by TVS Measurements.
Ivan Ciofi 1 , Mikhail Baklanov 1 , Giovanni Calbo 1 , Zsolt Tokei 1 , Gerald Beyer 1 Show Abstract
1 , IMEC, Leuven Belgium
We evaluated Triangular Voltage Sweep (TVS) measurements as a technique to characterize plasma damage in low-k films. Blanket wafers with low-k films of different porosity and k value were prepared. Our samples included an SiOC:H material with 7% porosity and k value of 3.0, deposited on 200mm wafers, and two SiOC:H materials with 25% porosity and k value of 2.5, deposited on 300mm wafers. Before deposition, a thin layer of dry thermal oxide (2 – 5 nm) was grown on the n-type wafers to stabilize the silicon interface. After deposition, low-k films were exposed to N2/H2 plasma for different times in order to induce different degree of plasma damage. Untreated low-k films were always included as a reference. For electrical measurements, metal dots were deposited on pieces to fabricate Metal-Insulator-Semiconductor capacitors. TVS measurements were performed at 190°C on the different samples. On samples exposed to N2/H2 plasma, we detected a current peak in the TVS trace, whose magnitude increased with exposure time to plasma. No peaks were detected on untreated films. This indicates that TVS measurements are sensitive to plasma damage. Furthermore, TVS results correlated well with FTIR spectra that showed increasing damage and H2O uptake with increasing exposure time to plasma. We conclude that TVS measurements are suitable for characterizing the degree of plasma damage in low-k films and complement well materials analysis, because with the help of TVS a link to leakage properties can be made. As an application, we used TVS measurements for evaluating restoration of plasma damaged low-k films by long N2-bake at high temperature. Wafer pieces from each sample were baked at 350°C for 4h30min in N2 atmosphere. A few pieces were measured immediately after baking. The remaining pieces were either left exposed to ambient for a few days or dipped in deionized H2O for a few hours to evaluate recovery of hydrophobic properties. The different treatments (N2-bake, exposure to ambient, H2O dipping) were always performed on blanket wafer pieces. Metal dots for electrical measurements were only deposited after the treatment. CV and FTIR measurements were performed before and after treatments to evaluate change in k-value and material structure, respectively. Our data show that long N2-bake at high temperature can partially restore damaged low-k films. The magnitude of the damage-related TVS peak was significantly reduced after heat treatment and remained stable even after H2O dipping. CV measurements performed on baked pieces after 6 days of exposure to ambient showed a reduced k-value. Consistently, FTIR spectra showed a significant reduction of H2O content soon after baking. The materials remained stable over several days and only minor reincorporation of H2O occurred after exposure to ambient or H2O dipping. Therefore, long N2-bake at high temperature can partially restore leakage (TVS), k-value (CV) and hydrophobic properties (FTIR) of damaged low-k films.
12:15 PM - D1.9
Three-dimensional Imaging of Pore Structures inside low-k Dielectrics by Electron Tomography.
Huolin Xin 1 , Peter Ercius 2 , David Muller 2 Show Abstract
1 Department of Physics, Cornell University, Ithaca, New York, United States, 2 School of Applied and Engineering Physics, Cornell University, Ithaca, New York, United States
While introducing porosity into dielectric films can reduce the RC delay in continued scaling of integrated circuits, it may also change the mechanical, thermal and chemical properties of the host dielectric. Previous research has largely relied on indirect bulk measurements from which only the average porosity can be extracted. However, to understand the microscopic changes in the film when porosity is introduced, three-dimensional information including pore connectivity and pore shapes is required. We report the first three-dimensional (3-D) real-space images of the pore structures inside low-k dielectrics. Using annular dark field scanning transmission electron microscopy (ADF-STEM), electron tomography allowed a reliable 3-D reconstruction of the pore structures with near one-nanometer resolution. Quantitative analysis of the 3-D structure of the porous low-k material (k = 2.5) shows that the pore sizes follow a log-normal distribution with an average pore size of 1.2-1.9 nm and 95% of the pores fall below a diameter of 5.91 nm. The 3-D tomographic technique provides an upper bound on the pore statistics and is useful in determining larger-scale porosity. It is also found that despite the presence of some large pore networks, on average there is little large pore connectivity.
12:30 PM - D1.10
Vibrational Spectroscopy of low-k films: Exploring the Potentiality of μ-Raman Characterization.
Francesca Clemente 1 , Mikhail Baklanov 1 , Adam Urbanowicz 1 , Thomas Hantschel 1 Show Abstract
1 , IMEC, Leuven Belgium
Understanding the mechanism of modifications on the low-k film matrix induced by photo and thermal curing is metrology challenging, in particular the identification of porogen residues formed during UV curing is highly desired as these residues have important impact to the leakage current of low-k materials. Fourier Transform Infrared Spectroscopy (FTIR) has been extensively used to characterize low-k films and to follow up the evolution of their properties as a function of the different applied treatments, namely UV and/or thermal curing, plasma exposure and so on. However, FTIR spectroscopy is not sufficiently sensitive to these CHx (or amorphous carbon like) residues.Micro-Raman spectroscopy offers an alternative approach to study bonds and molecular structures in low-k and presents a number of significant advantages over FTIR: improved spectral and spatial resolution and the possibility to monitor any variation in the Si substrate in the different processing steps.The improved spectral resolution, sub cm-1, can lead for example to a deeper and quantitative understanding of the CHx stretches evolution upon treatment whereas the possibility to perform μ-Raman measurements down to sub-micron spot size offers the possibility to perform mapping and enables the study the potential impact of patterning on film’s properties.Substrate monitoring offers additional information on the Si substrate, in particular on its crystalline quality, amorphization or presence of stress.In this work we present a comparative study of a set of low-k films undergone to different UV-curing and plasma treatments with particular regard to the analysis of the CHx stretch range and its related modifications. The stretching fingerprints of CHx are in the 2800-3100 cm-1 range: symmetric and anti-symmetric stretches arising from CH3- or CH2-like oscillators components can be identified and monitored as a function of the applied treatment. The spectral resolution of 0.3 cm-1 enables to identify small shifts in peak positions due to changes in the electronegativity of the substituent or in the chemical environment to which the CHx are linked to. Raman results are compared with FTIR data on the same films. Raman spectroscopy is a non destructive technique, however for organic materials and very sensitive thin films, laser irradiation at the micron scale can lead to local heating of the samples with associated degradations or unwanted modifications of the film. In this framework, possible local laser induced modifications on the samples during μ-Raman analysis are also discussed and laser power density effects on film stability shown. A power density threashold is identified. A comparison of spectra taken at different power densities for selected excitation wavelengths is also shown and discussed.
D3: Poster Session: Interconnects
Tuesday PM, April 14, 2009
Exhibition Hall (Moscone West)
6:00 PM - D3.1
Zeolite-inspired Low-k Dielectrics: Dependence on Synthesis Conditions.
Salvador Eslava 1 2 , Jone Urrutia 1 , Abheesh Busawon 4 1 , Mikhail Baklanov 1 , Francesca Iacopi 1 , Karen Maex 3 1 , Christine Kirschhock 2 , Johan Martens 2 Show Abstract
1 , IMEC, Leuven Belgium, 2 Center for Surface Science and Catalysis, Katholieke Universiteit Leuven, Leuven Belgium, 4 , Imperial College London, London United Kingdom, 3 Electrical Dept. (ESAT-INSYS), Katholieke Universiteit Leuven, Leuven Belgium
The so-called zeolite-inspired low-k (ZLK) approach for the synthesis of spin on low-k dielectrics has recently been demonstrated to overcome the intrinsic limitations of spin-on zeolite films (S. Eslava et al., J. Am. Chem Soc. 2008). Unlike zeolite films, ZLK dielectrics have pores smaller than 3 nm, are very hydrophobic (contact angle > 80 deg.), and are homogeneous at the scale of future on-chip interconnects. The ZLK approach consists of a sol-gel process with tetraalkoxysilanes and alkyltrialkoxysilanes in presence of organic templates commonly used in zeolite synthesis, i.e., tetraalkylammonium cations.In this work, we provide insight into the synthesis process of ZLK dielectrics. A systematic study of the preparation of the ZLK spin-coating precursors was performed with focus on the silane sources, the size and concentration of tetraalkylammonium cations, and the acidity-basicity. Films were prepared and characterized by thermogravimetric analysis, dynamic light scattering, Fourier transform infrared spectroscopy, ellipsometric porosimetry, water drop contact angle measurement, nanoindentation, and impedance analysis. The textural, physico-chemical, mechanical, and electrical characterization shows key insights into the dependence of the final film properties on the synthesis conditions. For example, variation of the acidity-basicity modifies the hydrolysis and co-condensation process of the silanes leading to either a random branched open network of organosilicate chains (acid) or a suspension of organosilicate nanoparticulates (base). Furthermore, the nanoparticulate structure is dependent on the tetraalkylammonium size and concentration, as a result of both colloidal and template effects.In conclusion, this work reveals and explores manners to tune the properties of ZLK dielectrics. It also emphasizes that there is high potential for research at the edge between sol-gel process and zeolite synthesis, fields that have not been synergistically exploited in the past decades.
6:00 PM - D3.10
CVD of Transition Metal Diboride Diffusion Barriers for Next Generation Interconnects.
Navneet Kumar 1 , Angel Yanguas-Gil 1 , Scott Daly 2 , John Abelson 1 , Gregory Girolami 2 Show Abstract
1 Materials Sci and Eng, University of Illinois Urbana-Champaign, Urbana, Illinois, United States, 2 Chemistry, University of Illinois Urbana-Champaign, Urbana, Illinois, United States
In future generations of microelectronics, the copper diffusion barrier must be smooth, pinhole-free, ultra-thin (< 5 nm), and conformal (uniform thickness) in trenches/vias of high aspect ratio (AR > 8). These requirements cannot be met using today’s materials and deposition approaches. We present new approach, the low temperature CVD of the metal diborides TiB2 and HfB2, which already meets the above requirements and has the potential to extend to even more challenging technologies. Metal diborides (MB2) are metallic ceramics with very high melting point (> 3000 oC), high hardness (> 20 GPa) and room-temperature resistance comparable to other thin barrier materials (300-450 μΩ-cm). The as-deposited films appear amorphous in X-ray and TEM diffraction measurements. TiB2 films grown from Ti(BH4)3dme nucleate remarkably well on oxide substrates and offer ultra-thin smooth films. However, they are not conformal in AR’s > 7:1. HfB2 films grown from Hf(BH4)4 are highly conformal in AR’s ≤ 30:1 but doe not nucleate as readily as TiB2 on oxide substrates. We discuss a combined approach – a co-flow of the two precursors – that affords HfxTi1-xB2 barrier films which are simultaneously ultra-thin, smooth, pinhole-free and conformal. We report the barrier properties of the diboride materials, including: the interface stability on low-k oxide after thermal annealing; the (de)wetting behavior of copper on the barrier; and the results of BTS measurements on Cu / barrier / oxide / Si stacks, i.e. the electrical leakage characteristics and mean the time to failure.
6:00 PM - D3.11
Thermal Stability of Cu Interconnect.
Suk Hoon Kang 1 , Jung Han Kim 1 , Hee-Suk Chung 1 , Kyu Hwan Oh 1 , Woong Ho Bang 2 , Liangshan Chen 2 , Choong-Un Kim 2 Show Abstract
1 , Seoul National University, Seoul Korea (the Republic of), 2 , University of Texas, Arlington, Texas, United States
The propagation delay of information induced by interconnections is one of the most important issues faced by microelectronic industry in order to continue the integrated device performance improvement. The feasibility of using materials with low-k, instead of conventional SiO2, to reduce the parasitic capacitance responsible for delay has received considerable attention. The stability of pores is becoming of critical question as it affects the properties related to reliability of interconnect structure. It is common assumption that the pores in low-k dielectrics are stable over processes. However, our investigation finds that pores are not necessarily stable and undergoes active reconfiguration when they are subjected to thermal stress. Interconnect pattern size and shapes also affects the thermal stability. In this study, thermal stability of low-k material is investigated by TEM observation and FEM simulation. The samples used in our investigation is fully executed Cu/porous low-k (MSSQ) interconnects with varying pattern density Because Cu, low-k and SiN have different elastic modulus and thermal expansion coefficient, severe thermal stresses are produced inside interconnect during the isothermal annealing and cooling. These observed results are compatible with FEM simulation, permanent configuration change of Cu is also understood by creep model.
6:00 PM - D3.12
Mechanical Stability of Air-gap Interconnects.
Xuefeng Zhang 1 , Suk-Kyu Ryu 2 , Daniel Chen 2 , Rui Huang 2 , Paul Ho 1 , Junjun Liu 3 , Dorel Toma 3 Show Abstract
1 Microelectronics Reseach Center, UT Austin, Austin, Texas, United States, 2 Aerospace Engineering and Engineering Mechanics , UT Austin, Austin, Texas, United States, 3 , Tokyo Electron US Holdings, Austin, Texas, United States
Implementation of air-gaps in the trench dielectric levels has been demonstrated as a potential effective solution for dielectric scaling beyond 32 nm with an achievable dielectric constant below 2.0. However, air-gap interconnect confronts serious challenges concerning its structural integrity and mechanical stability. Bridging low-k cap (or hard mask) was observed to collapse over wide gaps during thermal decomposition of the gap-forming material. Stress concentration and crack initiation at the tip of keyhole-shaped air-gaps formed by etchback and nonconformal refill schemes can also be a potential reliability concern. In this paper, we analyze the mechanical stability of air-gap interconnect structures during thermal processing and subsequent packaging assembly using 3D multilevel finite element analysis (FEA) models. Low-k cap delamination from the Cu barrier, channel cracking of the dielectric overlayer, and interface delamination under chip-package interactions (CPI) are examined with various designs of the air-gap structures including materials and geometry. Simulation results reveal that the delamination driving force depends very much on the gap width to cap thickness ratio, the channel cracking issue in the dielectric overlayers can be managed in the presence of constraints from adjacent Cu wires, and the introduction of air-gaps significantly increases the interfacial delamination probability under the outermost solder bumps. A numerical model is developed to simulate the decomposition process of the sacrificial material during formation of air-gaps. The adhesive interaction between the sacrificial material and the cap layer induces deformation and additional stresses in the low-k cap, which may lead to collapse of the low-k cap during the thermal process.
6:00 PM - D3.13
The Study of Cu/Hydrogen Silsesquioxane Interconnects Fabricated by Hot-embossing.
Chih-Chieh Hsu 1 , Li-Wei Cheng 1 , Fon-Shan Huang 1 Show Abstract
1 Electronics engineering, National Tsing Hua University, Hsinchu Taiwan
The Cu/hydrogen silsesquioxane (HSQ) interconnects fabricated by nanoimprint was studied in this paper. This simple novel method for Cu/HSQ interconnects fabrication without the conventional complicated chemical mechanical polish (CMP) process was proposed. The Cu nanowires were formed by electron beam lithography and immersion plating. An annealing process was applied to nanowires to promote grain growth. The Cu nanowires were then transferred onto HSQ by hot-embossing subsequently. After nanoimprinting, the Cu and Au nanowires could be further embedded into HSQ by a simple annealing process. The embedded depth of metal nanowires was controllable by annealing temperature and time. Moreover, there was no variation in the embedded depth of metal nanowires after 4 weeks storage. By carefully selecting the annealing condition, the Cu/HSQ single damascene structure without CMP processing having a flat surface could be obtained. Simultaneously, the adhesion between metal nanowires and HSQ was improved. The resist spin coated on the amorphous Si was patterned by electron-beam to form nano trench. Then the sample was immersed into the plating solution to deposit Cu nanowires with width 100~150 nm and height ~75 nm. The plating solution was CuSO4/HF. Thermal annealing of Cu nanowires was performed under flowing N2 to promote grain growth . After an annealing process, Cu nanowire had large apparent grain size ~50~100 nm. The resistivity of Cu nanowire was 7.2 x 10-6 Ω cm ~1.3 x 10-5 Ω cm measured by C-AFM. For substrate preparation, the HSQ diluted in methyl isobutyl ketone (MIBK) was spin coated on Si wafer. The HSQ film was prebaked at 150 °C for 3 mins in order to adjust its film viscosity and hardness. The metal nanowires were then imprinted onto HSQ by EVG 520HE at room temperature. It had a fidelity transfer of Cu nanowires. After nanoimprinting, the annealing processes at various temperature 350-400 °C for 5-60 s was successively adopted to embed Cu nanowires into HSQ film. SEM pictures show that the embedded depth of Cu nanowires was controllable by the annealing condition. However, embedded nanowires would suffer distortion caused by stress in HSQ film induced by a high temperature annealing. Changing the HSQ/MIBK volume ratio or substituting the stepwise annealing process for annealing form small pore size film with the same porosity. They may reduce the stress and suppress the line distortion. The stress of HSQ film was measured by TencorFLX-2320. The hardness and chemical structures of HSQ film with different annealing conditions was investigated by nanoindenter and Fourier transform infrared spectroscopy (FTIR), respectively. Nevertheless, the surface roughness and electrical characteristic of Cu/HSQ damascene line was measured by AFM and semiconductor parameter analyzer, respectively. This method will be a potential process for future ULSI back-end interconnection. C. C. Hsu, F. Y. Shen, and F. S. Huang 2005 Nanotechnology 16 2913
6:00 PM - D3.16
Low-Frequency Noise Characterization of the Prototype Graphene Interconnects.
Guanxiong Liu 1 , Qinghui Shao 1 , Desalegne Teweldebrhan 1 , Alexander Balandin 1 , Sergey Roumyantsev 2 , Michael Shur 2 Show Abstract
1 Electrical Engineering and Materials Science and Engineering, University of California Riverside, Riverside, California, United States, 2 Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States
As the semiconductor industry follows Moore’s law into 22-nm technology nodes one needs to find new materials for interconnect fabrication. The recently discovered carbon allotrope – graphene - consists of single atomic plane of sp2-bound atoms. Extremely high room temperature electron mobility and superior thermal conductivity  of graphene stimulated interest in using graphene for interconnect applications . The new interconnect material replacement becomes feasible only if defect densities and process variability are steadily reduced. Low-frequency noise measurements can be used as a sensitive tool for materials characterization. The reduction of the noise in graphene resistors is also important for the interconnect applications. The noise and inductive coupling can not be ignored in interconnects because of high clock frequencies and faster rise-fall time. In this talk, we present the results of the experimental investigation of the low-frequency noise in three-terminal bilayer graphene devices. The quality of graphene layers has been verified with micro-Raman spectroscopy . The back-gated devices were fabricated using the electron beam lithography and evaporation. The back-gate was used to adjust the electrical conductivity of the graphene layer placed on top of silicon/silicon-oxide substrate. The charge neutrality point for the examined devices was in the range of 13-20 V. The noise spectral density was rather low (on the order of ~ 10E-23 – 10E-22 A2/Hz at the frequency of 1 kHz). The noise was mostly determined by contacts and access layer but the upper bound of the estimated Hooge factor was 10E-5 – 10E-4, comparable to that for good quality semiconductor devices. The presence of G-R bulges and deviation from the 1/f spectrum suggest that the noise is of the carrier-number fluctuation origin due to the carrier trapping by defects. The low values of the low-frequency noise add validity to the proposed interconnect applications of graphene. The work at UC-Riverside was supported, in part, by DARPA – SRC Focus Center Research Program (FCRP) through its Interconnect Focus Center (IFC). The work at RPI was supported by NYSTAR program.  S. Ghosh, I. Calizo, D. Teweldebrhan, E.P. Pokatilov, D.L. Nika, A.A. Balandin, et al., "Extremely high thermal conductivity of graphene: Prospects for thermal management applications in nanoelectronic circuits," Appl. Phys. Lett., 92, 151911 (2008). Q. Shao, G. Liu, D. Teweldebrhan and A.A. Balandin, "High-temperature quenching of electrical resistance in graphene interconnects," Appl. Phys. Lett., 92, 202108 (2008). I. Calizo, W. Bao, F. Miao, C.N. Lau and A.A. Balandin "The effect of substrates on the Raman spectrum of graphene," Appl. Phys. Lett., 91, 201904 (2007).
6:00 PM - D3.2
Characterization of Electrical Properties of Spin-on Dielectric used for sub-60nm Technology and Beyond.
Wan-Gyu Lee 1 , Boo Tak Lim 1 , Hee Kyoung Bae 1 Show Abstract
1 Technology Application Team, National NanoFab Center, Daejeon Korea (the Republic of)
Since 1960s the minimum feature size of integrated circuits has been reduced. Especially, higher densities and smaller cell area has been realized for DRAM to reduce cost of manufacturing. This reduction of design rule requires development of machines and process technology satisfying high aspect ratio. Most of chip makers are trying to solve it with CVD. However, there are still problems and/or difficulties such as contentment of high aspect ratio, controllability of process, higher cost of process and machines, and low productivity. Spin-on glass (SOG) fulfills gap-fill property, productivity, and low cost whereas it has brought integration challenges like high wet-etch-rate and non-uniformity of CMP. Thus, combination of HDP CVD and Spin-on dielectric (SOD) is applied to STI(Shallow trench isolation) and ILD. Electrical properties of SOD used for sub-60 nm technology and beyond as a gap-fill material in STI will be presented in this study. The capacitance and leakage properties are characterized by patterned metal-insulator-metal (MIM) and comb-type structure on 8” wafer. Spin-on dielectric films of polysilazane based precursor films were deposited on stacked metal(TiN/Ti/Al/Ti)/TEOS/Si-substrates) by spin-coating and subsequently annealed at 150-400 C in N2 and then integrated further to form top electrode and pad. Electrical measurement and analysis indicated that the capacitance of the dielectric material with the area of 300 μm x 300 μm was 2.776 F at 0 V under 1MHz frequency, and the leakage current was low level of ~1 pA at 2V forward bias. The films exhibited reproducible leakage behavior with very low level of 10pA even at 20V. With smaller pattern spaces down to 200 nm, the electrical properties appeared slight increase in leakage current.However, it is maintained without any change with metal width. No fluctuation in capacitance of MIM structure was observed with applied voltage. Simple calculation gives the dielectric constant of 5.48 with extracted results which is summarized in Table 1. Gentle slopes are observed in I-V measurement when the applied voltage approaches ~6 volts.
6:00 PM - D3.20
Interfacial Adhesion of Single Glass Fiber/Gradient CNT-Epoxy Nanocomposites using Electro-Micromechanical Technique and Wettability
Joung-Man Park 1 4 , Zuojia Wang 1 , Jung-Hoon Jang 1 , Jin-Woo Kim 1 , Woo-Il Lee 2 , Jong-Kyoo Park 3 , Lawrence DeVries 4 Show Abstract
1 School of MaterialsScience and Engineering, Gyeongsang National University , Jinju, Gyungnam, Korea (the Republic of), 4 Department of Mechanical Engineering, University of Utah, Salt Lake City, Utah, United States, 2 School of Mechanical and Aerospace Engineering, Seoul National University, Seoul Korea (the Republic of), 3 , Agency for Defense Development, Daejeon Korea (the Republic of)
Interfacial adhesion and wettability with surface modification were investigated for single glass fiber/carbon nanotube (CNT)-polymer composites by electro-micromechanical technique and dynamic and static contact angle measurements under loading/subsequent unloading. Gradient specimen for contact resistance was prepared using CNT-epoxy nanocomposites and evaluated by mainly two- and four-point probe methods. The acid treatment of glass fiber surface was set up to obtain improved mechanical and adhesion properties. Apparent modulus and electrical contact resistance for CNT-epoxy composites were correlated based on the enhanced roughness effect on glass fiber. CNT-epoxy composites with good adhesion exhibited a higher apparent modulus because of better stress transferring effects due to the relatively uniform dispersion of CNT in epoxy and enhanced interfacial adhesion between CNT and the epoxy matrix. Good interfacial adhesion exhibited a higher apparent modulus and higher thermodynamic work of adhesion, Wa between single glass fiber and CNT-epoxy nanocomposite. Since the outermost surface domains are formed in heterogeneous style, the static contact angle exhibited hydrophobicity, comparing to neat epoxy exhibiting hydrophilic pattern. After glass fiber surface was treated, the tensile strength decreased significantly due to the etched fiber surface, whereas tensile modulus did not change because of inherent material’s property. Interfacial shear strength (IFSS) between etched glass fiber and CNT-epoxy nanocomposite increased possibly due to the increase in surface roughness. Acknowledgement: This work was supported by Defense Acquisition Program Administration and Agency for Defense Development under the contract UD070009AD. Zuojia Wang is grateful to the second stage of BK21 program for supporting a fellowship.
6:00 PM - D3.3
Curing Tool and Precursor Solution for Self-Assembled Scalable Porous Silica Low-k Films.
Hirakawa Masaaki 1 , Asahina Shinichi 1 , Yamazaki Takahisa 1 , Nakayama Takahiro 1 , Murakami Hirohiko 1 Show Abstract
1 , ULVAC, Inc., Suyama, Susono, Shizuoka Japan
We have developed porous silica low-k dielectric films produced by spin-coating with the precursor solution which contains the siloxane oligomer and the surfactant as a template of pores and by curing the coated films. In the curing process, films are exposed to UV light in order to remove surfactant and increase Young’s modulus at temperatures between 350-370 degree C. An increase of the dielectric constant of the film caused by moisture uptake becomes a serious issue by the UV irradiation. Hydrophobic treatment in hexamethyldisilazane (HMDS) vapor is known to be effective, but to shorten the HMDS treatment time is difficult at low temperature. If a batch furnace is used for the HMDS treatment, the turn-around-time becomes longer than 2 hours. Then, we developed and a cluster tool for UV curing and HMDS treatment by wafer-to-wafer process and precursor solutions. In the precursor solutions a gelation additive for the rapid conversion of siloxane oligomer to –Si-O-Si- network to enhance the Young’s modulus of films at low temperatures and the larger amount of organosiloxane with methylgroup to improve the hidrophobicity of films and to longer lifetime of precursor solutions as a gelation inhibitor below 100 degree C were examined for short process time and smaller thermal budget of wafers.Using precursor solutions with increasing amount of CH3/Si ratio from 0.25 to 0.56, hydrophobicity of the porous silica films was improved but the Young’s modulus was decreased. Using precursor solutions added methylsilicate and gelation agent, we examined process conditions of UV cure and HMDS treatment. When the time of HMDS treatment was varied from 0 to 35 min, the dielectric constant and Young’s modulus of porous silica films were observed no significant difference. Then the HMDS treatment time was fixed at 0 and 35 min, and the time of UV curing was varied from 20 sec to 5 min. The dielectric constants k = 1.9-2.1 and Young’s moduli E = 5.4-8.8 GPa was obtained by films with HMDS treatment, while k = 1.8-2.3 and E = 4.0-7.6 GPa were obtained by films even without HMDS treatment.To omit the HMDS treatment is possible from films formation process. The increase of the dielectric constant of films produced by only UV cure was less than 0.1 after 10 days, while in case of porous silica films produced using precursor solutions with much less amount of organosiloxane, an increase of the dielectric constant was larger than 0.3 after only 5 days.By controlling the amount of surfactant in a precursor solution, the dielectric constant was shown to be controllable from 1.7 to 2.6.
6:00 PM - D3.4
Low-k Materials Processible in Benign Solvents.
Eisuke Murotani 1 2 , Jin Kyun Lee 1 , Margarita Chatzichristidi 1 , Alexander Zakhidov 1 , Priscilla Taylor 1 , Christopher Ober 1 Show Abstract
1 Materials Science and Engineering, Cornell University, Ithaca, New York, United States, 2 R&D Center, Asahi Glass Co.,Ltd, Yokohama Japan
A new class of low dielectric constant materials composed of small molecules with a cross-linking group was synthesized. They showed high thermal stability over 400 °C and low dielectric constants of 2.7 ~ 2.8 at ambient temperature. Good amorphous film forming properties were observed in all compounds. The thermal properties including the glass transition temperature proved to be significantly improved after a cross-linking reaction. We also successfully patterned sub-micron structures in the material using an environmentally friendly, non-polar solvent; This is the first report of low-k materials processible in benign solvents such as hydrofluorous ether solvents.
6:00 PM - D3.5
Electrical Resistivity and Morphology of Thin TiN Films Grown by dc magnetron Sputtering on SiO2.
Fridrik Magnus 1 , Jon Agustsson 2 , Arni Ingason 1 , Christophe Gineste 1 , Unnar Arnalds 3 , Sveinn Olafsson 1 , Jon Gudmundsson 1 4 Show Abstract
1 Science Institute, University of Iceland, Reykjavik Iceland, 2 , Mentis Cura ehf, Reykjavik Iceland, 3 , Matvice ehf, Reykjavik Iceland, 4 Department of Electrical and Computer Engineering, University of Iceland, Reykjavik Iceland
Thin titanium nitride films were grown by reactive dc magnetron sputtering on thermally oxidized Si (100) substrates. The electrical resistance of the films was monitored in-situ during growth. The coalescence thickness was determined for various growth temperatures and found to increase with increased growth temperature from 0.7 nm at room temperature to 1.0 nm at 650 C. In contrast the thickness where a continuous film was formed decreases with increased growth temperature from 2.5 nm at room temperature to 1.7 nm at 650 C. The room temperature electrical resistivity decreases with increased growth temperature, while the in-plain grain size and the surface roughness, measured with a scanning tunneling microscope (STM), increase. Furthermore, the temperature dependence of the film electrical resistance at various stages during growth was explored.
6:00 PM - D3.7
A Study of Diffusion Barrier Characteristics of Electroless Co(W,P) Layers to Lead-free SnAgCu Solder.
Hung-Chun Pan 1 , Tsung-Eong Hsieh 1 Show Abstract
1 Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu Taiwan
Amorphous and polycrystalline electroless Co(W,P) layers were prepared and their diffusion barrier characteristics to lead-free SnAgCu (SAC) solder were investigated via the liquid- and solid-state aging tests in order to explore the applicability to under bump metallurgy (UBM) of flip-chip Cu-ICs.In the case of SAC/amorphous Co(W,P) subjected to liquid-state aging test at 250 degree C for 1 hr, scanning electron microscopy (SEM) in conjunction with energy dispersive spectroscopy (EDS) found the spallation of Ag3Sn and (Co,Cu)Sn3 intermetallic compounds (IMCs) into the solder. Further, an apparent P-rich layer containing various elements, e.g., Co, Sn and P, formed in between SAC and electroless Co(W,P). Transmission electron microscopy (TEM) revealed that the complicated IMC types comprise of the polycrystalline P-rich layer and the initially amorphous Co(W,P) transforms into polycrystalline with the embedment of numerous tiny IMC precipitates. As to the samples subjected to solder-state aging test a 150 degree C up to 1000 hrs, a thick (Cu,Co)6Sn5 IMC formed in between SAC and Co(W,P) layer was observed. There was no IMC spallation and the P-rich layer beneath IMCs was similarly seen. Formation of P-rich layer indicated that the Co(W,P) layer is in essential a sacrificial-type barrier. However, Co(W,P) may also serves as a stuffed-type barrier since the network-like IMCs forming during aging test is able to inhibit the diffusion of Cu underlayer along the grain boundaries.In the samples containing SAC/polycrystalline Co(W,P) subjected to liquid-state aging test, a mixture of (Co,Cu)Sn3 and (Co,Ag)Sn3 IMCs formed in between SAC and Co(W,P). The IMC thickness increased with the increase of aging time in accord with the diffusion-controlled growth mode. TEM revealed a distinct feature in such samples: an amorphous layer enriched with W elements formed in between SAC and polycrystalline Co(W,P). Similar interfacial morphology was observed in the samples subjected to the solid-state aging test. EDS line scan indicated the polycrystalline Co(W,P) may also serve as the diffusion barrier to solder in a sacrificial manner; nevertheless, it exhibits a higher consumption rate at the same aging condition. The analytical results above clearly illustrates the role of P element and its effects on the crystallinity of electroless Co(W,P) layer to barrier characteristics.
6:00 PM - D3.8
Programming Characteristics of Two Metal Via Type Electrically Programmable Fuse.
Deok-kee Kim 1 , Jucheol Park 1 , Yoondong Park 1 Show Abstract
1 , Samsung Electronics Company, Yongin, Gyeonggi-do, Korea (the Republic of)
Fuse devices are frequently used in CMOS chips for redundancy implementation in memory arrays, for trimming discrete components in analog circuits, for permanently holding information such as ‘chip-id,’ and for reconfiguration at the factory as well as in the field to improve chip yield. Electrically programmable fuses (eFUSEs) have replaced laser fuses (which use an external laser to burn through the wire) with their many advantages such as scalability, field programmability, and flexibility with BEOL processes.eFUSEs made of many different materials such as silicide [1, 2], Al , Cu  have been reported. eFUSEs are programmed using failure of metal lines under current stressing and, hence, maximizing flux divergence due to electromigration, thermomigration, etc. is good for easy programming. Up to now, mainly structural variations have been tried to maximize the flux divergence in metallic fuse devices. Adding flux divergence due to a material difference may be a good approach for eFUSE.In this study, microstructural and electrical characteristics of two metal Via type electrically programmable fuses were investigated. The lower level and Via metal was W and the upper level metal was Cu. The samples were made following standard DRAM processes. The thicknesses of W and Cu were 500Å and 7000Å. The metal lines were stressed with various current densities in the range of 108-109 A/cm2. The transient current profiles during stressing by a voltage pulse generator and the programming time of the fuses were measured using an oscilloscope. The microstructure of programmed fuses after stressing with various current densities was observed using TEM. Based on the tendency of the programming time variations due to different current densities and microstructural analysis of the programmed fuses, the programming mechanism of two metal Via type eFUSE was investigated. Conventional electromigration life time model was modified and applied to analyze the experimentally observed Via type metal eFUSE programming results.  D. Kim, A. Domenicucci, and S. S. Iyer, J. Appl. Phys. 103, 073708 (2008). M. Alavi, M. Bohr, J. Hicks, M. Denham, A. Cassens, D. Douglas, M. Tsai, IEDM Technical Digest, pp 855 – 858 (1997).  E. Misra, C. Marenco, N. D. Theodore, T. L. Alford, Thin Solid Films 474, 235 (2005). T. Ueda, H. Takaoka, M. Hamada, Y. Kobayashi, and A. Ono, 2006 Symposium on VLSI Technology Digest of Technical Paper (2006).
6:00 PM - D3.9
Impact of Cu Electrolyte on Filling and Resistivity of Cu Damascene Lines.
Anne Roule 1 , Vincent Carreau 1 , Emmanuel Deronzier 1 , Paul Henri Haumesser 1 , Sylvain Maitrejean 1 Show Abstract
1 , CEA, LETI, MINATEC, Grenoble France
In the damascene architecture, electrical conduction is obtained by the formation of lines and vias etched in a dielectric layer and then filled by a metal. Copper is the most commonly used metal and is deposited by Electrochemical Deposition (ECD). This process needs to be optimized to achieve Cu filling of narrower features and Cu resistivity reduction. Previous works have demonstrated that the electrolyte composition and the associated additive set are key parameters to improve both axes. Thus, specific electrolyte composition with additives is required in order to properly fill the trenches. However, at low dimensions, increase in Cu contamination resulting from electrolyte composition may induce high resistivity either due to electron scattering on impurities or reduction of grain size. Hence, the acid content of the electrolytes has been largely studied: ‘medium acid’ electrolytes give promising results for the 45 nm node and below in comparison with the more standard ‘low acid’ process. In the present study, a benchmark of two medium acid electrolytes (with different chloride contents) is proposed, with the comparison of both intrinsic Cu thin film properties and integrated Cu lines performances.The experiments were performed with identical protocol (same process tool, substrate type and testing conditions) to fairly compare the performances of the two electrolytes.Blanket wafers were used for the Cu thin film analysis (roughness, adhesion, composition, self annealing), and patterned wafers with features down to 70nm width were fabricated for the comparison of electrical performances (yield – Cu line resistivity). As a main result, a difference in copper resistivity (as deposited and integrated) is evidenced: the electrolyte with lower chloride content induces lower resistivity. However, our results suggest that the filling performances of this electrolyte are more limited in the narrowest features: higher electrical yields are obtained in these lines with the second electrolyte. Therefore, a trade-off will have to be found in the formulation of the electrolyte in order to ensure decent conductivity of the copper, while maintaining sufficient filling performances.
Alfred Grill IBM T. J. Watson Research Center
Martin Gall Freescale Semiconductor
Francesca Iacopi IMEC
Junichi Koiki Tohoku University
Takamasi Usui Toshiba America Electronic Components, Inc
D4: Metallization I
Wednesday AM, April 15, 2009
Room 2003 (Moscone West)
9:30 AM - **D4.1
Challenges of Cu Contact Process for 32nm Technology and Beyond.
Hirofumi Watatani 1 , Shinichi Akiyama 1 Show Abstract
1 , Fujitsu microelectronics limited, Kuwana Japan
In future technology nodes from 32 nm and below, the conventional W contact process will result in high contact resistance because the contact hole size is shrinking with technology. Since high parasitic resistances degrade the device performance such as drive current, inverter delay, etc., it will be necessary to reduce those resistances. Therefore, Cu filling contact may replace the conventional W contact technology.This talk will be discussed mainly together with our experience obtained from our evaluation of Cu contact that was fabricated based on 65 nm CMOS technology with 75 nm contacts landing on nickel silicide.It was necessary to overcome problems to Cu contact process, such as removal of oxide, adhesion of Cu/Barrier, and excellent barrier properties. Especially, investigation of the borderless contacts is very important because poor step coverage of barrier induces increase of the junction leak current. By using underlying titanium layer and optimizing barriers solved the problems and achieved good performance of contact resistances with excellent leakage properties without causing any damage on transistors, even after 11 Cu layer process.Cu contacts process is the promising method in future technology.
10:00 AM - D4.2
In-Situ FTIR Study of Atomic Layer Deposition of Ruthenium.
Sun Kyung Park 1 , Jin hee Kwon 1 , Yves Chabal 1 , Min Dai 2 , Ravi Kanjolia 3 Show Abstract
1 Material Science and Engineering, University of Texas at Dallas, Dallas, Texas, United States, 2 Department of Physics, Rutgers University, Piscataway, New Jersey, United States, 3 , SAFC Hitech, Haverhill, Massachusetts, United States
Ruthenium is attractive for a number of reasons: 1) high chemical and thermal stability with high-k materials; 2) no detrimental interface reactions or interdiffusion at the ruthenium-dielectric interface (i.e. most suitable noble metal electrode material); 3) potential capacitor electrode material for DRAMs and FRAMs, and potential gate metal in future metal-oxide-semiconductor field effect transistors (MOSFETs) due to is relatively high work function (4.7eV)1; 4) barrier and seed layer for copper, the interconnection metal in microelectronics. Since atomic layer deposition (ALD) is a technique of choice for deposition of thin, uniform, and conformal film growth even on structured surfaces such as trenches and via holes, there is an active search for ruthenium ALD precursors possessing appropriate physical and chemical properties, which are important for the development of a proper deposition process. There is also the need to understand the chemical interaction of these new precursors with various surfaces and the mechanism of ALD growth, requiring in-situ characterization. In this study, we present in-situ Fourier transmission infrared (FTIR) studies of ALD growth of a class of cyclopentadienyl dicarbonyl ruthenium precursors, with a focus on cyclopentadienyl ethylruthenium dicarbonyl [CpRuEt(CO)2] since it is liquid with a higher vapor pressure and higher growth rates. There is no measurable ALD of RuEt below 200oC. At higher temperatures, the RuEt begin to react with both oxidized and H-terminated Si surfaces. The reaction is complete at 300oC. Since the precursor decomposes at 350oC leading to CVD growth, the ALD window is very narrow. We grow Ru, using two types of precursors, O2 and D2O. Only when O2 is used, ligand exchange is clearly visible with in-situ FTIR. RBS measurements confirm that there is a negligible growth rate when water is used instead of O2. IR absorption measurements also make it possible to observe the electronic absorption associated with the growth of Ru and RuO2 films, with a transition from isolated, nucleated film to a continuous film. At that point, the absorbance is higher at lower frequencies, indicative of Drude absorption.  Titta Aaltonen et al., Chem. Vap. Deposition 9, 45 (2003).
10:15 AM - D4.3
Selective Cobalt Capping of Interconnects by Thermal CVD.
Harish Bhandari 1 , Roy Gordon 1 Show Abstract
1 Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States
Electromigration of copper is an increasingly important mechanism for failure of interconnects in microelectronics. The failure typically begins along the weak interface between the upper surface of copper lines and the material above, such as a silicon nitride capping layer. Placing cobalt on the upper surfaces of copper lines has been shown to strengthen this interface and thereby increase electromigration lifetimes. Several methods have been proposed for selectively placing cobalt on copper surfaces and not on adjacent insulating surfaces. Wet chemical reduction processes have difficulty maintaining adequate selectivity, because their autocatalytic mechanism amplifies growth on any defect on the insulator. Also, porous low-k materials can become contaminated by the metal ions in the solution, thereby reducing their insulating ability. Plasma-enhanced CVD have been shown to provide selective cobalt deposition, but plasma treatment increases the dielectric constant of low-k insulators. Here we introduce a selective thermal CVD process that avoids these difficulties. A vapor of a cobalt precursor reacts with molecular hydrogen gas on the surface of copper to form a continuous film of pure cobalt metal a few nanometers thick. Completeness of cobalt coverage was established by X-ray photoelectron spectra (XPS) showing the absence of copper signals from underneath the cobalt. XPS also established the absence of detectable impurities in the cobalt films. Insulating surfaces exposed to the same deposition conditions maintained their insulating character, measured by 4-point probe on planar surfaces (>10^6 ohms per square), as well as metal maze patterns separated by insulating lines 70 nm wide (>10^17 ohms per square).
10:30 AM - D4.4
Coupled Finite Element Potts Model Simulations of Grain Structure and Texture Evolution in Copper Electro-deposits.
Bala Radhakrishnan 1 , Gorti Sarma 1 , Don Nicholson 1 Show Abstract
1 Computer Science and Mathematics, Oak Ridge National Laboratory, Oak Ridge, Tennessee, United States
The evolution of grain structure and texture during self-annealing as well as annealing at higher temperatures in electro-deposited copper has been well investigated through experiments and modeling. However, rigorously coupling the effect of residual strain on grain growth and recrystallization, as well as the associated texture evolution at the microstructural length scale, has been a fairly recent activity. The initial texture distribution in the as deposited copper is fairly heterogeneous and depends on the line width as well as the distance from the bottom of the trench. The strongest texture develops at the bottom, and progressively weakens towards the top with the weakest texture existing in the over burden. Recrystallization and grain growth occur under the combined effects of curvature and strain induced boundary migration. The elastic energy within the copper grains is heterogeneous due to the elastic anisotropy as well as the local variations in constraint induced by the geometry of the interconnect design. We demonstrate a computational approach that starts with a realistic three-dimensional description of the grain structure and texture gradient in the deposit. An elasto-viscoplastic finite element model based on crystal plasticity approach is used to model the heterogeneous distribution of strain energy in the grain structure during annealing. The three-dimensional evolution of the grain structure during annealing is modeled using a Potts model that combines the driving forces due to curvature as well as the heterogeneous strain energy, which is mapped from the finite element model. The simulations will demonstrate the effect of trench geometry, thickness of over burden and the annealing temperature on the grain growth and texture evolution in the copper electro-deposit. This research was sponsored by the Laboratory Directed Research and Development Program of Oak Ridge National Laboratory (ORNL) managed by UT-Battelle, LLC for the U. S. Department of Energy under Contract DE-AC05-00OR22725.
10:45 AM - D4.5
Simulation of Interconnect Microstructures
Anthony Rollett 1 , Balasubramanian Radhakrishnan 2 , Katyun Barmak 1 Show Abstract
1 Materials Sci & Eng, Carnegie Mellon Univ., Pittsburgh, Pennsylvania, United States, 2 , Oak Ridge National Lab., Oak Ridge, Tennessee, United States
Microstructure, as in the grain boundary network, plays an important role in interconnects. Grain boundaries have a higher resistivity than the bulk in copper [J. Vac. Sci. Technol. A 26: 605] so achieving coarse grain structures reduces resistivity. In thin narrow films, the ideal microstructure is the one-dimensional, so-called bamboo structure with grain boundaries spanning the film (and no triple junctions between boundaries). In aluminum thin film interconnects it is well established that this type of microstructure, coupled with a strong <111> fiber texture (all grains share a 111 crystal axis normal to the film plane) is most resistant to electromigration failure [Mater. Chem. Phys. 41: 206]. It is not clear, however, that the <111> fiber texture is the optimum texture in copper for electromigration resistance. We review the processes of grain growth and recrystallization that can generate the desired microstructures and textures. Simulation of microstructural evolution provides useful insights into what is and is not possible to accomplish.
11:30 AM - D4.6
In-situ Characterization of Atomic Layer Deposition of Cu.
Min Dai 1 , Jinhee Kwon 1 , Yves Chabal 1 , Roy Gordon 2 Show Abstract
1 Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, Texas, United States, 2 Department of Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States
Due to its lower resistivity and higher melting point, copper is replacing aluminum as an interconnect material in integrated circuits. For such applications, a highly conformal and continuous copper seed layer is needed before subsequent higher growth rate electrochemical deposition of copper film. Atomic layer deposition (ALD) is advantageous to deposit highly uniform and conformal thin films. ALD has been successfully used to deposit a number of compounds, such as high-κ metal oxides (e.g. Al2O3, ZrO2 and HfO2) and is being seriously considered for Cu. There is therefore a need for mechanistic in situ studies of the ALD process for pure metals, particularly when new precursors are evaluated.We present work on pure copper ALD on SiO2 surfaces using a novel liquid copper precursor--copper(I) di-sec-butylacetamidinate ([Cu(sBu-amd)]2), which can react with molecular hydrogen at moderate temperatures (~150oC). Our study shows that copper agglomerates upon H2 reduction and a small portion also penetrates into the SiO2 film, as evidenced by the evolution of SiO2 phonon modes in the IR spectra. Cu agglomeration and diffusion increase when the deposition temperature is raised. The H2 reduction of the precursor ligand and ligand hydrogenation are observed by the vibrational modes attributed to CHx and NCN bonds. Ex situ XPS results confirm the deposition of copper on the SiO2 surface. Both FTIR and XPS results show residue ligand impurities inside the Cu films with small amount of N (< 2%) due to incomplete ALD reactions. RBS indicates that the growth rate on SiO2 is temperature dependent and the maximum growth rate is found in the range of 185-250oC based on one ALD cycle. At 185oC, the thickness of 10 cycles Cu is 1.04-1.18 nm with uniform nanocluster distribution.
11:45 AM - D4.7
Chemical Vapor Deposition of Copper Thin Film Using a Novel Unfluorinated Precursor of Copper(I)(N(1(dimethylvinylsiloxy)-1-methylethano)-2-imino-4-pentanoate).
Haizheng Song 1 , John A.T. Norman 2 , Yukihiro Shimogaki 1 Show Abstract
1 Department of Materials Engineering, The University of Tokyo, Tokyo Japan, 2 , Air Products and Chemicals, Inc., Carlsbad, California, United States
Copper chemical vapor deposition (CVD) is the candidate for ultra large scale integration (ULSI) multi-level interconnects for 22nm technology node and beyond. The main attraction of copper CVD is its ability to provide conformal step coverage and greater control over film quality at high deposition rates. In copper CVD, most of the copper precursors investigated in recent years have fluorine containing ligand in order to increase their volatilities. These fluorinated precursors, however, might result in fluorine contamination at the copper-barrier interface leading to poor adhesion. In addition, the expense of incorporating fluorine into a precursor keeps its price relatively high. Therefore, the unfluorinated copper precursor is more attractive for future commercial applications. In this work, a novel unfluorinated copper precursor, Copper(I)(N(1(dimethylvinylsiloxy)-1-methylethano)-2-imino-4-pentanoate), namely KI5, is investigated for CVD of copper on ruthenium substrate.In the molecule KI5, a seven membered ring imparts great stability, so that heating this precursor leads to intact evaporation of the precursor rather than disproportionation or decomposition. Since its thermal stability, KI5 can deposit copper by direct reduction. In this work, HCOOH is used as the reductant. Moreover, the thermal stability allows high source temperature to provide high vapor pressure without the concern of decomposition in the bubbler bottle. KI5 has a vapor pressure of 0.2-2.2Torr at the temperature range of 100-140C.Using KI5 and HCOOH, delivered by helium carrier gas, copper could be deposited on ruthenium at 150-350C. At chamber pressure of 5Torr, KI5 partial pressure (pKI5) of 0.02Torr, and HCOOH partial pressure of 0.69Torr, two growth regions could be distinguished: a diffusion limited region above 210C with the activation energy (Ea) of 1.9kJ/mol, and a reaction limited region below 210C with Ea=48.9kJ/mol. In the diffusion limited region, the growth rate could be increased by reducing HCOOH/KI5 ratio. It is nearly 50nm/min at 250C with the HCOOH/KI5 ratio of 2. This phenomenon implies that too much HCOOH suppresses the gas-phase diffusion of KI5. The effect of pKI5 on growth rate was examined at 150-250C. With increasing pKI5, the growth rate increased and then saturated, showing a Langmuir-Hinshelwood mode. Kinetic data extracted from these experiments enabled 2-D computational simulations for predicting copper deposition into trench structures. The simulation results indicated a good conformal deposition; the step coverage was higher than 90% for aspect ratio of 10:1. About 800nm copper film grown at 250C gave a resistivity of 1.9 μΩcm. SIMS analysis showed that carbon, hydrogen, nitrogen, oxygen or silicon was not detectable in the film making it at least 99.99 atomic % copper. These results imply that KI5 holds promise as a future copper CVD precursor for both IC interconnect and TSV/3-D structures for either copper seed layers or full fill.
12:00 PM - D4.8
Materials Engineering for Future Interconnects: Direct Electroless Cu Deposition on Self-assembled Monolayer Alternative Barriers.
Silvia Armini 1 , Ainhoa Gorrono 1 , Caroline Whelan 1 , Arantxa Maestre Caro 1 2 Show Abstract
1 AMPS, IMEC, Leuven Belgium, 2 Chemistry, KU Leuven, Leuven, Vlaams Brabant, Belgium
As device sizes decrease, accommodated by scaling and materials changes, electrochemical deposition is considered the most promising method due to its many advantages such as good uniformity and gap filling ability, selectivity and low processing temperatures. Due to the need for applied power and non-uniform current distribution of Cu electroplating, Cu electro-less deposition (ELD) is especially emphasized for future interconnect technologies. A conventional ELD approach suffers some shortcomings such as the high price of typical metal catalysts (Pt, Pd…) and possible damage to the electric properties of the Cu film due to the presence of catalyst as a contaminant. In this work, an alternative bottom-up Cu ELD method without other catalyst material activation is studied. It consists in the reduction the Cu ions in solution via standard reducing agents and mild experimental conditions (i.e. temperature, pH, reaction time, and concentrations). In addition, from an X-ray photon spectroscopy (XPS) aging study, the stability of the amino SAMs molecules chosen for the ELD deposition is demonstrated up to two months from the deposition. Transmission electron microscopy (TEM) combined with electron energy-loss spectroscopy (EELS) reveals the presence of a C-rich signal at the interface silica/ELD Cu. In particular, the EELS carbon peak corresponds to a 4 nm thick SAM layer fully compatible with the ELD experimental conditions.The ELD Cu film sheet resistance (Rs) is measured in the temperature range of 200-450°C. The initial decrease of ca. 4 Ohms/sq in Rs upon anneal and the increase observed only when the temperature reaches 450°C, confirm that the Cu silicide formation is suppressed on NH2-SAM for temperatures higher than 350°C.A conformal ELD Cu layer is deposited on patterned structures (vias and trenches). The effect of the deposition time on the Cu ELD on NH2-SAM barrier in the features is an increase in the Cu layer thickness. Lower roughness and higher adhesion strength are revealed upon anneal. In particular, we do not observed a significant difference in the Gc values measured by four-point bending adhesion measurements between the ELD and PVD Cu before (Gc of ca. 2.2 and 3.5 J/m2 for 70 nm ELD and PVD Cu layers respectively) and after (Gc of ca. 4.5 and 4.6 J/m2 for 70 nm ELD and PVD Cu layers respectively) anneal (anneal conditions: 300°C, 20 min., under forming gas atmosphere). XPS analysis was repeated on each side of the fractured sample used for the adhesion measurements at room temperature and after anneal. Based on the XPS results, at room temperature, the fracture can be located at the Cu/SiO2 interface, while after anneal it is not clear anymore where the fracture could happen.Coupon-level electrodeposition tests with standard plating chemistries on the direct ELD Cu seed layers are ongoing and compatibility with the following chemical-mechanical planarization step is being evaluated.
12:15 PM - D4.9
Rutherford Backscattering Spectrometry Analysis of Growth Rate and Activation Energy for Self-formed Ti-rich Interface Layers in Cu(Ti)/Low-k Samples.
Kazuyuki Kohama 1 , Kazuhiro Ito 1 , Kenichi Mori 2 , Kazuyoshi Maekawa 2 , Yasuharu Shirai 1 , Masanori Murakami 3 Show Abstract
1 Materials Science and Engineering, Kyoto University, Kyoto Japan, 2 Process Technology Development Div., Renesas Technology Corporation, Itami Japan, 3 , The Ritsumeikan Trust, Kyoto Japan
The device feature size has reduced to deep sub-micron scale in ultra-large scale integrated (ULSI) devices. Large resistance-capacitance (RC) delay has been critical issue, and decrease in effective electrical resistivity of Cu wires is mandatory to reduce the RC delay. The resistivity increase due to the barrier layers becomes significantly large with reduction in line width of the Cu wires. Thus, a fabrication technique to prepare nano-scale Cu wires with ultra-thin barrier layers should be developed.In our previous studies, thin Ti-rich interface layers were found to be formed in Cu(Ti)/SiO2 samples after annealing at elevated temperatures. This technique is called “self-formation of the diffusion barrier,” which is attractive for fabrication of ULSI interconnects. This technique was applicable to Cu(Ti) alloy films deposited on low dielectric constant (Low-k) materials. The Ti-rich interface layers formed on the Low-k layers were found to consist of crystalline TiC or TiSi in addition to amorphous Ti oxides. The composition of the Ti-rich interface layers cannot be explained by the enthalpy of formation of the Ti compounds (TiC and TiSi). In the present study, growth rate and activation energy for the Ti-rich interface layers were investigated by Rutherford Backscattering Spectrometry (RBS) methods to discuss the growth mechanisms.The Cu(Ti) alloys films with Ti concentrations of 1 at.%, 5 at.% and 10 at.% were deposited on the Low-k1-4(SiOxCy), SiCO, SiCN and SiO2 dielectric layers by sputtering technique. The Low-k1-4 materials have different dielectric constants. The Cu(Ti)/dielectric-layer samples were annealed at temperatures of 400°C-600°C in ultra high vacuum (UHV). The annealing in UHV suppresses the Ti segregation to the surface. The Ti segregation to the interface was investigated by RBS. In all the Cu(Ti)/dielectric-layer samples after annealing in UHV, Ti peaks were obtained only at the interface in the RBS profiles. The area (S) of the Ti peak is proportional to the number (N) of the Ti atoms. The value of S increased with annealing time and temperatures. Growth rates of the Ti-rich interface layers consisting of TiC were found to be faster than those consisting of TiSi. The growth of the Ti-rich interface layers consisting of TiC was indicated to be controlled by diffusion. Arrhenius plots of S vs 1/T suggested that the formation of the Ti-rich interface layers were thermally-activated process. The calculated activation energies of Cu(Ti)/Low-k samples were lower than those of the other samples. Those were dependent on the dielectric constant rather than what Ti compounds were formed. This tendency was observed in all the Ti concentration in the alloy films. However, the values of Cu(1at.%Ti)/dielectric-layer samples were lower than those of the others, which are similar. This suggests that the Ti concentration of 1 at.% is insufficient to continue to reaction of the Ti atoms with the dielectric layers.
12:30 PM - D4.10
Adhesion and Cu Diffusion Barrier Properties of a MnOx Barrier Layer Formed with Thermal MOCVD.
Koji Neishi 1 , Vijay Dixit 1 , Shiro Aki 1 , Junichi Koike 1 , Kenji Matsumoto 2 , Hiroshi Sato 2 , Hitoshi Itoh 2 , Shigetoshi Hosaka 2 Show Abstract
1 Materials Scinece, Tohoku University, Sendai Japan, 2 Technology Development Center, Tokyo Electron Ltd., Nirasaki Japan
A thin-amorphous MnOx layer using self-forming barrier process with a Cu-Mn alloy shows good adhesion and diffusion barrier properties between copper and dielectric layer, resulting in excellent reliability for stress and electromigration. Meanwhile, chemical vapor deposition (CVD) can be employed for conformal deposition of the barrier layer in narrow trenches and vias for future technology node. In our previous research, a thin and uniform amorphous MnOx layer could be formed on TEOS-oxide by thermal metal-organic CVD (MOCVD), showing a good diffusion barrier property. In addition, a good adhesion strength is necessary between a Cu line and a dielectric layer not only to ensure good SM and EM resistance but also to prevent film delamination under mechanical or thermal stress conditions during fabrication process such as chemical mechanical polishing or high temperature annealing. To date, no information is available with regard to the adhesion property of CVD-MnOx. In this work, we report diffusion barrier property in further detail and adhesion property in PVD-Cu/CVD-MnOx/SiO2/Si. The temperature dependence of the adhesion property is correlated with the chemical composition and valence state of Mn investigated with SIMS and Raman spectroscopy.Substrates were p-type Si wafers having a plasma-TEOS oxide of 100nm in thickness. CVD was carried out in a deposition chamber. A manganese precursor was vaporized and introduced into the deposition chamber with H2 carrier gas. After the CVD, a Cu overlayer was deposited on some samples using a sputtering system in load lock chamber of the CVD machine. The diffusion barrier property of the MnOx film was investigated in annealed samples at 400 oC for 100 hours in a vacuum of better than 1.0x10-5 Pa. The Adhesion property of Mn oxide was investigated by Scotch tape test in the as-deposited and in the annealed Cu/CVD-MnOx/TEOS samples. The obtained samples were analyzed for thickness and microstructure with TEM, chemical bonding states of the MnOx layer with XPS, and composition of each layer with SIMS. In the CVD deposition below 300 oC, no Cu delamination was observed both in the as-deposited and in the annealed Cu/CVD-MnOx/SiO2 samples. On the other hand, in the CVD deposition at 400 oC, the Cu films were delaminated from the CVD-MnOx/TEOS substrates. The XPS peak position of Mn 2p spectra indicated that the valence state of Mn in the as-deposited barrier layer at 200 oC was either 2+ or 3+. In contrast, the valence state of Mn in the as-deposited barrier layer at 400 oC was 4+. Composition analysis with SIMS as well as Raman also indicated the presence of a larger amount of carbon at 400 oC than at less than 300 oC. The good adhesion between Cu and MnOx could be attributed to the lesser charged state of Mn and to the smaller amount of carbon inclusion in the CVD barrier layer.
12:45 PM - D4.11
Electronic Transport Properties of Cu/MnOx/SiO2/p-Si MOS Devices.
Vijay Dixit 1 , K. Neishi 1 , J. Koike 1 Show Abstract
1 Material Science, Tohoku University, Sendai Japan
Our group has proposed a self-forming barrier process by the deposition of Cu-Mn alloy and subsequent annealing to promote solid-state reaction to form a MnOx barrier layer. As an alternative to the PVD-annealing process , we also proposed the MOCVD deposition of a MnOx barrier layer for an improved conformality in more advanced line structure . In the present work, we investigated diffusion barrier properties of MOCVD-MnOx by analyzing capacitance-voltage curves of MOS structure. Substrates were thermally grown SiO2 (50 nm) on p-type Si wafers. A very thin barrier layer of MnOx were grown on SiO2(50nm)/p-Si wafer by MOCVD at 100 to 400oC. After the growth of MnOx, a Cu(150nm) overlayer was deposited using a DC sputtering system located in a load-lock chamber. The blanket Cu layer was patterned to an electrode pad array of 60µmx120µm in dimension with standard photolithography process. The current-voltage curves of these MOS devices showed leakage current of <<1pA (below the detection limit of our instrument) at an electric field of 2MV/cm. The value of flat band voltage (VFB) is -1.03V as obtained from the flat band capacitance of 2.36x10-12 F. It is to be noted that without the barrier layer the VFB of an as-deposited MOS capacitor of Cu/SiO2/p-Si is approximately -6.7 volt . The negative flat band voltage shift of -1.03V with the barrier layer is mainly due to metal semiconductor work function difference, the presence of oxide charge and non-uniform carrier density due to thermal treatment of the wafer during thermal SiO2 growth. The obtain C-V data was compared with the normalized C-V curve of MOS structure made from Cu-Mg alloy that was obtained after BTA test . The C-V curve of the Cu-Mg alloy was claimed to indicate no significant interdiffusion of Cu into SiO2. Similarly, the as-deposited MOS capacitor of Cu/MnOx/SiO2/p-Si show that no sputtering and diffusion damage in these devices. The little smearing of the C-V curve along the voltage axis is due to the presence of interface, surface trap charge density. The carrier density distribution versus depletion width was also calculated. The distribution of interface trap charge density is found to be a low level of Dit ~1011eV-1cm-2. In conclusion, the barrier layer of MnOx grown below 400oC shows negligible leakage current (<<1pAmp at an electric field 2MV/cm), low surface and interface trap charge density and the absence of charge carrier in the oxide. These properties together with a small shift of VFB make the MOCVD-MnOx a promising material for a diffusion barrier layer for advanced technology node. REFERENCESJ. Koike and M. Wada, Applied Physics Letter, 87, 041911 (2005).K. Neishi, S. Aki, K. Matsumoto, H. Sato, H. Itoh, S. Hosaka, and J. Koike Appl. Phys. Lett., 93, 032106 (2008).T. Suwwan de Felipe, S. P. Murarka, S. Bedell, and W. A. Lanford, J. Vac. Sci. Technol. B, 15, 1987 (1997).
Alfred Grill IBM T. J. Watson Research Center
Martin Gall Freescale Semiconductor
Francesca Iacopi IMEC
Junichi Koiki Tohoku University
Takamasi Usui Toshiba America Electronic Components, Inc
D7: Emerging Interconnect Technologies
Thursday PM, April 16, 2009
Room 2003 (Moscone West)
2:30 PM - **D7.1
Molecular Engineering of Surfaces for Future Device Architectures using Self-assembled Monolayers.
Caroline Whelan 1 Show Abstract
1 SPDT, IMEC, Leuven Belgium
Complex interfacial structures become increasingly relevant in emerging technologies. One approach to gaining insight into metal-organic and organic-inorganic interfaces involves studying model systems. To this end, the atomically controlled surface chemistry and structure of self-assembled monolayers (SAMs) provide a means of creating model organic and inorganic thin films in the nanometre regime. This presentation will focus on the preparation, characterization and application of thiol- and silane-derived SAMs on metal and dielectric surfaces of interest in semiconductor device manufacturing of interconnects. As substrates for atomic layer deposition used in Cu metallization schemes, variation of SAM structure and chemistry facilitates tuning selectivity towards metal deposition. As passivation layers, SAMs enhance wire bonding. As potential barriers to Cu diffusion, SAMs are unique in terms of their composition and dimension. However, regardless of the application, these systems are non-trivial to characterize. This challenge can only be addressed with state-of-the-art analysis techniques. Examples will be demonstrated using high-resolution X-ray photoelectron spectroscopy, high-resolution transmission electron microscopy and low-energy ion scattering studies. Overall, SAMs represent a novel approach to surface engineering for future device structures.
3:00 PM - D7.2
Toughening Copper-silica Interfaces by Metal-catalyzed Molecular Ring Opening in a Nanolayer.
Saurabh Garg 1 , Binay Singh 1 , Xinxing Liu 2 , Pethuraja Ganesan 1 , Leonard Interrante 2 , Ganapathiraman Ramanath 1 Show Abstract
1 Materials Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States, 2 Chemistry and Chemical Biology, Rensselaer Polytechnic Institute, Troy, New York, United States
Copper-based nanodevice wiring structures require near-zero-thickness interfacial barriers for inhibiting Cu transport into, and enhancing adhesion with, low dielectric permittivity (low k) materials. Currently used refractory metal-based barriers are untenable for future devices due to difficulties in obtaining contiguous ultra thin layers in high aspect ratio features. The ultimate goal, however, is to eliminate the barrier and integrate Cu directly with the low-k dielectric such that there is high interfacial toughness without interfacial mixing. Here, we demonstrate that a molecular nanolayer of a 1,3-Disilacyclobutane-terminated organosilane (DSCBTOS) at copper-silica interfaces results in a 10-fold increase in fracture toughness upon annealing. Such chemically-induced interfacial toughening through interaction of Cu with disilacyclobutane rings paves the way for directly integrating DSCB-containing carbosilane low-k dielectrics with DSCB rings. We further show that DSCB ring-opening reduces the surface copper oxide, which could be an attractive means to decrease surface-scattering induced resistivity in Cu lines. We synthesized and assembled DSCBTOS on silica to form a 0.7-nm-thick nanolayer. Four-point bending fracture tests on as-prepared Cu/DSCBTOS/SiO2 sandwiches revealed a low interface toughness of 2.1 J/m2, comparable to pristine Cu/SiO2 structures. Core-level spectra acquired from fracture surfaces by X-ray photoelectron spectroscopy (XPS) reveal fracture at the Cu/DSCB interface. However, interfacial toughness increases monotonically with annealing temperature, yielding values as high as 21.3 J/m2 for Tanneal = 500 °C. For Tanneal ≥ 250 °C, fracture is observed at the DSCB/SiO2 interface, indicative of enahanced Cu-DSCB bonding. Cu/SiO2 interfaces treated with methyl-terminated organosilanes show 50% lower toughness for the same annealing treatments, underscoring the crucial role of DSCB rings. Infrared spectroscopy of DSCB ring-containing molecules on Cu and silica surfaces shows that annealing-induced Cu-catalyzed DSCB ring opening and Cu-DSCB bonding, and strong siloxane bonding at the DSCB/SiO2 interface, are the main interfacial toughening mechanisms. Vacuum annealing DSCBTOS assembled on Cu for Tanneal ≥100 °C reduces Cu (II) to Cu (I) or Cu (0) state. The temperature regime for adhesion enhancement and surface copper oxide reduction coincide with that of Cu catalyzed DSCB ring opening.
3:15 PM - D7.3
Self Assembly of Organic Monolayers as Protective and Conductive Bridges for Nanometric Surface-Mount Applications
Ilia Platzman 1 , Hossam Haick 1 2 , Rina Tannenbaum 1 2 3 Show Abstract
1 Chemical Engineering, Technion- Israel Institute of Technology, Haifa Israel, 2 Russell Berrie Nanotechnology Institute, Technion – Israel Institute of Technology, Haifa Israel, 3 School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
State-of-the-art surface mount technology (SMT) involves the use of stencil-printing process, in which a thin layer of solder-paste is deposited on copper (Cu) substrates and/or pads, followed by the positioning the components of interest onto their designated places. While this technology can be applied successfully in the macro- and micro-scale regimes, it fails when either the lateral and/or horizontal dimensions of the devices approaches the nanometric scale. In this work we adapted a new SMT that operates at the molecular/nanoscale level, which consists of the use of conductive and precision molecular bridges between the Cu pads and components, to form a monolayer that could also inhibit the oxidation of the Cu surface. We did so by examining the formation of a series of symmetric X-phenyl-X, (X= -NC, -CH=CH-COOH, -N=C=O) SAMs on ultra smooth (~ 0.5 nm roughness) Cu surfaces and investigating the stability of the resulted surfaces to oxidation upon exposure to ambient air conditions. The results showed that the molecules were bound to the Cu substrate through only one of the terminal groups, while the other was oriented away from the substrate. Exposing the molecularly modified surfaces to ambient conditions showed dependence between the functionality of the phenyl-X molecules and the resistance to oxidation that was observed. Nevertheless, all molecularly modified surfaces exhibited higher oxidation resistance than the bare Cu. The conductive properties of molecularly modified surfaces were characterized by employing an assembly of top contact preparation methods, such as hanging drop mercury electrode (HDME), nanotransfer printing (nTP) of the Cu components and soft contact lamination. Preliminary results have shown that the tunneling was the dominant mechanism of charge transport. The tunneling decay parameter was depending mostly on molecule-Cu chemical bond and found to be in range from 0.2 to 0.5 1/A.Our findings imply that SAMs used in this study can serve as protective coatings for Cu and, furthermore, as conductive molecular bridges that can potentially bind circuital pads/components in a selective manner in micro and nanoelectronic applications.
3:45 PM - D7.5
Plasma-Assisted Etching of Copper Films at Low Temperature
Fangyu Wu 1 , Dennis Hess 1 , Galit Levitin 1 Show Abstract
1 School of Chemical & Biomolecular Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Primarily due to the inability to form volatile etch products for Cu plasma etching at temperatures <200° C, no effective subtractive etch process for Cu has been reported. We have developed a low temperature (<20° C), reactive plasma etch process for copper films in an attempt to mitigate the size effect in electrical resistivity, a critical limitation to future integrated circuit device generations. As proposed previously by a thermochemical analysis of the Cu-Cl-H system, the plasma etch process is executed in two steps. In the first step, copper films are exposed to a Cl2 plasma to preferentially form CuCl2, which is believed to be volatilized as Cu3Cl3 by exposure to a H2 plasma in the second step. Both thin (9nm) and thicker films (400nm) have been etched with this sequence as established by x-ray photoelectron spectroscopy (XPS) analysis of sample surfaces before and after etching. Several cycles consisting of a Cl2 plasma followed by a H2 plasma, were needed to completely etch the thicker films. The effect of Cl2 and H2 plasma exposure times on chloride (CuClx) formation and removal has also been investigated by XPS to determine the controlling process step. In addition, Cu samples masked with photoresist (PR) have been etched to investigate the ability of this new etch process to form patterns, Etch anisotropy, etched surface roughness, and line edge roughness have also been investigated. Plasma etch conditions such as temperature, pressure and power level have been varied to gain insight into the influence of these parameters on etch rates and etch profiles.
4:30 PM - **D7.6
Multi-layer Graphene Grown by Low Temperature CVD for Advanced Carbon-based Interconnects.
Mizuhisa Nihei 1 2 5 , Motonobu Sato 1 2 5 , Daiyu Kondo 1 2 5 , Shintaro Sato 1 2 5 , Shuichi Ogawa 3 5 , Yuji Takakuwa 3 5 , Eiji Ikenaga 4 5 , Yuji Awano 1 2 Show Abstract
1 , Fujitsu Laboratories Ltd., Atsugi Japan, 2 , Fujitsu Limited, Atsugi Japan, 5 , CREST/JST, Tokyo Japan, 3 , Tohoku Univ., Sendai Japan, 4 , JASRI, Hyogo Japan
With shrinking dimensions of devices, resistivity and electromigration (EM) have become important issues for large-scale integrated (LSI) circuits in hp32nm technology node and beyond. In the case of conventional copper (Cu) interconnects, the resistivity increases and the EM reliability deteriorates as the line width decreases. Carbon-based materials such as carbon nanotubes (CNT) and graphene nanoribbons (GNR) have been studied as an interconnect material instead of Cu, because of their lower resistivity  and intrinsically higher EM tolerance compared with Cu. We succeeded in fabricating multi-layer graphene by using chemical vapor deposition (CVD) methods which are more suited to the mass production techniques of LSI circuits. In this study, we investigated the crystal structure and the electrical properties of multi-layer grapheme grown by CVD methods, as compared with that by cleaving bulk Highly Oriented Pyrolytic Graphite (HOPG). We used two types of CVD method for growing multi-layer graphene on silicon substrates. One is a thermal CVD method using Fe catalyst films. The growth temperature was 620°C and the source gas was a mixture of acetylene (C2H2) and argon (Ar). We succeeded in growing multi-layer graphene, having the same crystal’s faces within the grain, on Fe films. We measured the grain size of the multi-layer graphene by using an Electron Backscatter diffraction Pattern (EBSP). From the EBSP measurement, the grain size was measured to be about 100 nm, which is smaller than that of HOPG, which has a grain size of several micrometers. The other CVD method is a photoemission-controlled plasma CVD method without using any catalysts, in which DC discharge plasma is controlled by photoemission induced by UV irradiation. The growth temperature was 700°C and the source gas was a mixture of methane (CH4) and argon (Ar). From the TEM observation, polycrystalline graphite particles are connected to each other in a complicated network of graphene sheets. We also measured the I-V characteristics of multi-layer graphene with four terminal metal electrodes, which are formed on the top graphene layer. In the case of HOPG, the I-V results have linear characteristics, which indicate that good ohmic contacts are realized between metal electrodes and the graphene layer. We developed multi-layer graphene growth technology, in which we use two types of CVD methods with and without metal catalyst films. Although we need to expand the grain size, our CVD technologies have a potential to realize future multi-layer graphene interconnects, and are suited to LSI’s fabrication processes.Acknowledgements: We would like to thank Dr. H. Watanabe, Research Supervisor of CREST and Dr. N. Yokoyama at Fujitsu Laboratories Ltd. for their support and useful suggestions.References:  Azad Naeemi and James D. Meindl, IEEE International Interconnect Technology Conference 2008, pp. 183–185.
5:00 PM - D7.7
Single-Layer and Bi-Layer Graphene Interconnects: High-Temperature Performance.
Qinghui Shao 1 , Guanxiong Liu 1 , Desalegne Teweldebrhan 1 , Alexander Balandin 1 Show Abstract
1 Nano-Device Laboratory, Department of Electrical Engineering and Materials Science and Engineering Program, University of California - Riverside, Riverside, California, United States
Graphene, the latest of all discovered carbon allotropes, consists of separate atomic planes of sp2-bound atoms. It manifests extremely high room temperature electron mobility and superior heat conduction properties . Graphene layers have been recently proposed for interconnect applications owing to their excellent current conduction and possibility to avoid the electro-migration problem. Since conventional VLSI circuits operate at elevated temperatures it is important to understand how the electrical resistance of graphene interconnects changes as temperature increases. Here we report the results of the experimental investigation of the electrical resistance of graphene biased near the charge-neutrality point. The prototype graphene interconnect structures were fabricated from the single-layer graphene (SLG) and bi-layer graphene (BLG) produced by mechanical exfoliation from bulk graphite. The number of atomic layers was determined using the micro-Raman spectroscopy . Graphene layers have been placed on Si substrates with the electrically insulating oxide films grown on top of them. A set of SLG and BLG resistors contacted by platinum (Pt) electrodes have been fabricated with the focused ion beam (FIB) system. The temperature was controlled externally through the hot chuck. The measurements have been carried out in regular atmosphere. It was found that as temperature increases from 300 to 500K the resistance of the SLG and BLG graphene interconnects drops down by 30% and 70%, respectively . The temperature dependence of the resistance was explained by the thermal generation of the electron-hole pairs in the conditions when the carrier mobility in graphene is limited by the defect scattering rather than phonon scattering. Such a dependence is opposite from the one observed in metals. In metals the number of charge carriers does not change with temperature but the interaction with phonons increases. The observed resistance quenching in the prototype graphene interconnects can have important implications. The resistance quenching in the relevant temperature range may lead to a significant reduction in the power dissipation. The work in Balandin group was supported, in part, by DARPA – SRC Focus Center Research Program (FCRP) through its Interconnect Focus Center (IFC).  A. A. Balandin, S. Ghosh, W. Bao, I. Calizo, D. Teweldebrhan, F. Miao and C.N. Lau, "Superior thermal conductivity of single-layer graphene," Nano Letters, 8, 902 (2008). I. Calizo, F. Miao, W. Bao, C. N. Lau and A. A. Balandin "Variable temperature Raman microscopy as a nanometrology tool for graphene layers and graphene-based devices," Appl. Phys. Lett., 91, 071913 (2007). Q. Shao, G. Liu, D. Teweldebrhan and A. A. Balandin, "High-temperature quenching of electrical resistance in graphene interconnects," Appl. Phys. Lett., 92, 202108 (2008).
5:15 PM - D7.8
Rational Carbon Nanotube Growth for Interconnect via Fabrication.
Xuhui Sun 1 , Tsutomu Saito 1 , Ke Li 1 , Dinh Nguyen 1 , Cary Yang 1 Show Abstract
1 Center for Nanostructures, Santa Clara University, Santa Clara, California, United States
The inevitable limits in performance and reliability of copper arising from electromigration, significant increase in resistivity of nanoscale interconnects, and fabrication difficulties from filling up ultrafine via holes have created interest in the search for novel one-dimensional nanomaterials as potential replacements in nanoscale applications. Carbon nanotube (CNT) has been investigated as candidate material to replace or augment the existing copper-based technologies for via interconnects, due to their high current capacity, structural strength, ballistic transport, and high aspect ratio. For use of CNT in interconnect via technology, their rational growth with desirable morphology and low resistance is critical and urgently needed. Although low-resistance CNT vias have been reported, the effects of CNT growth parameters on the CNT vias resistance have not been well understood. In this paper, we present a systematic study of a number of growth parameters such as choice of catalysts (e.g. Ni, Fe, Co, etc.) and pretreatment conditions, growth temperature and plasma power, and underlayer metal selection, which have been found to be essential to the rational growth of CNT using plasma-enhanced chemical vapor deposition (PECVD). Further, these parameters critically impact the growth rate, density, diameter distribution, alignment, nanostructure, and ultimately the resistance of CNT via. For example, very different growth rates of CNTs are obtained for different combinations of catalysts and underlayer metals. The density of CNT is increased by suitable thermal annealing and plasma-etch treatments of the catalysts prior to growth. The high-resolution transmission electron microscopy (HRTEM) images show that the Fe-catalyzed CNT has higher degree of graphitization than Ni-catalyzed CNT, while the latter exhibits similar qualities under a wide range of growth conditions (e.g. varying catalyst thickness and underlayer material). The interconnect vias have been fabricated based on this growth study and via resistance as well as individual CNT resistance inside the via have been measured. The CNT growth parameters are correlated with the measured via resistance, yielding a useful scheme for characterizing the growth process. The resulting improved CNT growth processes lead to fabrication of higher performing interconnect vias.
5:30 PM - D7.9
Contact Resistance in Carbon Nanotube Interconnect Vias.
Ke Li 1 , Xuhui Sun 1 , Raymond Wu 1 , Wen Wu 1 , Shoba Krishnan 1 , Cary Yang 1 Show Abstract
1 Center for Nanostructures, Santa Clara University, Santa Clara, California, United States
Copper interconnect technology is rapidly approaching its scaling limit because of increasing resistivity, reliability concerns due to electromigration, and excessive power dissipation related to ever-increasing clock frequencies. One viable alternative to copper is carbon nanotube (CNT). Before CNT can be used in next-generation integrated circuits, its electrical and thermal properties of CNTs must first be studied. One of the most important information that is needed in this area, and yet the least studied, is the contact resistance between the CNTs and the metal layers in a vertical interconnect via. Minimizing contact resistance is the key issue in the interconnect fabrication process, especially when the dimension is in the nanoscale.The purpose of this paper is to study the contact resistance between vertically grown CNTs and the base metal in the vias. Following the bottom-up approach of interconnect processes in the semiconductor industry, we design and fabricate a via test structure to extract the contact resistance. Since unlike the CNT resistance, the contact resistance is not a function of length, it can be extracted by varying the via (CNT) length within the same test structure. CNTs are first grown on a terrace-patterned test structure with a metal underlayer, followed by TEOS SiO2 deposition, CMP process, and top metal electrode deposition to obtain the CNT via arrays with different lengths. By measuring the resistances of CNT vias with different lengths, the contact resistance can be extracted from the resistance vs. length plot. In addition, the contact resistance between a single CNT and the base metal has also been obtained using the atomic force microscopy (AFM) current-sensing technique. We find that the contact resistance, usually a few kΩ for each CNT, dominates the total resistance of the CNT via in our process. By investigating the relationship between contact resistances and various combinations of catalysts and underlayer metals, as well as the effects of other CNT growth conditions, the contact resistance in the via structure can be reduced significantly.
5:45 PM - D7.10
Integration of Hollow Metal Waveguides and Beam Splitters for Photonic Interconnect.
Jong-Souk Yeo 1 , Robert Bicknell 1 , Pavel Kornilovitch 1 , Lenward Seals 1 , Laura King 1 , Michael Tan 2 , Paul Rosenberg 2 , Sagi Mathai 2 , Huei-Pei Kuo 2 Show Abstract
1 Imaging and Printing Group, Hewlett-Packard Company, Corvallis, Oregon, United States, 2 HP Labs, Hewlett-Packard Company, Palo Alto, California, United States
As data rates continue to increase in high performance computer systems and networks, it is becoming more difficult for copper based interconnects to keep pace. An alternative approach to meet these requirements is to move to optical based interconnect technologies, which offer higher bandwidth, lower signal distortion, and lower power requirements. Integration, advanced packaging, and disruptive architecture for hybrid optical and electrical solutions are required to achieve performance and cost targets with the optical technologies. Addressing challenges from board-to-board to chip-to-chip photonic interconnect requires a number of enabling photonic components such as low cost waveguides, splitters, couplers in addition to the active components that are becoming cost-effective nowadays. In order to meet the stringent requirements of high performance at low cost (<$1/Gbps), manufacturable waveguide and splitter technologies have been investigated with an emphasis on novel hollow core metallic waveguides (HMWGs). A typical HMWG is fabricated as a trench in a substrate (such as silicon), metallized with silver, and enclosed with a silver metallized cover. These waveguides have demonstrated very low optical losses of <0.05 dB/cm, low dispersion, ease of coupling, temperature stability, and the capability to transmit at the data rates of well in excess of 10 Gbps. Along with low loss waveguides, the design of optical bus architecture for on-board application requires a number of optical splitters with precise split ratios, low excess loss (<0.25 dB), and polarization insensitivity. HMWGs and beam splitters are integrated while minimizing beam walk-off: by offsetting the outgoing waveguide, by introducing an additional symmetric optical element to shift the beam back to the original optical path, or by using pellicle beam splitter. We designed a microelectro-mechanical system (MEMS) based thin glass splitter and developed processes to make pellicle beam splitter coated with dielectric interference filters using glass thickness of 20 μm or less by wafer level bonding and thinning. These methods of pellicle splitters or walk-off compensation have been shown to effectively mitigate the losses and potentially provide low cost manufacturing options for photonic interconnects. The fabrication, modeling, characterization, and integration of the HWMGs and various types of splitters are discussed as basic building blocks to enable photonic interconnect solutions, for future generations of computer and server products.
Alfred Grill IBM T. J. Watson Research Center
Martin Gall Freescale Semiconductor
Francesca Iacopi IMEC
Junichi Koiki Tohoku University
Takamasi Usui Toshiba America Electronic Components, Inc
D8/F6: Joint Session: Interconnect and Packaging
Friday AM, April 17, 2009
Room 2003 (Moscone West)
9:30 AM - **D8.1/F6.1
Reconfigurable 3-D Integration and Super Chip.
Mitsumasa Koyanagi 1 Show Abstract
1 Department of Bioengineering and Robotics, Tohoku University, Sendai Japan
Three-dimensional (3-D) integration is the most promising technology to achieve a future advanced LSI since we can easily reduce the wiring length, the chip size and the pin capacitance by employing 3-D LSIs and consequently we can increase the signal processing speed and decrease the power consumption. We have developed 3-D integration technology based on wafer-on-wafer bonding method and fabricated several 3-D LSI prototype chips such as 3-D image sensor chip, 3-D shared memory, 3-D artificial retina chip and 3-D microprocessor chip. In the wafer-to-wafer 3-D integration technology, however, the overall chip yield exponentially decreases with an increase in the number of stacked layers. Furthermore, we cannot stack chips with deferent size and different thickness in the wafer-to-wafer 3-D integration technology. We have proposed a new 3-D integration technology based on reconfigured wafer-on-wafer bonding technique to solve these problems in the wafer-to-wafer 3-D integration technology. 3-D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100%. As a result, we can obtain a high production yield even after bonding many wafers. It is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3-D integration technology based on the reconfigured wafer-on-wafer bonding technique. We call this technology a reconfigurable 3-D integration technology. A batch self-assembly process using a multi-chip self-assembly machine is the key in our reconfigurable 3-D integration technology. We have developed a multi-chip self-assembly machine. A multi-chip picking-up holder can simultaneously pick up and transfer more than 500 chips in this machine. First, small volumes of aqueous liquid are coated on hydrophilic bonding areas formed on an 8-inch wafer and then a larger number of KGDs are roughly pre-aligned onto hydrophilic bonding areas on the 8-inch wafer. After that, the KGDs are released onto the bonding areas, and consequently, the many KGDs are quickly and precisely self-assembled onto the bonding areas by surface tension of the liquid. After evaporating the liquid at room temperature under ordinary pressure, these chips are directly and tightly bonded on the hydrophilic areas because these KGDs have hydrophilic SiO2 layer on their backside. We are aiming to realize a super chip using the reconfigurable 3-D integration technology with such self-assembly process. Various kinds of chips with different sizes such as MEMS chip, sensor chip, CMOS RF-IC, MMIC, power IC, control IC, analog LSI, and logic LSI are vertically stacked in a super chip.
10:00 AM - D8.2/F6.2
Low Temperature Direct Cu-Cu Immersion Bonding for 3D Integration.
Rahul Agarwal 1 , Wouter Ruythooren 1 , Ingrid DeWolf 1 Show Abstract
1 Process Technology, IMEC, Leuven Belgium
Die-to-die stacking is a key enabler in 3-D integration with high density and high speed interconnections. At IMEC direct metal-to-metal bonding for die stacking is being investigated as an alternative to solder bonding due to its advantages, such as low processing cost due to fewer processing steps and predictable reliability because of single metal joints. Unlike solder bonding, in direct metal-to-metal bonding there is no solder reflow which makes this technology very useful for tighter pitch bump formation. The purpose of this paper is to demonstrate immersion thermo-compression bonding for direct (as plated) Cu-Cu interconnects. High yield and high strength direct Cu-Cu thermo-compression bonds are obtained at temperatures as low as 175°C and results from high density micro-bumps will be presented. Cu-Cu thermo-compression bonding requires higher temperature and pressure to make electrical connections as compared to solder bonding (for eg. Cu-Sn). Bonding temperature and pressure can be reduced by conditioning the plated Cu bumps. Since there is no reflow of metal the surface roughness plays an important role and hence most of the low temperature Cu-Cu bonding results presented in literature have relied on surface planarization steps like CMP or diamond bit cutting to obtain a surface roughness of a few nanometers and/or on surface activation in plasma and bonding at ultra high vacuum [1-4]. In the immersion bonding method presented here, citric acid is present between the samples being bonded providing in-situ cleaning of the Cu surface during the bonding. As plated Cu bumps with average roughness of more than 200nm are successfully bonded at temperatures as low as 175°C. Bonding is performed on two different test devices. First test device with 40µm pitch peripheral array (480 interconnections distributed over 2 daisy chains) have 100% yielding devices at temperatures as low as 175°C and 10g/bump load. The second test device with 100µm pitch area array (2018 interconnections distributed over 9 daisy chains) give a bump chain yield ranging from 87% to 100% depending on the bonding process conditions. For reference, samples which are bonded without citric acid clean prior to bonding did not show any cohesion while samples which are bonded after citric acid clean (but no in-situ cleaning) give only 44% electrically yielding daisy chains. Hence the results indicate an important strong beneficial impact of the immersion bonding method.Reference:1.Gueguen P., et al., “Copper direct bonding for 3D integration,” IEEE IITC, 2008.2.Ruythooren W., et al., “Cu-Cu bonding alternative to solder based micro-bumping,” IEEE ECTC, 2007. 3.Arai K., et al., “A new planarization technique by high precision diamond cutting for packaging,” IEEE ISSM, 2004.4.Kim T. H., et al., “Low temperature Direct Cu-Cu bonding with low energy Ion activation method,” IEEE EMAP, 2001.
10:15 AM - D8.3/F6.3
Thermo-Mechanical Reliability of 3-D Interconnect with Through-Si-Vias.
Xuefeng Zhang 1 , Kuan-Hsun Lu 1 , Suk-Kyu Ryu 2 , Jay Im 1 , Rui Huang 2 , Paul Ho 1 Show Abstract
1 Microelectronics Research Center, UT Austin, Austin, Texas, United States, 2 Aerospace Engineering and Engineering Mechanics, UT Austin, Austin, Texas, United States
Three-dimensional integrated circuits with through silicon vias (TSVs) offer a solution to improve the device density and electical performance without scaling. However, process-induced thermal stresses around TSVs in 3-D interconnect structures raise serious reliability issues such as Si cracking and performance degradation of devices. Thermo-mechanical reliability was investigated using finite element analysis (FEA) combined with bending beam experiments. First a 3D TSV interconnect model was developed and verified using experimental results from bending beam measurements. After verification, the process-induced stresses in the 3D interconnect were calculated by FEA. The pitch-to-diameter ratio of the TSV and the die thickness were identified as important parameters in controlling the thermal stress distribution inside and near the TSVs. The surface stress in the Si was found to decrease as a function of distance from the fully filled Cu TSV but increase with the TSV diameter. Reducing the TSV pitch caused the stress fields from the adjacent vias to interact, which can lead to significant stress enhancement with a reduction of the pitch-to-diameter ratio less than 2.5. The effect of Si die thickness was also studied. The radial stress at the Si surface can increase by as much as 50% with the die thickness reducing from 200um to 20um. This indicates that die thickness can significantly influence the size of the keep-away zone for devices. Additional simulation results demonstrated that significant stress reduction can be achieved by optimizing the TSV interconnect structure, such as using partial Cu filling and adding a thin polymer buffer layer between Cu TSV and Si. Finally, silicon cracking induced by thermal stress interaction between TSVs was investigated. The critical cracking stress of silicon was found to depend on the maximum thermal load and the pitch to via diameter ratio. The crack driving force in silicon between TSVs was found to increase significantly with decreasing pitch-to-diameter ratio and will have to be considered in the design of the TSV structure.
10:30 AM - D8.4/F6.4
Failure Analysis and Process Improvement for Through Silicon Via Interconnects.
Bivragh Majeed 1 , Marc Van Cauwenberghe 2 , Deniz Tezcan 1 , Philippe Soussan 1 Show Abstract
1 IPSI, IMEC, Leuven Belgium, 2 AMPS, IMEC, Leuven Belgium
This paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV’s for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.
10:45 AM - D8.5/F6.5
Effects of Thinned Multi-stacked Wafer Thickness on Stress Distribution in the Wafer-on-a-Wafer (WOW) Structure.
Hideki Kitada 1 , Nobuyuki Maeda 1 , Koji Fujimoto 2 , Kousuke Suzuki 2 , Tomoji Nakamura 3 , Takayuki Ohba 1 Show Abstract
1 , The University of Tokyo, Tokyo Japan, 2 , Dai Nippon Printing, Kashiwa Japan, 3 , Fujitsu Laboratories Ltd, Atsugi Japan
Since conventional shrink scaling based on an empirical More's law has reached the limitation of manufacturability, performance, and power consumption, an alternative integration technology such as 3-dimentional processes is anticipated. Recently, novel through silicon via (TSV) integration process formed after wafer bonding based on wafer on-wafer (WOW) has been developed . The WOW process provides the wafer-scale 3D manufacturability and high productivity of chip integration. Because the WOW employ the thinned Si wafer (<20um) stack process, the TSV dry etching and the copper plating process can be simplified. In this report, the stress of multi stacked Copper-TSV/Si wafers and Copper/Low-k device structure was analyzed using Finite Element Method (FEM). The wafer was stacked with face to back by using the Cyclotene™ adhesive. And the TSV formation after bonding was developed by self-alignment process based on the BEOL process. Therefore, the TSV after bonding process enabled the low temperature process compared with the conventional metal-metal bump connection about 400 degree C. In the WOW process of wafer bonding and the TSV, a low temperature (250 degree C) process was expected to reduce the TSV stress more than general BEOL process (400 degree C). The FEM analysis result showed that the TSV stress was small in the case of low temperature via last process. Moreover, in the low aspect TSV structure, the result showed low internal stress in Cu-Via plug and low residual stress around copper via. This fact was an advantage for the reliability of the TSV structure by WOW process. Especially, the influence of stress on the device structure, such as Tr and BEOL interconnect, was comparatively small. This simulation result showed effectiveness of WOW process in the points of structural complex TSV and device deterioration by stress with TSV process. By using this process, it was succeeded in the fabrication of seven layer multi stacked of 20um thinned Si wafer with 30 um diameter and 80um pitch TSV. In addition, the electrical characteristic of the TSV chain with two levels in three layers WOW was confirmed without the failure. It is shown that via after bonding technique of the WOW base is very excellent method for the chip minimization of 3D-IC and reduction of TSV size. The electric characteristics and the stress analysis of TSV will discuss in this presentation. N. Maeda, et al. Proc. Advanced Metallization Conference (2008) p91-92.
11:30 AM - **D8.6/F6.6
Power Delivery, Signaling and Cooling in 3D Integrated Systems.
Muhannad Bakir 1 Show Abstract
1 MiRC, Georgia Tech, Atlanta, Georgia, United States
In this paper, we describe a novel 3D system that features low-cost and fully compatible electrical and fluidic I/O interconnects between strata. The electrical interconnects are used for power delivery and signaling between strata, and the fluidic interconnects are used to enable the rejection of heat from each stratum in the 3D stack. Each silicon die in the 3D stack contains the following features: 1) a monolithically integrated microchannel heat sink (MCHS); 2) through-silicon electrical vias (TSEVs) and through-silicon fluidic (hollow) vias (TSFVs); 3) solder bumps (electrical I/Os) and microscale polymer pipes (fluidic I/Os) on the side of the chip opposite to the microchannel heat sink. Microscale fluidic interconnection between strata is enabled by the combination of through-silicon fluidic vias and polymer pipe I/O interconnects. The chips are designed such that when they are stacked, each chip makes electrical and fluidic interconnection to the dice above and below. Consequently, power delivery and signaling can be supported by the electrical interconnects, and the heat removal from each stratum can be supported by the fluidic I/Os and microchannel heat sinks. Using the fluidic I/Os, the chip junction-to-ambient thermal resistance has been measured to be 0.24 C/W for a single chip.Due to the integrated microchannel heat sink and fluidic interconnects, the high-power chips can be placed anywhere in the 3D stack and are no longer restricted only to being at the top most layer for direct interfacing to a heat sink. This is in sharp contrast to other 3D integration technologies. The thermal resistance and pressure drop in the microchannel heat sink are both a function of the channel geometry; for example, increasing channel height reduces thermal resistance and pressure drop. However, as the microchannel heat sink height increases, so does the aspect ratio of the TSEVs (assuming fixed diameter). Unlike other 3D integration technologies that seek to thin down the silicon wafer to as small a thickness as possible before mechanical handling becomes challenging (~30-100μm), the microchannel heat sink requires a silicon wafer thickness of ~ 250 μm. This is an important fundamental difference and imposes different constraints on TSEV fabrication and optimization. To this end, we have developed novel processes for the integration of a MCHS and TSEVs in a Si wafer. Moreover, modeling and optimization algorithms are used to provide optimal designs for the electrical and thermal interconnect networks in a 3D system based on various performance constraints. The impact of TSV density on power supply noise in a 3D stack is also shown.
12:00 PM - D8.7/F6.7
Copper Deposition Technology for Thru Silicon Via Formation Using Supercritical Carbon Dioxide Fluids Using a Flow Type Reaction System.
Masahiro Matsubara 1 , E. Kondoh 1 Show Abstract
1 , University of Yamanashi, Kofu Japan
New interconnect process technologies are required to fabricate high performance LSIs. One of the crucial technological targets is the formation of MEMS-based thru Si vias in 3D IC. Cu electroplating is the most popular deposition technology being currently investigated; however, the deposition technology in supercritical fluids is becoming of crucial interest as a replacement of electroplating because of its excellent penetration capability of supercritical fluids. In this study, Cu deposition in thru via was carried out using a flow-type deposition processor that was designed to enable long time deposition [1,2].
A precursor, Cu(dibm)2, was dissolved in acetone and was supplied to a reaction chamber continuously. We used a one-dimensional deposition reactor. Cu films were fomed directly on Si having TSV holes formed by a usual BOSCH method. Deposition temperature was varied from 180 degC to 280 degC, and the precursor and H2 concentrations were fixid at 0.0292 mol%, 1.53 mol% respectively. Deposition time was 60 min. Cross-sectional view of Cu deposited in thru via at 220degC revealed Cu film reached 129 µm in a hole of 10 µm in dia.
The temperature dependence of the Cu-coating depth was studied. At 180 degC, Cu film reached full-depth (350 µm) but its thickness was very small. As the temperature increased, the maximum depth was decreased, whereas the film thickness increased. At 280 degC, a large film thickness at the via opening decreased rapidly with depth. At lower temperatures, the film thickness profiles became less depth-dependent. These experimental results were compared with numerically simulated results.
 M. Matsubara and E. Kondoh, 40th Autumn Meeting of Society of Chemical Engineering Japan, (Sep. 2008)
 M. Matsubara, M. Hirose, K. Tamai, and E. Kondoh, submitted to J. Eelctrochem. Soc.
12:15 PM - D8.8/F6.8
Fully Low Temperature (350°C) Processed Si PMOSFET with Poly-Ge Gate, Radical Oxidation of Gate-Oxide and Schottky Source/Drain for Monolithic 3D-ICs.
Munehiro Tada 1 2 , Jin-Hong Park 1 , Duygu Kuzum 1 , Gaurav Thareja 1 , Yoshio Nishi 1 , Krishna Saraswat 1 Show Abstract
1 , Stanford University, Palo Alto, California, United States, 2 , NEC corporation, Sagamihara Japan
The 3D integration paradigm addresses the power/delay issue of wires in devices by realizing shorter interconnect line length as well as higher logic density. A more promising 3D approach is monolithic stacking whereby active devices are built in back end of the line. The advantages of such approach are that it can achieve high vertical via density and scale geometries at the same rate as the CMOS technology. The monolithic 3D requires process temperature below 350°C in order not to damage the underlying devices and interconnects. In this paper, we have developed a novel low temperature LPCVD Ge growth technique and in-situ dopants activation for a gate electrode coupled with fully low temperature gate oxide and Schottky S/D processes.Conventionally, a LPCVD Si layer deposited at 500°C has been used as a seed for the Ge growth on SiO2. We have newly developed a technique to grow Ge on SiO2 below 350°C, featuring a diborane pretreatment. Depending on the partial pressure of diborane in the pretreatment, the substrate SiO2 is contentiously covered by boron and the Ge film is uniformly grown with a smooth surface (RMS~1nm). Weaker B-H bonds of B2H6 than Si-H bonds of SiH4 promote attachments of boron atoms on the SiO2 surface.Boron and phosphorous are in-situ doped using B2H6 and PH3 during the Ge growth and activated at 310°C and 350°C. By increasing the diborane flow ratio, the resistivity of the poly-Ge film decreases and significantly low resistivity of ~1mΩcm is obtained around the 0.2 diborane ratio. The crystalinity of Ge (111) and deposition rate also depend on the diborane flow ratio and excess doping makes the phase amorphous, resulting in high resistivity. This low resistive Ge is useful for gate electrodes on Fin and/or Gate-all-around type transistors due to the conformal electrode deposition by LPCVD. Here, we select the heavily boron doped Ge film for a p-type gate electrode and demonstrates the in-situ dopants activation in the fully low temperature planer type transistor.Si PMOS transistors using the in-situ boron activated Ge gate electrode are integrated with a radical oxidizing gate oxide and Schottky Ni, Pd or Pt silicide S/D at temperatures below 350°C. A 8.3nm gate oxide is formed by using SPA plasma with 2.45GHz microwave and O2/Ar chemistry at 350°C. The junctions of NiSi, PdSi and PtSi to n-Si are formed below 350°C. Significantly high forward/reverse current ratio of the diodes is obtained in the PtSi/n-Si junction, in which Ioff of the transistor is reduced below 10-14A/μm. Characteristics of the Si PMOSFET show excellent Ion/Ioff ratio over 107, low gate leakage and steep SSmin=77.9mV/dec. The estimated hole mobility is ~150cm2/Vs, which is compatible to a thermally grown oxide at 850°C. The low temperature Ge growth, gate oxide and Schottky S/D technologies are indispensable for a low thermal budget processing below 350°C, enabling to fabricate a transistor within metal interconnects for 3D applications.
12:30 PM - D8.9/F6.9
Metal-Induced Dopants Activation (MIDA) on Amorphous Germanium for Monolithic 3D-ICs.
Jin-Hong Park 1 , Munehiro Tada 1 2 , Kyeongran Yoo 1 , Woo-Shik Jung 1 , H. -S. Philip Wong 1 , Krishna Saraswat 1 Show Abstract
1 Electrical Engineering, Stanford University, Stanford, California, United States, 2 Device Platforms Research Laboratories, NEC corporation, Sagamihara, Kanagawa, Japan
Germanium (Ge), by virtue of its low melting point, is a highly suitable material for 3D-ICs, which requires a low process temperature to prevent damaging the underlying devices and interconnects. A critical aspect currently plaguing Ge transistor integration for 3D application is the lack of dopant activation technique at sub-400°C. In this work, we demonstrate low temperature boron (B) and phosphorus (P) activation in amorphous (α)-Ge using metal-induced crystallization (MIC). This method can prove to be indispensible for gate, source, and drain formations at a low temperature required for 3D ICs. A 200nm thick α-Ge is deposited at 300°C by LPCVD on top of a thermally grown SiO2 on a Si (100) substrate. Then p- and n- type Ge films were created by implanting B (49BF2, 40keV, and 4e15cm-2) and P (P31, 90keV, and 4e15cm-2) ions. In total, three kinds of α-Ge films (undoped, B doped, and P doped) are prepared to investigate dopants activation. Reference (or control) samples are created by annealing each of these three types of samples for 1 minute at 600°C. A 5nm thick metal film is subsequently deposited on the α-Ge films to study dopants activation at a low temperature using MIC process. The samples are isothermally annealed in a N2 ambient for 1-3 hours at below 360°C. The annealed samples are then analyzed by x-ray diffraction (XRD), resistivity measurement, and transmission electron microscopy (TEM) systems. We first investigated the temperature at which MIC process occurs with eight different metals (Pd, Cu, Ni, Au, Co, Al, Pt, and Ti) on undoped Ge film after annealing for 1 hour at various temperatures (300-450°C). Then, we selected five metals (Pd, Cu, Ni, Au, and Co) which have a MIC process temperature below 380°C, having no self-nucleation in the α-Ge film. The selected MIC samples show a lower XRD peak intensity and a broader width at the half maximum points of Ge (111) XRD peak (thus, a lower crystal grain size) than the sample thermally annealed for 1 minute at 600°C. Because B and P atoms in the α-Ge film are rearranged and activated during the MIC process, we can conclude that B (with the above five metals) and P (with Co) atoms were activated during the MIC process at below 360°C. We predict that the reason why Co MIC process only activates P atoms is compensation process between P atoms and metals, mostly working as acceptor-like traps. The metal themselves also seem to contribute to a slight reduction in the resistivity of the film, and the amount of activated B and P atoms by MIC process are expected to be lower than one activated by thermal annealing process at 600°C. The low temperature dopants activation technique featuring the MIC process is demonstrated for (1) a Ge gate electrode in a Si P-MOSFET and (2) Ge N+/P & P+/N junction diodes in Ge MOSFETs. This technique is promising for integrating Ge transistors at low temperatures which is a critical requirement for 3D ICs.