Meetings & Events

 

Spring 2009 Logo2009 MRS Spring Meeting & Exhibit



April 13-17, 2009
| San Francisco
Meeting Chairs: Paul R. Besser, Peter Fratzl, Nicola Spaldin, Terry M. Tritt

Symposium F : Packaging, Chip-Package Interactions, and Solder Materials Challenges

2009-04-15   Show All Abstracts

Symposium Organizers

Paul A. Kohl Georgia Institute of Technology
Paul S. Ho University of Texas-Austin
Patrick Thompson Texas Instruments, Inc.
Rolf Aschenbrenner Fraunhofer IZM
F1: Mechanics and Chip-Package Interaction
Session Chairs
Paul Ho
Paul Kohl
Wednesday AM, April 15, 2009
Room 2002 (Moscone West)

9:30 AM - **F1.1
Mechanical Scaling Trends and Methods to Improve Reliability of Packaged Interconnect Structures.

Michael Lane 1
1 Department of Chemistry, Emory & Henry College, Emory, Virginia, United States

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10:00 AM - **F1.2
Cracking and Delamination in Interconnect Structures

Thomas Shaw 1 , X. Liu 1 , E. Liniger 1 , S. Hosadurga 2 , D. Goldfarb 1 , M. Lane 3 , G. Bonilla 1
1 IBM Research, IBM, Yorktown Heights, New York, United States, 2 IBM in Albany Nano Technology Research Center, IBM, Albany, New York, United States, 3 Department of Chemistry, Emory and Henry College, Emory, Virginia, United States

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10:30 AM - F1.3
Probing the Mechanics of Complex Multilayer Structures for Emerging Technologies.

Alexander Hsing 1 , Reinhold Dauskardt 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States

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10:45 AM -
BREAK

11:15 AM - **F1.4
Impact of Chip-Package Interactions on Mechanical Reliability of Advanced Interconnects.

Rui Huang 1 , Xuefeng Zhang 2 , Suk Kyu Ryu 1 , Se Hyuk Im 1 , Paul Ho 2
1 Department of Aerospace Engineering and Engineering Mechanics, University of Texas at Austin, Austin, Texas, United States, 2 Laboratory of Interconnect and Packaging, University of Texas at Austin, Austin, Texas, United States

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11:45 AM - F1.5
Improved All-Copper Flip-Chip Connections: Moving Towards Manufacturability.

Tyler Osborn 1 , C. Hunter Lightsey 1 , Paul Kohl 1
1 School of Chemical and Biomolecular Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States

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12:00 PM - F1.6
High Aspect Ratio, Aqueous-Develop, Photosensitive Polynorbornene Dielectric for Packaging and Interconnect Applications.

Venmathy Rajarathinam 1 , C. Hunter Lightsey 1 , Tyler Osborn 1 , Brian Knapp 2 , Edmund Elce 2 , Sue Ann Bidstrup Allen 1 , Paul Kohl 1
1 Chemical Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States, 2 , Promerus LLC, Brecksville, Ohio, United States

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12:15 PM - F1.7
A Novel X-ray Diffraction-based Technique for Complete Stress State Mapping of Packaged Silicon Dies

Balaji Raghothamachar 1 , Vishwanath Sarkar 1 , Vladimir Noveski 2 , Michael Dudley 1 , Sujit Sharan 2
1 Materials Science & Engineering, Stony Brook University, Stony Brook, New York, United States, 2 , Intel Corporation, Chandler, Arizona, United States

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12:30 PM - F1.8
Viscoelastic Modeling and Reliability Assessment of Microelectronics Packages.

Aditya Karmarkar 1 , Charlie Zhai 2 , Xiaopeng Xu 3 , Xiao Lin 3 , Greg Rollins 3 , Victor Moroz 3
1 TCAD, Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh, India, 2 Silicon Operations, Nvidia, Santa Clara, California, United States, 3 TCAD, Synopsys, Inc., Mountain View, California, United States

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2009-04-17   Show All Abstracts

Symposium Organizers

Paul A. Kohl Georgia Institute of Technology
Paul S. Ho University of Texas-Austin
Patrick Thompson Texas Instruments, Inc.
Rolf Aschenbrenner Fraunhofer IZM
F6/D8: Joint Session: Interconnect and Packaging
Session Chairs
Alfred Grill
Paul Ho
Friday AM, April 17, 2009
Room 2003 (Moscone West)

9:30 AM - **F6.1/D8.1
Reconfigurable 3-D Integration and Super Chip.

Mitsumasa Koyanagi 1
1 Department of Bioengineering and Robotics, Tohoku University, Sendai Japan

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10:00 AM - F6.2/D8.2
Low Temperature Direct Cu-Cu Immersion Bonding for 3D Integration.

Rahul Agarwal 1 , Wouter Ruythooren 1 , Ingrid DeWolf 1
1 Process Technology, IMEC, Leuven Belgium

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10:15 AM - F6.3/D8.3
Thermo-Mechanical Reliability of 3-D Interconnect with Through-Si-Vias.

Xuefeng Zhang 1 , Kuan-Hsun Lu 1 , Suk-Kyu Ryu 2 , Jay Im 1 , Rui Huang 2 , Paul Ho 1
1 Microelectronics Research Center, UT Austin, Austin, Texas, United States, 2 Aerospace Engineering and Engineering Mechanics, UT Austin, Austin, Texas, United States

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10:30 AM - F6.4/D8.4
Failure Analysis and Process Improvement for Through Silicon Via Interconnects.

Bivragh Majeed 1 , Marc Van Cauwenberghe 2 , Deniz Tezcan 1 , Philippe Soussan 1
1 IPSI, IMEC, Leuven Belgium, 2 AMPS, IMEC, Leuven Belgium

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10:45 AM - F6.5/D8.5
Effects of Thinned Multi-stacked Wafer Thickness on Stress Distribution in the Wafer-on-a-Wafer (WOW) Structure.

Hideki Kitada 1 , Nobuyuki Maeda 1 , Koji Fujimoto 2 , Kousuke Suzuki 2 , Tomoji Nakamura 3 , Takayuki Ohba 1
1 , The University of Tokyo, Tokyo Japan, 2 , Dai Nippon Printing, Kashiwa Japan, 3 , Fujitsu Laboratories Ltd, Atsugi Japan

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11:00 AM -
BREAK

11:30 AM - **F6.6/D8.6
Power Delivery, Signaling and Cooling in 3D Integrated Systems.

Muhannad Bakir 1
1 MiRC, Georgia Tech, Atlanta, Georgia, United States

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12:00 PM - F6.7/D8.7
Copper Deposition Technology for Thru Silicon Via Formation Using Supercritical Carbon Dioxide Fluids Using a Flow Type Reaction System.

Masahiro Matsubara 1 , E. Kondoh 1
1 , University of Yamanashi, Kofu Japan

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12:15 PM - F6.8/D8.8
Fully Low Temperature (350°C) Processed Si PMOSFET with Poly-Ge Gate, Radical Oxidation of Gate-Oxide and Schottky Source/Drain for Monolithic 3D-ICs.

Munehiro Tada 1 2 , Jin-Hong Park 1 , Duygu Kuzum 1 , Gaurav Thareja 1 , Yoshio Nishi 1 , Krishna Saraswat 1
1 , Stanford University, Palo Alto, California, United States, 2 , NEC corporation, Sagamihara Japan

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12:30 PM - F6.9/D8.9
Metal-Induced Dopants Activation (MIDA) on Amorphous Germanium for Monolithic 3D-ICs.

Jin-Hong Park 1 , Munehiro Tada 1 2 , Kyeongran Yoo 1 , Woo-Shik Jung 1 , H. -S. Philip Wong 1 , Krishna Saraswat 1
1 Electrical Engineering, Stanford University, Stanford, California, United States, 2 Device Platforms Research Laboratories, NEC corporation, Sagamihara, Kanagawa, Japan

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