Symposium Organizers
Michael Dudley State University of New York-Stony Brook
Stephen E. Saddow University of South Florida
Edward Sanchez Dow Corning Compound Semiconductor
Feng Zhao University of South Carolina
B1: Bulk Growth
Session Chairs
Tuesday PM, April 06, 2010
Room 2004 (Moscone West)
9:30 AM - **B1.1
Growth of Large Diameter 6H SI and 4H n+ SiC Single Crystals.
Ilya Zwieback 1 , Avi Gupta 1 , Ping Wu 1 , Varatharajan Rengarajan 1 , Xueping Xu 1 , Murugesu Yoganathan 1 , Chris Martin 1 , Ejiro Emorhokpor 1 , Andy Souzis 1 , Tom Anderson 1
1 WBG, II-VI Incorporated, Pine Brook, New Jersey, United States
Show AbstractSiC single crystals are grown at II-VI by the seeded sublimation technique. The process has been optimized to support commercial production of high-quality 3” diameter 6H SI and 4H n+ substrates. Over the last several years, the process has been scaled up to allow transition to 100 mm substrates. The growth process incorporates special elements aimed at achieving uniform sublimation of the source, slightly convex growth interface, steady growth rate, uniform doping and reduced presence of background impurities. Semi-insulating 6H substrates are produced using precise vanadium compensation. Vanadium doping is optimized to yield SI material with very high resistivity and low capacitance.Crystal quality of the substrates is evaluated using a wide variety of techniques. Specific defects, their interaction and evolution during growth are described with emphasis on micropipes, dislocations and carbon inclusions. The current quality of the 6H SI and 4H n+ crystals grown at II-VI is summarized.
10:00 AM - B1.2
Effect of Doping on the Plasticity of Homoepitaxied 4H-SiC Single Crystals: A Microindentation Study.
Alexandre Mussi 1 3 , Jean-Luc Demenet 1 , Tanguy Rouxel 2 , Jacques Rabier 1
1 PhyMat, UMR 6630 CNRS-Université de Poitiers, 86962 Futuroscope Chasseneuil Cedex France, 3 Laboratoire de Structure et Propriétés de l'Etat Solide , Université Lille1, 59655 Villeneuve d'Ascq France, 2 LARMAUR, Université Rennes1, 35042 Rennes Cedex France
Show AbstractMany examples in materials science show that a low content of impurities can play an important role on plasticity. In semiconductors, such as silicon and GaAs, it is well established that doping acts on dislocation mobility through electronic effects and as a consequence yields to a modification of the brittle-to-ductile transition temperature. As far as mechanical or electronic applications of silicon carbide are concerned, it is of interest to check whether such a phenomenon can be evidenced in this material. In this context an instrumented microindentation study has been performed on 10 μm thick homo-epitaxied 4H-SiC single crystals on the basal plane: intrinsic (Ni≈ 6.1013 cm-3), n-type (N, Nn ≈ 8.1017 cm-3) and p-type (Al, Np ≈ 4.1017 cm-3). Two sets of experiments have been performed applying respectively loads up to 50 and 300 mN. At room temperature, the analysis of both pop-in effect and integrated area under the indentation curve clearly reveals different mechanical behaviors as a function of electronic doping. These results as well as those of indentation experiments as a function of temperature will be discussed and compared to those relevant to silicon and GaAs.
10:15 AM - B1.3
Boule Shape Dependence of Shear and von-Mises Stress Distributions in Bulk SiC During PTV Growth.
Roman Drachev 1 , Darren Hansen 1 , Mark Loboda 1
1 Compound Semiconductor Solutions, Dow Corning Corp., Auburn, Michigan, United States
Show AbstractMagnitude and special uniformity of shear and von-Mises stress distributions during PVT (Physical Vapor Transport) growth of bulk SiC (Silicon Carbide) are among the major factors that determine structural quality of the grown material. While shear stress characteristic values define generation of dislocations and their movement, which can lead to formation of micropipes (the most undesirable SiC device killing defects), von-Mises stress characteristics become important in terms of preventing SiC boules from cracking during the later stages of wafer fabrication. Besides the fact that the stress magnitude and its uniformity depends on the temperature distribution within the growing boule and thermo-mechanical properties of the materials that are in direct contact with the crystal during the process of growth, those stress characteristics also depend on the shape factors of the growing boule such as seed diameter, growth front shape, height and inclination angle of the crystal side surface. Although it is very difficult, in practice, to separate effects of all the contributing factors on the stress characteristics, it can be done using numerical modeling. In this study we focused on the boule shape dependence of shear and von-Mises stress distributions in growing SiC boules.The project was completed in the form of 2x4 DOE (Design of Experiment) with the seed diameter, side surface height, height of the growth front and inclination angle of the side surface as the DOE factors while the method of the crystal suspension, reference temperature, axial and radial temperature gradients at the back of the boule and growth front surface were fixed. The “high” and “low” levels for the DOE were selected as follow: 50 – 100 mm for the seed diameter; 5 – 25 mm for the side surface height; 3 – 15 mm for the growth front height; and 0 – 15o for the inclination angle of the side surface. The DOE runs were performed and responses obtained using a numerical simulation package. As the DOE responses maximal values within the simulated domains and measures of the special uniformities, i.e. (max-min)/mean, for both shear and von-Mises stress distributions have been chosen. Then the DOE analysis has been completed.As the preliminary DOE analysis revealed the growth front height to be the most significant factor that influence shear stress magnitude and both, magnitude and uniformity, of von-Mises stress distribution. At the same time, uniformity of the shear stress distribution is primarily depends on the boule side surface height. The more detailed results, which include factor interaction effects, will be presented. The results will be discussed in terms of the challenges faced during engineering of large (100mm and larger) diameter crystals.
10:30 AM - B1.4
Defect Reduction in SiC Growth Using Physical Vapor Transport.
Darren Hansen 1 , Mark Loboda 1 , Roman Drachev 1 , Edward Sanchez 1 , Jie Zhang 1 , Eric Carlson 1 , Gil Chung 1
1 , Dow Corning Compound Semiconductor Solutions, Midland, Michigan, United States
Show Abstract4H SiC is a promising material because of its mechanical, electrical, and physical properties. However, SiC material defects have had a rate limiting effect on the widespread adoption of SiC. Micropipes, basal plane dislocations (BPD), elementary screw dislocations (SDD) and threading edge dislocations (TED) have all been identified as limiting to device operation and/or performance. An ideal PVT strategy for manufacturing SiC crystals would be capable of driving defects out the crystal via a combination of stress control and defect dissociation pathways. In this work a PVT technology was realized which is capable of continuously improving the crystal quality, at each growth event. A low crystal stress PVT process was conceived and optimized using iterative experiment and simulation methods. During the maturation of the process it was observed that the crystal stress and crystal defect density repeatedly decreased relative to the seed crystal, as evaluated by x-ray topography and x-ray diffraction analysis, and also thru inspection by molten salt etching. The process improvements were leveraged successfully to achieve 4H n+ SiC wafers at 76-100 mm diameter with MPD <1 cm-2, SDD <500 cm-2, and BPD <500 cm-2. This paper will illustrate the defect reduction pathways leading to state of the art defect density 4H SiC crystals and the impact of the improved crystal on epitaxy defects and simple device experiments.
10:45 AM - **B1.5
Progress in Semi-insulating 6H-SiC Single Crystal Growth.
Xiaobo Hu 1 , Xiangang Xu 1 , Xiufang Chen 1 , Yuqiang Gao 1 , Yan Peng 1 , Minhua Jiang 1
1 , State Key Laboratory of Crystal Materials, Shandong University, Jinan , Shandong, China
Show AbstractSemi-insulating 6H-SiC single crystals have been successfully grown by vanadium doping sublimation method. Uniform vanadium doping was realized by the gradual release of vanadium throughout whole crystal growth procedure. Influence of experimental conditions on the vanadium distribution in SiC single crystal was investigated. The resistivity of wafer was measured by contactless resistivity mapping system. Secondary ion mass spectrometry was used to determine the impurity contents in the SiC powder source and crystal. It was found that the impurity contents in crystal were less than those in powder source. The dislocation density of semi-insulating SiC single crystal was estimated by chemical etching. The result shows that the morphologies of etching pits depend on the electrical properties of SiC single crystals, i.e. the morphology of etching pits can reflect indirectly the electrical properties of semi-insulating 6H-SiC single crystals. Finally, a high electron mobility tube fabricated on the substrate of semi-insulating 6H-SiC was demonstrated.
B2: Defects and Characterization I
Session Chairs
Tuesday PM, April 06, 2010
Room 2004 (Moscone West)
11:30 AM - **B2.1
Tracking Basal Plane Dislocation Glide and Conversion to Threading Edge Dislocations in SiC Epitaxy.
Robert Stahlbush 1
1 , NRL, Washington, District of Columbia, United States
Show AbstractSiC power devices are in the process of replacing their Si-based counterparts. The emergence of commercially available SiC devices is due in a large part to the reduction of materials defects that have occurred over the last decade. Further market penetration will depend on continued materials improvements and improved techniques for identifying materials defects that degrade electrical performance.The newly developed ultraviolet photoluminescence (UVPL) technique has a number of advantages compared with alternate methods for examining dislocations and other extended defects in SiC epitaxy. The UVPL technique provides plan-view images of dislocations stacking faults and other extended defects within the epitaxy. The images extend over whole wafers and span the entire epitaxial thickness even for epitaxial layers that are 100 µm or more thick. Furthermore, UVPL is non-contact and non-destructive. These features make it an attractive method to screen wafers before fabrication and to evaluate the quality of epitaxial growths.UVPL is also a valuable tool to track the path of extended defects through the epitaxy. In this presentation, that ability has been applied to basal plane dislocations (BPDs). They cause degradation in a number of bipolar power devices including PiN diodes, BJTs and thyristors due to Shockley stacking faults that originate from the BPDs during device operation. These expanding stacking faults degrade the lifetime within the drift region causing the forward voltage to drift upward. There is also evidence that BPDs adversely affect device leakage.The glide of BPDs within the basal plane during epitaxial growth has been directly observed by growing multiple layers and imaging the BPDs after each of the growths. One consequence of the BPD glide is the formation of a defect alternately called a pair array or a half-loop array. This defect results from a single BPD gliding distances of up to many mm in epitaxial layers in the 50 - 100 µm thickness range. During its glide, the BPD generates an array of half loops. Each half loop contain a small, ~ 1 µm, BPD segment at its bottom and during forward-biased device operation, the array of BPD segments form a Shockley stacking fault that expands until it spans the entire epitaxial layer. The UVPL images show the entire structure of the half-loop array defect and the interaction of the gliding BPD with threading screw dislocations.The ability to track the path of BPDs within the epitaxy has also enabled a better understanding of the conversion of BPDs into threading edge dislocations in epitaxy grown on 4° and 8° offcut substrates. In the 4° case the conversion tendency is very strong during typical epitaxial growth and in the 8° case the conversion process is typically very weak. In the latter case, the ability to track the BPD path has enabled the development of a growth interruption process to increase the conversion rate within the epitaxial layer to over 98%.
12:00 PM - B2.2
Analysis of Dislocation Interactions in Low Dislocation Density, PVT-grown, Four-inch Silicon Carbide Single Crystals.
Michael Dudley 1 , Ning Zhang 1 , Yu Zhang 1 , Balaji Raghothamachar 1 , Shayan Byrappa 1 , Gloria Choi 1 , Edward Sanchez 2 , Darren Hansen 2 , Roman Drachev 2 , Mark Loboda 2
1 Department of Materials Science and Engineering, Stony Brook University, Stony Brook, New York, United States, 2 , Dow Corning Compound Semiconductor Solutions, Midland, Michigan, United States
Show AbstractSynchrotron White Beam X-ray Topography studies are presented of dislocation behavior and interactions a new generation of one hundred millemeter diameter, 4H-SiC wafers grown using Physical Vapor Transport under specially designed low stress conditions. Such low stress growth conditions have enabled reductions of dislocation density by two or three orders of magnitude compared to previous levels. For example, detailed analysis of transmission geometry topographs recorded from wafers ranging in thickness from four hundred to seven hundred nanometers demonstrates extremely low defect basal plane dislocation (BPD) densities of just a few hundred per square centimeter. Lowering of dislocation densities to such levels provides a unique opportunity to discern the details of dislocation configurations and interactions which were previously precluded due to complications of image overlap at higher dislocation densities. Among the phenomena observed in these studies is the conversion of non-screw oriented glissile BPDs into sessile threading edge dislocations (TEDs). This is observed to provide pinning points for the beginnings of the operation of single ended Frank-Read sources. In some regions, once converted TEDs are observed to re-convert back into BPDs, most probably through overgrowth by macrosteps in a repetitive process which provides multiple BPD pinning points. Deflection of other threading defects into the basal plane is also observed to produce complex defect configurations the details of which will be presented. The implications of such substrate defect configurations on subsequently grown homoepitaxial layers will be discussed.
12:15 PM - B2.3
Spontaneous Conversion of Basal Plane Dislocations During Epitaxial Growth on 8° Off-axis 4H-SiC.
Rachael Myers-Ward 1 , Yang Yang 1 , Joseph McCrate 1 , Kok-Keong Lew 1 , Brenda VanMil 1 , Virginia Wheeler 1 , Nadeem Mahadik 1 , Joseph Tedesco 1 , Robert Stahlbush 1 , Charles Eddy, Jr. 1 , D. Kurt Gaskill 1
1 , US Naval Research Laboratory, Washington, District of Columbia, United States
Show Abstract Silicon carbide (SiC) is a material of interest for high-temperature, high-voltage and high-power switching device applications. In order for bipolar SiC devices to become feasible, material with long lifetimes and low extended defects are needed. Basal plane dislocations (BPDs) are a major concern for the SiC bipolar devices required for high-voltage applications as they source Shockley-type stacking faults in the presence of an electron-hole plasma and reduce minority carrier lifetimes [1, 2]. Many researchers have investigated methods to reduce the BPD density by experimenting with pre-growth treatments [3-5], substrate orientation [6], growth parameters [6, 7] and growth interrupts [8]. It has been shown that the conversion of BPDs to threading edge dislocations (TEDs) continues throughout the epitaxial growth process in 4° off-axis SiC material and that a maximum thickness of ~16 µm is required to convert all BPDs to TEDs [9].This work investigates the spontaneous conversion of BPDs in 8° off-axis 4H-SiC material. Epitaxial layers were grown in an Aixtron/Epigress VP508 horizontal hot-wall reactor using the standard chemistry of silane (SiH4, 2% in H2) and propane (C3H8). The films were both unintentionally (UID) and intentionally (ID) doped using a nitrogen source gas. All films investigated were grown with all other growth parameters maintained at T = 1580°C, P = 100 mbar and C/Si = 1.55. Before growth, the substrates structural quality was investigated using X-ray rocking curve maps. Ultraviolet photoluminescence (UVPL) imaging was used to identify the BPDs after epitaxial growth. Atomic force microscopy was used to determine the surface roughness, while the morphology was evaluated using Nomarski microscopy. The BPDs converted spontaneously to TEDs during the growth process in the 8° material, similar to that of 4° material, however, the conversion rate was much slower in the former than the latter material. The conversion efficiency profiles of 8° material will be presented for epitaxial layers without growth treatments. The substrate and doping influence on BPD conversion efficiency will also be presented. [1] J.P. Bergman et al. Mater. Sci. Forum Vol. 353-356, 299 (2001).[2] R.E. Stahlbush et al., J. Electron. Mater. 31, 370 (2002).[3]Z. Zhang, E. Moulton, and T.S. Sudarshan, Appl. Phys. Lett. 89, 081910 (2006).[4] J.J. Sumakeris et al., Mater. Sci. Forum 527-529, 529 (2006).[5]H. Tsuchida et al., Mater. Sci. Forum 483-485, 97 (2005).[6]W. Chen and M.A. Capano J. Appl. Phys. 98, 114907 (2005). [7]T. Ohno et al., J. Cryst. Growth 271, 1 (2004).[8]R. E. Stahlbush et al., Appl. Phys. Lett. 94, 041916 (2009).[9]R.L. Myers-Ward et al., Mater. Sci. Forum 615-617, 105-108 (2009).
B3: Defects and Characterization II
Session Chairs
Erwin Schmitt
Robert Stahlbush
Tuesday PM, April 06, 2010
Room 2004 (Moscone West)
2:30 PM - **B3.1
Examination and Reduction of Structural Defects in PVT Grown Silicon Carbide Crystals.
Erwin Schmitt 1 , Thomas Straubinger 1 , Michael Vogel 1 , Arnd-Dietrich Weber 1
1 , SiCrystal AG, Erlangen Germany
Show AbstractDue to its outstanding material properties Silicon Carbide always has been of great interest as substrate for high power and high temperature devices. Increasing demands to reduce CO2-emission have additionally boosted the necessity to implement a progressive generation of energy-saving devices based on 4H-SiC. Improvements in wafer diameter and crystalline quality during the last decade have brought Silicon Carbide closer to market launch. But particularly with regard to automotive applications there is still the need for ongoing defect reduction in Silicon Carbide wafers to durably meet the requirements.In this work we demonstrate that a significant improvement to reduce the occurrence of severe structural crystalline imperfections such as subgrain boundaries was achieved by securing polytype stability in PVT-grown crystals. The resulting transmission images of 3” and 100 mm wafers under crossed polarizer’s show no relevant stress contrast, related to this defect category. Also micropipe densities are reduced to minor levels. Besides this, the reduction of dislocation densities has become the centre point of material research since stability and robustness of high power devices are greatly affected by them. For that reason several methods for the evaluation of dislocations, e.g. KOH defect etching, optical microscopy, electron microscopy, and synchrotron white beam topography were conducted. This comprehensive study on dislocation types lead to an improved understanding of possible sources for screw dislocations, threading edge dislocations and basal plane dislocations. It was found out that for basal plane dislocations basal and prismatic glide systems are acting as source for their generation and movement. Therefore thermo elastic stress as origin for dislocation generation and movement of dislocations has to be reduced. With the assistance of numerical modelling advanced boundary conditions for PVT growth were introduced. By this the occurrence of the basal plane dislocations was considerable reduced and the formation of slip bands could be suppressed. Best values for 3” or 100 mm 4H wafers show large areas with etch pit densities (EPD) < 104 cm-2 and in particular basal plane dislocation densities (BPD) < 5*103 cm-2. Finally we examined the influence on nitrogen doping. For outperforming device characteristics a low resistivity of the 4H substrates is desired. We found out that reducing the resistivity by increasing the nitrogen content faces a critical level of 16 mΩcm, at which substantial conversion of basal plane dislocations into stacking faults appears.
3:00 PM - B3.2
Non-destructive Detection and Visualization of Extended Defects in 4H-SiC Epilayers.
Gan Feng 1 , Jun Suda 1 , Tsunenobu Kimoto 1 2
1 Department of Electronic Science and Engineering, Kyoto University, Kyoto Japan, 2 Photonics and Electronics Science and Engineering Center, Kyoto University, Kyoto, Kyoto, Japan
Show AbstractExtended defects, dislocations and in-grown stacking faults (SFs), are electrically active defects and carrier traps in 4H-SiC. The nonradiative recombination process via the extended defects contributes to the intensity reduction of near-band-edge emission of 4H-SiC. In this work, the micro-PL intensity mapping at the near-band-edge emission (390 nm) is performed to spatially profile the extended defects in 4H-SiC epilayers grown at high growth rates (50-90 μm/h). Dislocations and in-grown SFs in 4H-SiC epilayers are successfully visualized in the micro-PL intensity mapping at 390 nm with different contrast features. The small circles (5~20 μm in diameter) with relatively low intensity have been identified as dislocations, while the large contrast areas with typically triangle shapes are in-grown SFs. Among the dislocations, the threading dislocations (TDs) can be distinguished from basal plane dislocations (BPDs) by the size of the circles and the contrast. TDs exhibit the larger size (10~20 μm in diameter) and contrast than that of BPDs. This contributes to the stronger strain field (the larger capture cross section) around TDs than BPDs. Furthermore, in-grown SFs in 4H-SiC form quantum-well-like electronic states which give rise to the additional emission band besides the intensity reduction of the near-band-edge emission. Three different kinds of in-grown SFs have been successfully identified in the samples based on the micro-PL spectra at room temperature. Each kind of in-grown SFs shows the distinct PL emission with a specific peak wavelength located at 460 nm (IG-I), 480 nm (IG-II), and 500 nm (IG-III), respectively. Each in-grown SF is then selectively visualized to reveal its own shape, location, and density by micro-PL intensity mapping at its own specific wavelength (band energy). IG-I is the dominant in-grown SFs in our samples, typically with the density of 1-20 cm-2. It has the right-angled triangular shape with the uniform size within one sample. The length of the right-angled triangles along the step flow direction corresponds to the projected length of the basal plane in the epitaxial layer. It means that IG-I is generated at the beginning of the epitaxial growth. IG-II and IG-III have the similar size and the density of 1-5 cm-2. However, their sizes are obviously smaller than IG-I, especially the width vertical to the step flow direction. This might be a hint that the nucleation processes of IG-II and IG-III differ from IG-I. In order to verify the reliability of micro-PL mapping method, the samples are etched in molten KOH at 500 oC for 5-10 min. The one to one correlation between KOH etch pits and micro-PL mapping contrasts for the dislocations and in-grown SFs is observed, indicating the high reliability of micro-PL mapping method for detection and visualization of the extended defects in 4H-SiC epilayers.
3:15 PM - B3.3
Intrinsic Surface Defects on 4H SiC Substrates.
Mary Ellen Zvanut 1 , Sarah Thomas 1 , Jamiyanaa Dashdorj 1 , Rachael Myers-Ward 2 , Charles Eddy 2 , D. Kurt Gaskill 2
1 Physics, University of Alabama at Birmingham, Birmingham , Alabama, United States, 2 , Naval Research Laboratory, Washington DC, District of Columbia, United States
Show AbstractThe quality of the SiC surface is critical for successful operation of all SiC-based electronics. We have investigated a point defect, common to all SiC substrates, that is thought to be a broken carbon bond. Electron paramagnetic resonance (EPR) spectroscopy in combination with three different etching methods is used to demonstrate that the center lies near the surface. The results from the various etching methods consistently suggest that on the order of 1011 cm-2 defects are removed within the first micron of the Si-face surface.Three types of 4H SiC substrates grown by physical vapor transport (PVT) and one undoped epitaxial layer are being studied. The bare substrates were cut from a 3 Ohm-cm single-sided polished p-type wafer, a 5-10 Ohm-cm double-sided polished n-type wafer, or vanadium-doped double sided polished high resistivity wafer. The epi-layer was grown by chemical vapor deposition (CVD) to a thickness of 4 μm on the Si-face of a high resistivity 4H SiC wafer. All samples were cut and solvent cleaned in preparation for EPR measurements. EPR was performed at room temperature before and after annealing in either dry (<1 ppm H2O) N2 or O2 up to 1000 oC or in steam at 1150 oC. Reactive ion etching was performed using NF3 at an etch rate of 90 nm/min. The spectra of all of the as-cut samples were dominated by a signal that arises from the cut edges. A 600 oC dry N2 anneal reduces the cut-induced signal and reveals an isotropic 3 G wide spectrum with g=2.0022. The 3 G spectrum remains unaltered by 30 min N2 heat treatments at temperatures as high as 900 oC, but the intensity decreases by 25% during a 30 min dry O2 anneal at this temperature. A 6 h oxidation in steam produced the same g=2.0022 signal but the intensity was 40% less than that remaining after the 1000 oC dry O2 treatment. The oxidation studies suggest defect removal by means of etching SiC or reaction of the defect with O2. RIE was performed to eliminate involvement of O2 and to enable selective etching of each face of the sample. Initial studies show that about 30% of the centers, 1011 cm-2 defects, are located within 350 nm of the polished Si-face of the p-type wafer. Surprisingly, removing about half of the epitaxial layer showed an equivalent decrease in the number of defects. In summary, the studies indicate that at least 1011 cm-2 defects are located within the top micron of the Si-face, whether a PVT grown bulk wafer or CVD epitaxial layer. The more refined oxidation ‘etching’ study indicates that the centers may be within a few nanometers of the surface.The work is supported by Dr. Paul Maki, ONR Grant N0014-09-1-0082. We thank Dr. J. Williams and Tamara Isaacs-Smith, Auburn University, for performing RIE.
3:30 PM - **B3.4
Evolution of Stacking Faults Defects During Epitaxial Growths: Role of Surface Kinetics.
Massimo Camarda 1 , Antonino La Magna 1 , Andrea Canino 2 , Francesco La Via 1
1 , CNR-IMM, Catania Italy, 2 , Epitaxial Techn. Center, Catania Italy
Show AbstractKinetic Monte simulations on super-lattices are applied to the study of the evolution of stacking faults during epitaxial growths. We show that, in the case of epitaxially grown Silicon Carbide, a single stacking fault can either extend throughout the entire epilayer (i.e. extend from the substrate up to the surface) or close into a dislocation loop depending on the deposition conditions. We explain this behaviour in terms of a surface kinetic competition between the defect and the surrounding crystal: if the growth rate of the defect is higher compared with that of the perfect crystal the defect will expand, otherwise it will close. Furthermore, it is possible to mathematically correlate the density, on the surface, of a specific stacking fault in terms of the growth rate Gr, f(Gr), to the dependencies of f() on other two important parameters, namely the misorientation cut and the growth temperature. This result greatly simplifies the behaviour of f() and, thus, reduces the experiments necessary to study the evolution of these defects in the epilayers. These findings allow to explain several experimental results on homo and hetero epitaxies.
4:30 PM - B3.5
Identifying Stacking Fault Positions at SiC(0001) -√3×√3 Surfaces via Nanometer-scale Electron Diffraction on LEEM.
Jiebing Sun 1 , James Hannon 2 , Ruud Tromp 2 , Karsten Pohl 1
1 Phys. Dept. and Mat. Sci. Program, Univerisity of New Hampshire, Durham, New Hampshire, United States, 2 , IBM Research Division, T. J. Watson Research Center, Yorktown Heights, New York, United States
Show AbstractTo understand the epitaxial growth mechanism that determines the surface structures intimately correlated to the SiC- and graphene/SiC-based electronics, it is necessary to identify the stacking sequence or the stacking fault locations in surface regions. To obtain the 3-dimensional atomic surface structure is, however, extremely difficult since the stacking faults can be too deep to detect or their different positions could give very little difference in the surface probing signal. In this presentation, we highlight a novel low-energy electron microscopy (LEEM) technique – nanometer-scale low-energy electron diffraction analysis – which is capable of identifying the stacking fault positions on the 4H-SiC(0001)-√3×√3 surface. Atomic force microscopy and dark-field low-energy electron microscopy studies show half-unit-cell step heights on both 4H-SiC(0001) and 6H-SiC(0001) surfaces. Dynamical analysis of single domain electron diffraction intensities from 4H-SiC(0001)-√3×√3 proves a termination with a stacking fault located between the 2nd and 3rd bilayers. This finding helps to identify the cubic growth on 4H-SiC(0001) at elevated temperature, leaving the stacking fault between the 3rd and 4th bilayers. This evidence suggests a preferred termination on 6H-SiC(0001) with the same stacking fault position, consistent with DFT theoretical arguments.
4:45 PM - B3.6
Single Shockley Faults Evolution Under UV Optical Pumping.
Andrea Canino 1 , Massimo Camarda 2 , Francesco La Via 2
1 , Empaxial Technology Center, Catania, Sicily, Italy, 2 IMM, CNR, Catania, Sicily, Italy
Show Abstract4H-SiC, due to superior structural, electrical and mechanical properties, is an interesting material for the development of devices with improved performances in the field of high-power and high-frequency electronics and also for high-temperature applications. The limiting step for the commercialization of efficient bipolar devices is the degradation of I-V characteristics due to the presence of stacking faults (SFs) in the epitaxial layers.Spatially resolved micro-photoluminescence (mPL) has been used to map both density and geometry of SFs that exhibit an intense room temperature photoluminescence (PL). In particular we focused our attention on the effect of the pumping laser on the single Shockley fault (SSF) that has a peak centered, at room temperature, at about 2.93 eV. In fact it is known that high power optical pumping can supply the energy for the enlargements and formation of SSFs.In order to investigate this aspect with the aim of finding a power threshold for this phenomenon, we performed a set of measurements using different power density (PD) on the samples by opportunely filtering the pumping laser signal. First of all we perform mPL map of the sample surface with a PD of the order of about 100 W/cm^2 in order to individuate the SSFs. This value of PD avoids changing structural properties of indentified defects. After individuating an isolated SSF we performed a set of exposition with different PDs up to of 500 W/cm^2. At this limit we observed an evolution of SSFs dimension. Considering these results, a particular experimental setup has been used to vary the power density in the 100÷500 W/cm^2 range with a defocusing technique.
5:00 PM - B3.7
Study of the Crystallographic and Electronic Properties of Stacking Faults in 4H Silicon Carbide.
Massimo Camarda 1 , Antonino La Magna 1 , Corrado Bongiorno 1 , Andrea Canino 2 , Francesco La Via 1
1 , CNR-IMM, Catania Italy, 2 , Epitaxial Techn. Center, catania Italy
Show AbstractIn recent years the commercialization of 4H-SiC high-voltage p-i-n diodes has been hampered due to the degradation of the forward I-V characteristics during the device life-time. This effect is now well documented to be caused by the expansion of Shockley-type stacking faults (SSF) in the zone device reached by the electron-hole plasma. These defects can either appear during the growth ("as grown defects") or during a later process like doping, annealing or oxidation ("process induced defects"). It has recently become customary, when discussing the crystallographic structure of SSF, to use the Hagg's or Zhadanov notations instead of the classical ABC one. Although these new notations greatly simplify the description of the defects, highlighting their symmetries, they have an important drawback: they do not adequately describe the structure of these defects along the [0001] direction (i.e. perpendicularly to the basal plane). More specifically, it has been found that SSFs have to be considered as three dimensional defects, with a finite extension along the [0001] direction. For this reason the formation energy, as well as all considerations concerning their stability have to be deeply reconsidered. High resolution transmission electron microscopy have been extensively used to reveal the structure of the partial dislocations surrounding these defects. We have also investigated their electronic structures by density functional theory to correlate the photoluminescence (PL) spectra peaks with calculated defect-related intra-state energy bands.
5:15 PM - B3.8
Theory of Neutral Divacancy in SiC: A Defect for Spintronics.
Adam Gali 1 , Andreas Gaellstroem 2 , Ngyen Son 2 , Erik Janzen 2
1 , Budapest University of Technology and Economics, Budapest Hungary, 2 , Linköping University, Linköping Sweden
Show AbstractWe investigate the neutral divacancy in SiC by means of first principles calculations and group theory analysis. We identify the nature of the PL transitions associated with this defect. We show that how the spin state may be manipulated optically in this defect. We propose that the neutral divacancy in SiC may be an appropriate candidate for realizing solid state qubits.
5:30 PM - B3.9
Radio Frequency Plasma Source Atomic Spectroscopy and Mass Spectrometry: A Novel Approach to Silicon Carbide (SiC) Material Characterization.
Fuhe Li 1 , Scott Anderson 1
1 Balazs NanoAnalysis, Air Liquide Electronics, Fremont, California, United States
Show AbstractRadio Frequency (RF) plasma source atomic spectroscopy and mass spectrometry have been developed in our laboratory to characterize various silicon carbide (SiC) materials for elemental composition. The specific techniques that were studied included glow discharge optical emission spectroscopy (RF GD-OES) and laser ablation ICP mass spectrometry (LA ICP-MS). By utilizing RF plasma or laser ablation for material sputtering, excitation or ionization, many intrinsic limitations associated with traditional electron, ion or x-ray techniques are avoided in characterizing surface, interface and bulk SiC materials. RF GD-OES has been used to profile surface, near surface and interface (e.g. oxide and SiC interface) of SiC materials with nm depth resolution and simultaneous multi-element profiling capability. The depth profiles obtained have been successfully used to assist ion implantation process and doping control in SiC. LA ICP-MS has been used for microscopic defect identification and quantitative determination of trace residue impurities in Bulk SiC. The information obtained have been used to help EPI layer preparation and SiC crystal purification. The signal intensities produced by both techniques all have simple and well-defined mathematical (linear) relationships with elemental concentrations in the material. Each technique has a wide linear dynamic range and coupled with various NIST traceable material standards developed in our laboratory have made accurate and precise surface and bulk SiC analyses possible.
Symposium Organizers
Michael Dudley State University of New York-Stony Brook
Stephen E. Saddow University of South Florida
Edward Sanchez Dow Corning Compound Semiconductor
Feng Zhao University of South Carolina
B4: Epitaxial Growth
Session Chairs
Stephen Saddow
Edward Sanchez
Wednesday AM, April 07, 2010
Room 2004 (Moscone West)
9:30 AM - **B4.1
Effects of Growth and Post-growth Processes on Defects in 4H-SiC Epilayers.
Hidekazu Tsuchida 1 , Masahiro Nagano 1 , Tetsuya Miyazawa 1 , Isaho Kamata 1 , Ito Masahiko 1 , Norihiro Hoshino 1 , Xuan Zhang 1
1 Materials Science Research Laboratory, Central Research Institute of Electric Power Industry (CRIEPI), Yokosuka, Kanagwa, Japan
Show AbstractIn thick epitaxial growth for very high voltage SiC bipolar devices, reductions of basal plane dislocations (BPDs), in-grown stacking faults and point defects are the major issues in 4H-SiC epitaxy. Moreover, the post-growth device process can also have significant effects on the formation or modification of the defects in the epilayers. This paper reports recent results in the characterization of growth and post-growth process induced defects in 4H-SiC epilayers. The 4H-SiC epilayers were grown in two different vertical type reactors or a planetary reactor. In a vertical reactor, very high growth rates exceeding 100 μm/h (up to 250 μm/h) are obtained. Various characterization techniques, which include grazing incidence or transmission synchrotron X-ray topography, photoluminescence (PL) imaging, transmission electron microscope (TEM), time-resolved PL, microwave photoconductive decay (μ-PCD) measurement and deep level transient spectroscopy (DLTS), are utilized to investigate the defects in the epilayers and the carrier lifetimes. We find the formation of interfacial basal plane dislocations (IDs) near the epilayer/substrate interface; not only during 4H-SiC epitaxial growth as reported earlier [1, 2] but also the post-growth high-temperature annealing process. In the case of the high-temperature annealing after ion-implantation, the formation of IDs at the bottom of the implanted layers is also observed. Moreover, the formation of arrays of BPD loops (Shockley faults) near the epilayer surface is found in conjunction of the high-temperature annealing. The process conditions are confirmed to significantly influence the formation of such defects. Enhancement of the carrier lifetimes is another challenge in 4H-SiC epitaxy. The growth temperature and C/Si ratio have a strong influence on the Z1/2 concentration, while the growth rate has little effect, as reported earlier [3]. Under optimal growth conditions, we obtain a carrier lifetime of 2-5 μs (μ-PCD) for an as-grown epilayer with a thickness of 250 μm. The carrier lifetime is significantly improved by the application of the C-ion implantation/annealing process [4], and an extraordinary long carrier lifetime of 27 μs is evaluated in the same epilayer after the process. Further analysis of the carrier lifetimes will be discussed.[1] X. Zhang et al., J. Appl. Phys. 101 (2007) 053517, [2] H. Tsuchida et al., Mater. Res. Soc. Symp. Proc. 1069 (2008) 123, D04-03, [3] K. Danno et al., J. Appl. Phys 101 (2007) 053709, T. Hori et al., J. Cryst. Growth 306 (2007) 297, [4] L. Storasta et al., J. Appl. Physics 103 (2008) 013705.
10:00 AM - B4.2
Characterization and Growth Mechanisms of B12As2 Epitaxial Layers Grown on Off-axis (0001) 4H-SiC Substrates.
Yu Zhang 1 , Hui Chen 1 , Michael Dudley 1 , Yi Zhang 2 , James Edgar 2 , Lihua Zhang 3 , Yimei Zhu 3
1 Department of Materials Science and Engineering, Stony Brook University, Stony Brook, New York, United States, 2 Department of Chemical Engineering, Kansas State University, Manhattan, Kansas, United States, 3 Center for Functional Nanomaterials, Brookhaven National Laboratory, Upton, New York, United States
Show AbstractAs a member of icosahedra borides, B12As2 has a wide band gap of 3.47eV, possessing many exceptional properties such as high hardness, high temperature thermoelectric and “self-healing” from radiation damage. A potential application of B12As2 is for the fabrication of beta cells capable of producing electrical energy by coupling a radioactive beta emitter to a semiconductor junction. Previous efforts were devoted to deposit B12As2 on (0001) 6H-SiC substrates by chemical vapor deposition (CVD), but the films contained high density of B12As2 twin boundaries which may have adverse effects on device performance. In this report, B12As2 epitaxial layers grown on off-axis (0001) 4H-SiC substrates have been studied using synchrotron white beam x-ray topography (SWBXT) and high resolution transmission electron microscopy (HRTEM). SWBXT revealed that only one orientation of B12As2 was present in the epitaxial layer, which was grown along (111) surface normal. The SWBXT also revealed that B12As2 diffraction spots have much better-defined shapes compared to those grown on 6H-SiC substrates. This indicates the film grown on off-axis (0001) 4H-SiC substrate is highly single crystalline and has much higher quality. Cross-sectional HRTEM also confirmed the presence of only one orientation in the B12As2 grains grown along (111) surface normal. The growth mechanism of B12As2 on off-axis c-plane 4H-SiC are also proposed, which suggests that off-axis c-plane 4H-SiC may be a suitable substrate to grow B12As2 single crystals.
10:15 AM - B4.3
3C-SiC Heteroepitaxial Growth on Inverted Silicon Pyramids (ISP).
Giuseppe D'Arrigo 1 , Andrea Severino 1 , Christopher Locke 2 , Gabriella Milazzo 1 , Corrado Bongiorno 1 , Nicolo Piluso 1 , Stephen Saddow 2 , Francesco La Via 1
1 IMM, Consiglio Nazionale delle Ricerche, Catania Italy, 2 EE Dept, University South Florida, Tampa, Florida, United States
Show Abstract3C-SiC devices are hampered by the defect density in heteroepitaxial films. Acting on the substrate, it is possible to achieve a better compliance between Si and 3C-SiC. In literature several approaches for the defect reduction using a lattice compensation or flexible structures to absorb the generated strain were reported, but the most interesting approach suitable for wafers fabrication and production was proposed by Nagasawa et al.. We present here a new approach to favorite defect geometrical reduction in both [110] directions by creating Inverted Pyramids on Si (IPS). A study of 3C-SiC growth on IPS is reported showing benefits in the film quality and a reduction in the linear density of stacking faults. Growth on IPS leads also to a decrease in the 3C-SiC residual stress as well as in the bow of the Si/SiC system. 3C–SiC films were grown in a hot-wall chemical vapour deposition (CVD) reactor. All the processes were performed at the same time on the ISP substrate and on Si (100) on axis to observe the differences in the defect density. Material characterization has been conducted by Atomic Force Microscopy (AFM), Transmission Electron Microscopy (TEM) and X-Ray Diffraction (XRD). XRD has been conducted by studying the full width at half-maximum (FWHM) of the rocking curve related to the 3C-SiC {200}-planes to evaluate the film quality in films grown on IPS and on (100) Si. As the thickness grows, FWHMs decrease for both substrates, being almost halved for 3C-SiC on IPS and reaching a value lower than 800 arcsec for a 6 micron thick 3C-SiC film. Raman analysis show a smaller shift suggesting a lower amount of tensile stress in the 3C-SiC/IPS system for the thicker film as compared to 3C-SiC/(100) Si. A decrease of the residual stress in the 3C-SiC film should imply a higher density of structural defects because of the action of plastic deformations in releasing such a stress. TEM, both in plan-view and in cross-section, have been performed to better study and evaluate defect generation and propagation in films grown either on IPS and (100) Si substrates. From plan-view TEM, larger defect-free zones at the surface of 3C-SiC films grown on IPS as compared to films grown on conventional (100) Si have been observed. Linear stacking faults density was strongly lowered in films grown on IPS. By a comparison between 3C-SiC growth on ISP and (100) Si, stacking faults density was found to be about 3×104 cm-1 (almost constant in the range between 1 and 5 micron) for the latter while a value of about 1.5×104/cm is observed after the growth of 1 micron 3C-SiC on ISP. This value further decreases increasing the 3C-SiC layer thickness reaching a value of 0.6×104/cm after the growth of 5 micron 3C-SiC film. A further reduction of this defect density can be expected increasing the layer thickness and with a better optimization of the growth process.
10:30 AM - B4.4
The Spontaneous Formation of a New Polytype on SiC(0001).
James Hannon 1 , Rudolf Tromp 1 , Nikhil Medhekar 2 , Vivek Shenoy 2
1 T.J. Watson Research Center, IBM Research Division, Yorktown Heights, New York, United States, 2 Division of Engineering, Brown University, Providence, Rhode Island, United States
Show AbstractUsing in situ electron microscopy, we have studied the evolution of SiC(0001)-4H during annealing at elevated temperatures. Above roughly 900 C, a new cubic layer spontaneously forms on top of the surface. We show that the growth of the new cubic polytype is fundamentally limited to one layer because the cubic layer does not wet the steps of underlying hexagonal polytype (no vertical twin boundary forms). As a consequence, the cubic layer cannot grow thicker via step overgrowth. The cubic layer expands laterally, accelerating step bunching in the surrounding hexagonal regions. During SiC epitaxy, the lack of step edge wetting of the cubic phase leads to the growth of 3C twins separated by deep grooves.
11:30 AM - **B4.6
Recent Developments in SiC Homoepitaxy Using Dichlorosilane for High Power Devices.
Tangali Sudarshan 1 , Iftekhar Chowdhury 1 , Mvs Chandrashekhar 1
1 Electrical Engineering, University of South Carolina, Columbia, South Carolina, United States
Show AbstractHigh voltage SiC devices (~10kV) are of great interest for smartgrid and other power conversion applications. Recent demonstrations include PiN diodes, Schottky barrier diodes, DMOSFET and implanted VJFET. Epitaxial layers ~100 µm are required to obtain a breakdown voltage ~10 kV. To obtain such large thickness with standard epitaxy processes ~6-7µm/hr, a process time of more than 10 hours is required with the consequent high cost. A new process that overcomes this limitation by adding HCL or using halide precursors has been developed recently. However, the growth of thick epitaxial layers (>50μm) with low doping concentration (<1E14/cm-3) remains a very difficult task, since the surface morphology usually degrades, exhibiting various morphological defects. The epilayer quality degradation is especially severe during growth on low off-cut substrates <40.In this paper, we will present results on high quality, thick 4H-SiC (0001) 80 off-axis toward (11-20) that have been grown by a vertical hot-wall chemical vapor deposition (CVD) furnace (temperature 15000-17000C, pressure 80-300 torr) at a high growth rate using a novel precursor Dichlorosilane, a kinetically favorable halide precursor. RMS roughness in the range of 0.3-0.4 nm with no morphological defects (carrots, triangular defects etc.) has been shown at growth rates 30-100 µm/hr, 5-16 times higher than the conventional speed. The surfaces were specular. Site-competition epitaxy was clearly observed over a wide C/Si ratio window, with donor concentration as low <1E14 cm-3. The full width at half maximum (FWHM) obtained using x-ray rocking curves was as narrow as 7.8 arcsec, which indicates a high quality of the epilayer. Microwave photoconductive decay (µPCD) measurement showed high injection lifetime in the range of 2µs. Micro-Raman Spectroscopy showed the 4H polytype uniformity of these layers.By appropriate adjustment of the ratio, we have been able to grow thick high purity semi-insulating (HPSI) epilayer on 4H-SiC, Si-face, n-type (~0.02 Ohm-cm) samples. The C/Si window for HPSI is relatively wide (1.3-1.7). Resistivity >1E7Ω-cm was determined using the transmission line model (TLM). Secondary ion mass spectroscopy (SIMS) of HPSI epilayer showed low B and Al concentrations with respect to N(1E15 cm-3), which suggests that the nitrogen is compensated by a trap concentration of ~ 1E15cm-3.By implementing this process on 6H-SI, Si-face substrates, 20 off-axis towards [11-20], 12 µm/hr growth rate has been achieved without step bunching. Surface roughness measured by AFM is < 0.3 nm with no morphological defects. Site competition is again clearly observed. These low angle off-cut results will also be presented.This work was supported from ONR, Grant no. N000140910619. The authors thank Dr. H. Scott Coombe of ONR for his support of this research. We also thank II-VI WBG for providing high quality 6H substrates for this work.
12:00 PM - B4.7
Effect of Inclusions and Strain in SiC Epitaxial Layers Grown on 4o Offcut Substrates.
Nadeemullah Mahadik 1 , Robert Stahlbush 1 , Syed Qadri 2 , Orest Glembocki 1 , Dimitri Alexson 1 , Rachael Myers-Ward 1 , Joseph Tedesco 1 , Charles Eddy 1 , D. Gaskill 1
1 Code 6881, Naval Research Laboratory, Washington, District of Columbia, United States, 2 Code 6366, Naval Research Laboratory, Washington, District of Columbia, United States
Show AbstractSilicon carbide (SiC) devices have the potential to replace silicon devices for high power and high temperature applications due to superior intrinsic properties such as large bandgap, high breakdown field, and good thermal conductivity. However, the performance and reliability of SiC devices are degraded by various extended defects such as basal plane dislocations (BPDs), threading dislocations, inclusions, etc. Recently, SiC epilayers grown on 4o off-axis SiC substrates have shown a significant reduction in the density of BPDs. Although the epilayers grown on 4o offcut substrates show better conversion of the BPDs in the substrate to benign threading edge dislocations in the epilayers, it is more difficult to minimize other extended defects at the lower offcut angles. In this work, we have investigated the structure of inclusions in 20 μm thick, 4H-SiC epilayers, on n+ 4H-SiC substrates cut 4o off axis. The samples were grown using standard silane + propane chemistry in a hot-wall Aixtron VP508 chemical vapor deposition reactor. Comprehensive defect mapping was performed using the recently developed, non destructive, ultraviolet photoluminescence (UVPL) imaging technique. Various extended defects such as basal plane dislocations (BPD), in-grown stacking faults, threading dislocations, and 3D defects like inclusions were observed in these images. The inclusions seen in the UVPL images show the presence of BPDs emanating from them and can be attributed to the locally induced stress field. High resolution x-ray topographs (HRXT) were obtained on a double crystal arrangement using the asymmetric SiC (1,0,10) reflection. Various defects such as inclusions, surface features, and strain fields from extended defects were observed in the sample. A one-to-one correlation of various defects between the UVPL and HRXT images was observed and the origins of these defects were analyzed. Furthermore, micro-Raman spectroscopy was also performed on selected areas of the sample to identify any polytypes within the inclusions and map local strain fields.Spectral UVPL imaging was also done for selected defects in the sample using near band-edge bandpass filters. Small bright features within some of the inclusions were seen in the UVPL images taken with the 450-520 nm (2.75-2.38 eV) filters, which may have luminescence from band edge emission of 3C-SiC. These features are similar to the small features identified as 3C-SiC polytype in the micro-Raman map. These small features are in the range of 10-20 μm, and seem to create the total defect. In summary, we have used UVPL, HRXT, and micro-Raman mapping to investigate the structure of various inclusions in epitaxy on 4° offcut substrates. Some, but not all, of these inclusions appear to originate from smaller (~10 μm) polytype inclusions. The overall structure introduces a local strain field and BPDs within this strain field.
12:15 PM - **B4.8
Fabrication Processes for All-epitaxial SiC Power Device.
Adolf Schoner 1
1 Department of Nanoelectronics, Acreo AB, Kista Sweden
Show AbstractRecently SiC devices receive more and more acceptance in power applications. Power Schottky barrier diodes with up to 1700V blocking voltage and more than 20A current rating are commercially available. SiC power switches are on the edge to be commercialized. Power modules including several SiC diodes and switches in parallel to achieve more than 100A current handling capability are demonstrated. SiC MOSFET and SiC JFET devices are used in such power modules. Ion implantation is typically employed to form selectively regions with different doping levels and conductivity type. Due to the in standard implanters available acceleration voltages of around 300keV and depending on the employed ions, the thickness of the implanted layers or areas is often limited to below 1µm. Another limitation is the maximum doping concentration. Ion implantation of very high doping concentrations damages the material. This so called implantation damage is difficult to remove, even when elevated temperatures are used during implantation and the post implantation anneal is done at temperatures above 1600°C. Additional device performance limiting defects can be created during high dose implantation and the consecutive high temperature anneal, which can result in an undesirable high resistivity of the implanted layer. Epitaxial growth is known to create material with high quality. Compared to ion implantation the created defect density and the layer resistivity are lower for the same nominal doping concentration. In addition, epitaxial layers can be grown at almost any thickness and with a wide range of doping concentrations. Both, doping concentration and thickness, can be easily controlled by the precursor flow rates. But the growth is done on the whole substrate and it is difficult to selectively create different doped and different conducting device areas. The fabrication techniques to be used for that are processes like dry etching of trenches and mesas, epitaxial re-growth, and surface planarization. Advantages and disadvantages of such fabrication processes for the device performance and for future device production will be discussed and are being compared to processes employing mainly ion implantation. It will be shown that all-epitaxial SiC device concepts benefit from the better material quality and that they can be done with about the same efforts and costs as ion implantation based device concepts. Hence, all-epitaxial SiC device designs can be feasible for future volume production of higher performing SiC power devices.
B5: Deep Level Defects and Carrier Lifetime
Session Chairs
Wednesday PM, April 07, 2010
Room 2004 (Moscone West)
2:30 PM - B5.1
Improvement of Carrier Lifetimes in N-type 4H-SiC Epilayers.
Tsunenobu Kimoto 1 , Toshihiko Hayashi 1 , Kohtaro Kawahara 1 , Yusuke Nishi 1 , Jun Suda 1
1 Electronic Science & Engineering, Kyoto University, Kyoto Japan
Show AbstractIn recent years, one of the major lifetime killers in 4H-SiC has been identified as the Z1/2 center (Ec – 0.65 eV) [1,2], although the lifetimes in SiC are still short, typically 0.6-2 μs. In this study, significant improvement in lifetimes in n-type 4H-SiC epilayers by reducing the Z1/2 concentration is presented.4H-SiC(0001) epilayers (thickness: 50 μm) were grown by hot-wall CVD at a high growth rate of 25-50 μm/h. All the epilayers were intentionally doped with nitrogen to 1E15 cm-3. The carrier lifetimes of epilayers were measured by differential μ-PCD with a YLF-3HG laser (349 nm) as an excitation source. The typical density of irradiated photons and the temperature were varied in the wide range of 2E12-1E15 cm-2, and 293-523 K, respectively. The concentration of deep levels was evaluated by DLTS on Ni/4H-SiC structures.The Z1/2 concentration in as-grown epilayers strongly depends on the C/Si ratio and the growth temperature, but not much on the growth rate. A high C/Si ratio and low growth temperature are beneficial to obtain a low Z1/2 concentration. Since it is also important to keep good surface morphology, these growth parameters have been optimized. As a result, the Z1/2 concentration has been reduced from 1E13 cm-3 to 2E12 cm-3, while maintaining good morphology (Tg=1620oC, C/Si=1.2). For an epilayer grown under the optimized condition, a significantly improved carrier lifetime of 5.2 μs was attained at 293K. The lifetime showed continuous increase at elevated temperature, and reached 8.4 μs at 523 K.The Z1/2 concentration was further reduced by thermal oxidation at 1300oC for 5 h [3]. By this treatment, the Z1/2 concentration could be reduced to below 1E11 cm-3 in the whole 50 μm-thick epilayer. Regarding the mechanism of the Z1/2 elimination by oxidation, the excess C atoms are emitted from the oxidizing interface and may diffuse into the bulk region, leading to the recombination with C vacancies (likely an origin of the Z1/2 center). The lifetimes were measured after oxide removal by HF dip to keep the same surface condition. Through the Z1/2 elimination by oxidation, the lifetime was increased from 5.2 μs to 9.5 μs at 293K.Based on a model which takes account of several recombination paths such as SRH recombination, surface and Auger recombinations, the experimental decay curves as well as the dependencies of lifetime on the injection level and temperature have been quantitatively analyzed. This investigation has revealed that the lifetime is governed by the SRH recombination via the Z1/2 center at the low-injection level, and is limited by recombination at the surface and in the substrate at the high-injection level. Detail of carrier recombination paths and impacts of extended defects are discussed at the symposium.[1] P.B. Klein et al., APL 88, 052110(2006). [2] K. Danno et al., APL 90, 202109(2007). [3] T. Hiyoshi et al., APEX 2, 041101(2009).
2:45 PM - B5.2
Deep Levels in n- and p-type 4H-SiC Generated by Reactive Ion Etching and Their Reduction.
Koutarou Kawahara 1 , Jun Suda 1 , Tsunenobu Kimoto 1
1 , Kyoto University, Kyoto Japan
Show AbstractThe Reactive Ion Etching (RIE) is an essential process for the fabrication of SiC devices such as mesa diodes and trench MOSFETs. However, the RIE introduces a lattice damage by ion bombardment and generates deep levels in SiC. Deep levels in semiconductors have several harmful effects such as carrier trapping, increase of leakage current, or reduction of minority carrier lifetimes. In this study, the authors investigate deep levels generated by Capacitive Coupled Plasma (CCP)-RIE in n-type and p-type 4H-SiC. Both n- and p-type 4H-SiC(0001) epilayers (doping concentration: mid 1015 cm-3) were employed to monitor deep levels located in the whole bandgap. RIE was performed for 7 min under a standard condition (CF4: 5 sccm, O2: 10 sccm, rf power: 150 W, pressure: 20 Pa), by which a layer of about 0.9 μm was etched off from the surface. After RIE, generated deep levels were evaluated by DLTS measurements on Ni/n-SiC and Ti/p-SiC structures.Electrical characterization revealed that the etching-induced damage is much more severe in p-type SiC. The capacitance of as-etched p-type SiC is remarkably small, indicating the existence of a carrier-compensation or acceptor-deactivation region which is extended from the surface to the complete epilayer thickness (15 μm). Because such an extremely deep compensated or deactivated region cannot be explained by a lattice damage due to ion bombardment which should have an effect on only surface-near region, the authors speculate that the compensation or deactivation might originate from fluorine diffusion during RIE process. The depth profiling of impurities by SIMS is under investigation.The small capacitance recovers to that of as-grown sample after annealing at 1000oC in Ar. However, various kinds of defects, IN2 (EC – 0.35 eV), EN (EC – 1.6 eV), IP1 (EV + 0.35 eV), IP2 (HS1: EV + 0.39 eV), IP4 (HK0: EV + 0.72 eV), IP5 (EV + 0.75 eV), IP7 (EV + 1.3 eV), and EP (EV + 1.4 eV), remain at a high concentration (1013-1015 cm-3) even after annealing at 1000oC. In particular, the HK0 and EP centers exhibit rather flat depth profiles and high concentrations (~1014 cm-3 from the surface-near region to a deep region over 1 μm). Although the defects generated by RIE observed in n-type samples can be significantly reduced by thermal oxidation at 1100oC for 30 min, the defects observed in p-type samples remain. However, almost all these defects can be remarkably reduced by subsequent annealing at 1400oC in Ar. In summary, a high density of various deep levels is generated by RIE of SiC, but almost all these defects can be remarkably reduced by two-step thermal treatment, thermal oxidation at 1100oC followed by Ar annealing at 1400oC.
3:00 PM - B5.3
Deep-level Defects in Electron Irradiated 6H-SiC.
Michal Kozubal 1 , Pawel Kaminski 1 , Stanislaw Warchol 2 , Katarzyna Racka-Dzietko 1 , Krzysztof Grasza 1 3 , Emil Tymicki 1
1 , Institute of Electronic Materials Technology, Warsaw Poland, 2 , Institute of Nuclear Chemistry and Technology, Warsaw Poland, 3 , Institute of Physics Polish Academy of Sciences, Warsaw Poland
Show AbstractSilicon carbide (SiC) is a wide band-gap semiconductor whose properties make it suitable for manufacturing high-temperature, high-frequency and high-power electron devices. However, the material properties are strongly affected by intrinsic and extrinsic defect centers formed during the crystal growth. These centers introduce either shallow or deep energy levels in the band gap and may act as traps or recombination centers reducing the device performance. Thus, to control the material quality it is important to know the electronic properties of defect centers and to understand their nature. Defect centers in SiC crystals have been recently intensively studied both theoretically and experimentally. Amongst the experimental techniques, the deep level transient spectroscopy (DLTS) is especially efficient to determine the parameters of deep levels. However, the origins of the observed levels are very difficult to identify due to a large number of native defects, residual impurities, and their complexes. In this paper we demonstrate that electron bombardment can be a tool for identification of defect levels detected by DLTS method, for it is the most convenient way to create the particular point defects uniformly distributed over the crystal volume. In the as-grown C-rich crystals, five electron traps labeled as T1A, T1B, T2, T3 and T4 with activation energies 0.34, 0.40, 0.64, 0.67 and 0.69 eV, respectively, were revealed. After the irradiation with a dose of ~2E17 cm(-2) of 0.3-MeV electrons the traps T1A (0.34 eV) and T1B (0.40 eV) disappeared and a new electron trap T1C (0.50 eV) was formed. The irradiation also resulted in the substantial increase of the concentrations of traps T2 (0.64 eV), T3 (0.67 eV) and T4 (0.69 eV). In the as-grown Si-rich crystals, the traps T1D (0.38 eV) and T1C (0.50 eV) were found. A strong effect of the energy of bombarding electrons on the formation of traps T1D (0.38 eV), T1C (0.50 eV) and T2A (0.52 eV) was observed. At the energy of 0.3 MeV, the trap T1D (0.38 eV) with the concentration of ~5E16 cm(-3) were found to be predominant. At the energy of 0.7 MeV, the predominant trap was T2A (0.52 eV) with the concentration of ~1E17 cm(-3). At the energy of 1.5 MeV the predominant traps were T1C (0.50 eV) and T2A (0.52 eV) with the concentrations of ~7E16 cm(-3). A model of the formation of point defects is proposed. The traps T1A (0.34 eV) and T1B (0.40 eV) are attributed to the carbon vacancy-carbon antisite complex V(C)C(Si) in different lattice sites, the trap T1C (0.50 eV) is likely to be the carbon vacancy-silicon vacancy pair V(C)V(Si), the trap T1D (0.38 eV) is identified with a carbon vacancy, the traps T2 and T3 are attributed to complexes involving a silicon vacancy and nitrogen atom in hexagonal and quasi-cubic sites, respectively, and the trap T4 (0.69 eV) is identified with the complex formed by nitrogen atom and carbon interstitial.
B6: Processing
Session Chairs
Wednesday PM, April 07, 2010
Room 2004 (Moscone West)
3:15 PM - B6.1
Analysis of Microstructure and Temperature Dependence of Contact Resistance of Ni/(Nb, Ta, Ti, V) Electrode on n-type 4H-SiC.
Kunhwa Jung 1 , Yuji Sutou 1 , Junichi Koike 1
1 Department of Material Science, Tohoku University, Sendai, 980-8579 Japan
Show Abstract Silicon carbide (SiC) is material for high temperature, high power and high frequency electronic devices. In order to operate SiC devices, metallic electrodes are necessary. One of the important requirements for the electrode materials is ohmic behavior with a low contact resistivity. A number of different metals have been proposed as the electrode materials for SiC. Nickel electrodes have been widely investigated for n-type 4H-SiC. In spite of the electrical benefits, there are major issues related to the microstructure of Ni on n-SiC; broadening of the metal SiC interface,; rough interface morphology with void formation,; excess carbon segregation,; and rough contact surface.In this research, various metals were inserted to the interface between the Ni electrode and the SiC substrate with an aim to improve these disadvantages of the Ni electrode, especially carbon segregation and void formation. We chose Nb, Ta, Ti and V as inserted metals by considering their carbide and silicide formation energies as well as kinetic parameters. Ni/(Nb, Ta, Ti, V) bi-layer films were deposited to the thickness of 80 nm/ 20 nm on SiC substrates by RF sputtering. A lift-off process was used to form a transmission-line-method (TLM) pattern. The obtained specimens were annealed at 1000 °C for 10 min under high vacuum condition to form ohmic contact. The microstructure was observed in cross section with a transmission electron microscope (TEM). The reaction phase was further examined by X-ray diffraction (XRD) for phase determination. Composition depth profile was investigated by secondary ion mass spectrometry (SIMS). Electrical properties which are related to barrier height and contact resistivity were characterized by current-voltage (I-V) measurements at 25, 100, 200 and 300 °C by using the TLM pattern. In all specimens after annealing, Ni was diffused across the inserted metal layer to the SiC substrate to form nickel silicide. Carbide formation prevented the presence of void and rough interface. All the inserted metals formed carbide and silicide with a good ohmic contact behavior, which indicate that the carbide did not interfere with the ohmic behavior of the metal-SiC contact. The contact resistivity, ρc, decreased with increasing measurement temperatures. Among the examined inserted metals, Nb had the best electrical properties, the barrier height was 0.34eV at room temperature. The ρc was 5.68E-4 Ωcm2 at room temperature and decreased to 3.08E-4 Ωcm2 at 300 °C, which is similar to that of Ni (8.47E-4 Ωcm2 at RT to 1.08E-4 Ωcm2 at 300 °C).
3:30 PM - B6.2
Investigation of SiO2 Cap for Al Implant Activation in 4H-SiC.
Feng Zhao 1 , Mohammad Islam 1 , Mvs Chandrashekhar 1 , Krishna Mandal 1 , Tangali Sudarshan 1
1 Electrical Engineering, University of South Carolina, Columbia, South Carolina, United States
Show AbstractSelective doping of SiC by ion implantation is an important fabrication technology. After ion implantation, the dopants must be thermally activated and substrate damage must be removed by high temperature annealing in the range of 1400~1700°C. The presence of severe surface roughening is observed on SiC implanted with Al or B followed by high temperature annealing, which deleteriously affects the device performance. To preserve the surface morphology, graphite and AlN encapsulation layers have been traditionally used during implant activation with effective protection demonstrated, but it is difficult to remove them after annealing. Graphite caps have to be ion milled, plasma ashed, or oxidized, all of which damage the underlying SiC. Using a plasma may introduce trapped charges at the SiC surface which degrades the inversion channel mobility in SiC MOSFETs. Removing AlN requires the use of KOH which also etches SiC and thus is not suited for device fabrication. In this paper, we investigate the use of SiO2 as an encapsulation cap for Al implant activation. Although when it is on Si, SiO2 only survives up to ~1200°C, on SiC it survives higher temperatures to ~1600°C owing to the lower vapor pressure of Si over SiC. Unlike graphite and AlN caps, there is no process difficulty associated with SiO2 layer deposition on and removal from the SiC surface. The process is also compatible with Si-processing technology benefiting from a lower cost.Two 4H-SiC samples with pin diodes were used in this investigation. After Al implantation to form the p-type active region and JTE region, the samples were annealed at 1400°C for 10 min for activation. One sample was capped with a graphite layer and the other sample with SiO2 by PECVD, both 1 um thick. After annealing, the graphite cap was removed by thermal oxidation at 1000°C for 1 hour, and the SiO2 cap by dilute HF for 5 min. Surface roughness was measured using AFM with a scanned area of 50×50 um2. Table 1 summarizes the surface roughness after implantation and annealing, the minimum forward leakage current J0 and maximum breakdown voltage VBR from diodes on both samples. It shows that the surface roughness was improved after annealing, and both graphite and SiO2 caps protected the SiC surface effectively. The low J0 confirms the high quality of diode junctions. The lower VBR from sample #2 was attributed to the fact that the temperature and time were not optimized for SiO2 capped annealing. Further investigation will be performed and the results will be reported in the conference. The authors thank the Southeast Center for Electrical Engineering Education (Grant No. SCEEE-09-001) and Dr. H. Scott Coombe of ONR (Grant No: N000140910619) for their support of this research.
4:15 PM - **B6.3
Afterglow Chemical Processing for Oxide Growth on Silicon Carbide.
Andrew Hoff 1 , E. Short, III 1 , H. Benjamin 1 , E. Oborina 1
1 , University of South Florida, Tampa, Florida, United States
Show AbstractThe unique capabilities and characteristics provided by afterglow or remote plasma chemical oxide growth processing of silicon carbide are reviewed. Such processing provides for thermal growth of oxide films at temperatures far below those employed by conventional atmospheric processing methods. Overshadowing this growth capability is the ability to create chemistries, sequential procedures, and specific process environments to address material and defect issues in a manner not possible under conventional atmospheric conditions. The details and outcomes of multi-step afterglow oxidation processing of SiC will be discussed. An example sequence might include; 1) Surface conditioning, 2) Film growth at 850C and 1 Torr total pressure, and 3) Reduced pressure unexcited media post-growth treatments. Surface conditioning impacts the thickness uniformity of the final oxide film and the oxidation rate. The film growth interval produces a nominal 50nm of oxide film in 90 minutes at 850C, a temperature that would not produce any significant oxide film at atmospheric pressure. And the post-growth processing improves the performance of the dielectric film. Using in-line corona-Kelvin metrology the characteristics of these processes have been determined. Electrical effective oxide thickness results were used to assess thickness uniformity and to estimate process activation energies for comparison to other process methods. Fowler-Nordheim, F-N, characteristics determined with the same metrology demonstrate that afterglow, AG, oxides require higher field levels to produce the same F-N current as thermal oxides and that AG films are less susceptible to stress fluence. Process extensions from these and other results are discussed and related to chemical, physical, and electrical film outcomes and potential pathways to improve control over dielectric SiC structures.
4:45 PM - B6.4
Optimization of Poly-silicon Process for 3C-SiC Based MOS Devices.
Romain Esteve 1 2 , Adolf Schoener 1 , Sergey Alexander Reshanov 1 , Carl-Mikael Zetterling 2
1 Nanoelectronics, ACREO AB, Kista, Stockholm, Sweden, 2 Information and Communication Technology, KTH, Kista, Stockholm, Sweden
Show AbstractCubic 3C-SiC is regarded as a perfect material for medium power MOSFETs with blocking voltages of around 1500 V and current handling of 100 A and more. One of the main issues to realize such power MOSFETs is the improvement of the MOS gate to ensure low on-state resistance operation.The benefits of the implementation of an advanced oxidation process combining PECVD SiO2 deposition and short post-oxidation steps in wet oxygen has been previously demonstrated [R. Esteve et al., J. Appl. Phys. 106, 044514 (2009)]. The concentrations of fixed and mobile charges in the oxide and at the SiO2/SiC interface were significantly reduced. But the optimization of the gate material is still an issue. The experiences from silicon technology point in the direction of using a poly-Si gate for MOS controlled devices. Significant improvements in terms of gate oxide reliability could be achieved by applying a poly-Si gate. But the usage of hydrogen for passivation of defects in oxides grown on 3C-SiC gives restrictions to the poly-Si deposition and activation process conditions. A reduced thermal budget is required to preserve the high electrical properties of the oxide.We investigated the electrical properties of MOS structures prepared with poly-Si gates. The poly-Si layer was deposited by the LPCVD technique mixing Si2H6 and PH3 at 380°C. The poly-Si activation has been carried out with five different methods. The influence of the following two main parameters has been considered: the process duration (thermal annealing or rapid thermal annealing) and the gas atmosphere (argon, dry or wet oxygen).MOS capacitors were fabricated on the oxidized free-standing n-type 3C-SiC (001) wafers with 5 µm low nitrogen doped (5×1015 cm-3) epitaxial layers. The MOS capacitors were characterized on the wafer level (about 200 MOS structures per wafer) by capacitance-conductance-voltage (C-G-V) measurements using a HP4284A LCR meter in the frequency range of 100 Hz to 1 MHz. The measurements were performed at room temperature in a light-tight and electrically shielded environment. The interface trap densities Dit were extracted by the conductance method. To assess the oxide reliability, time-zero dielectric breakdown (TZDB) measurements were conducted on the fabricated MOS structures.The optimized poly-Si activation process based on RTA in argon has minimal thermal budget and preserves the oxide and interface quality. The fabricated MOS structures demonstrate high electrical properties and reliability of the oxide: A small negative flat band voltage shift of -1 V and an interface state density Dit of 4.6×1011 eV-1cm-2 at 0.63 eV below the conduction band. The TZDB measurements revealed an average breakdown electric field of 9.4 MV/cm.
5:00 PM - B6.5
Self-aligned Process for SiC Power Devices.
Tomoko Borsa 1 2 , Bart Van Zeghbroeck 1 2
1 , TrueNano Inc., Boulder, Colorado, United States, 2 Department of Electrical, Computer, and Energy Engineering, University of Colorado at Boulder, Boulder, Colorado, United States
Show AbstractSilicon carbide is a semiconductor with desirable material properties, such as a wide bandgap and high thermal conductivity. It is an excellent material for constructing power switching devices operating in harsh environments where conventional semiconductors cannot adequately perform. One example of such a power device is a bipolar junction transistor (BJT). While the potential of the SiC BJT is recognized, appropriate techniques for producing devices is lacking due to its difficulty.For example, in order to achieve a high voltage 4H-SiC BJT switch with nanosecond switching time, the device must have a low base resistance. The simulation results indicate that for an emitter width of 2.0 μm and a base width of 1.2 μm the distance between the two should be 0.4 μm or less to meet the requirement for base resistance. To produce the above-described geometries and spacing, it is desirable to construct the device in a self-aligned manner. Self-alignment in this context means that the relative spacing of features of the device, such as contacts, is automatically controlled by the processing sequence and process parameters, rather than by the careful alignment prior to exposure of a photo sensitive layer. For this purpose, we developed a novel self-aligned process for SiC BJT devices, that enables the fabrication of the design with high yield, as standard silicon self-aligned technique are not applicable.The newly developed process starts with the deposition of the emitter contact metal, which provides the metal mask for the etching of the emitter ridges. Next, the wafer is planarized with photoresist and etched, so that only the emitter contacts are exposed. Electroless plating is then used to enlarge the contacts, and after removal of the resist, the plating provides an overhang, suitable for lift-off of the base contact metal. After the base contact metal deposition, the structure is planarized and etched, this time with a silicon dioxide layer, again exposing the plated emitter contacts and the lift-off step is the wet etching of the plated metal. The emitters are then all connected with a blanket wiring level, which also forms the base contact pad. This process is simpler and more robust than the process we developed to date. The main difference is the inclusion of a sacrificial lift-off overhang, created by electroless plating. It enables a well controlled overhang independent of steepness of the SiC ridge profile and the height of the emitter mesa. We successfully fabricated the overhang structure on 4H-SiC substrates.In conclusion, we report the demonstration of a new self-aligned process, which provides a self-aligned emitter contact, a self-aligned base contact and eliminates the need for via holes smaller than the emitter stripe widths. We consider this new process a major improvement over existing processes to fabricate SiC BJT devices.
5:15 PM - B6.6
Improved Inversion Channel Mobility in Si-face 4H-SiC MOSFETs by Phosphorus Incorporation Technique.
Dai Okamoto 1 , Hiroshi Yano 1 , Shinya Kotake 1 , Kenji Hirata 1 , Tomoaki Hatayama 1 , Takashi Fuyuki 1
1 Graduate School of Materials Science, Nara Institute of Science and Technology, Ikoma, Nara, Japan
Show AbstractIt is well known that the interface state density, channel mobility, and reliability of 4H-SiC MOSFETs strongly depend on the crystal face and oxidation process. Recently, we have reported that the interface state density near the conduction band edge can be decreased by over-oxidation of P-implanted 4H-SiC. However, the P-implanted MOS capacitor showed a slightly higher value of interface state density compared to the N-implanted one, which could be attributed to the larger implantation damage due to heavier P ions. In this report, we propose a new technique to reduce the interface state density near the conduction band edge by incorporation of phosphorus atoms into the SiO2/SiC interface.MOS capacitors were fabricated on n-type Si-face 4H-SiC epitaxial substrates. Dry oxidation was performed at 1200 °C to form a 55-nm-thick SiO2 film. Then, the samples were annealed in a gas mixture of phosphorus oxychloride (POCl3), oxygen and nitrogen at a high temperature to introduce P atoms into the SiO2/SiC interface. Al was evaporated to form gate and backside electrodes. Post-metallization annealing was carried out in pure nitrogen at 400 °C for 30 min. Similarly, planar n-channel MOSFETs were fabricated on n-type Si-face 4H-SiC substrates with a 5-μm-thick p-type epilayer. The net acceptor concentration of the p-epilayer was 7 x 1015 cm-3.Capacitance and conductance measurements of the MOS capacitors revealed that the interface state density near the conduction band edge was significantly reduced by the P incorporation. The interface state density at Ec - E = 0.3 eV was mid-1010 cm-2eV-1 for the sample annealed at 1000 °C in the phosphorus-containing gas. This value is two orders of magnitude smaller than that of a dry oxide (~1012 cm-2eV-1). The flat-band voltage was -0.2 V. In high-frequency C-V measurements, hysteresis was not observed for all samples. The fabricated MOSFETs showed normally-off operation, and the peak value of field-effect mobility reached 89 cm2/Vs. This value is much higher than that of dry oxide (~5 cm2/Vs). The threshold voltage, determined by linear extrapolation of Id-Vg curves to zero was approximately 0 V. This small threshold voltage implies a small number of negative charges trapped at the interface. The incorporation of P into the interface is a promising method to fabricate high-performance 4H-SiC MOSFETs.
B7: Poster Session
Session Chairs
Thursday AM, April 08, 2010
Salon Level (Marriott)
9:00 PM - B7.1
Effects of Doping Concentrations on Characteristics of Porous 3C-SiC Films.
Gwiy Chung 1 , Kang-San Kim 1
1 School of Electrical Enginnering, University of Ulsan, Ulsan Korea (the Republic of)
Show Abstract Prous SiC (pSiC) structures consisting of many pores and pillars are widely used to yield efficient visible photoluminescence (PL) at room temperature. Such light-emission behaviors are primarily attributed to electron confinement in the nano-crystals that constitute the porous structure. Moreover, several reports on pSiC have been already published for applications of light emitting device, bio MEMS, and chemical and bio sensors. However, the variation of porous structures with doping concentration for control of their properties is important. As doping process is widely used to control of there properties and it will effect to formation of electron-hole pairs. Therefore, doping will influence to porous structures. This paper describes the effect of n-type in-situ doping concentrations on the characteristics of pSiC structures. In this work, a conventional, hot-wall, horizontal reaction tube was used to deposit of poly 3C-SiC thin films on p-type Si substrates using HMDS (Si2(CH3)6). High purity N2 was injected as a dopant source gas and flow rate was 0, 10, 40 and 100 sccm, respectively. pSiC layers were formed by electrochemical anodization of the doped 3C-SiC films grown on p-type Si substrates, in HF solution (HF : H2O : C2H5OH = 1 : 1 : 2) with current density of 7.1 mA/cm2. Anodization was performed using a Pt mesh as the counter electrode under 380 nm UV-LED illuminations for 60 sec. Surface morphology and chemical bonding were evaluated by SEM and FT-IR, respectively. Emission wavelength ranges of thin films and pSiC were from 480 ~ 500 nm when the excitation wavelength was 325 nm. Carrier concentration was saturated after 40 sccm N2 flow rate. Si-C bonding of 3C-SiC was appeared at 800 cm-1 in thin film and pSiC. In case of porous, full width half maximum was improved about 20 cm-1 compare with thin film. These results are similar with stress relaxation of pSi. Si-H bonding was detected around 2100 cm-1. SEM images of thin film and pSiC, respectively. 50~70 nm porous was achieved at 0 sccm N2 flow rate with 7.1 mA/cm2 and 380 nm UV-LED illumination for 60 sec. Finally. photoluminescence spectra of thin film and pSiC at room temperature show the band gap (2.5 eV) of un-doped thin film and pSiC, respectively. Therefore, this pSiC film has many potential applications in chemical and bio sensor fields.
9:00 PM - B7.10
Diffusivity of Si in the 3C-SiC Buffer Layer on Si(100) by X-ray Photoelectron Spectroscopy.
Wei-Yu Chen 1 , Jian-You Lin 1 , Jenn-Chang Hwang 1 , Chih-Fang Huang 2
1 Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan, 2 Department of Electrical Engineering, National Tsing Hua University, Hsinchu Taiwan
Show AbstractA void free 3C-SiC film grown on Si(100) can be achieved by low pressure chemical vapor deposition using the modified four-step method. The diffusion step plays an important role to enhance the quality of the 3C-SiC buffer layer on Si(100). X-ray photoelectron spectroscopy was used to characterize the bonding characteristics of the 3C-SiC buffer layer of about 10 nm thick. The Si-C bonds are partially formed on the as-carburized Si(100) before the diffusion step. The ratio of C-C to Si-C bonds on the as-carburized Si(100) is about 7:3, which can be lowered to about 1:9 after the diffusion step at 1350 oC for 5 min or at 1300 oC for 7 min. The XPS C1s core level profile, which fits with Fick’s second law, shows that the relative amount of Si-C bonds is a function of temperature and time. The derived activation energy is 3.86 eV for the diffusion of Si atoms in the 3C-SiC buffer layer. The growth kinetics in the 3C-SiC buffer layer is discussed based on the diffusion coefficient data.
9:00 PM - B7.12
Phosphorus Oxide Assisted n-type Dopant Diffusion in 4H-Silicon Carbide.
Suwan Mendis 1 , Chin-che Tin 1
1 Physics Department, Auburn University, Auburn, Alabama, United States
Show AbstractPhosphorus, being a group (V) element, is an important n-type dopant for semiconductor substrates. Although thermal diffusion of phosphorus in silicon has been well documented and experimentally proven, there is much scope for the development of phosphorus as an effective thermal diffusant in silicon carbide, especially at lower temperatures. A thorough investigation is conducted in to the probable reactions between silicon carbide and phosphorus oxide at temperatures below 1700 Kelvin using tabulated thermodynamic data. The effectiveness of phosphorus as an n-type dopant in 4H-silicon carbide is discussed based on the reactivity between silicon carbide and phosphorus oxide below 1700 Kelvin. When considering the standard free energies of the probable reactions, it is implied that Phosphorus is an effective thermal diffusant for silicon carbide at temperatures below 1700 Kelvin. Bearing in mind that the most commonly used methods for introducing impurities into silicon carbide at the present, which include ion implantation, thermal diffusion and in-situ doping during crystal growth by chemical vapor deposition, are costly and require considerably higher temperatures than 1700 Kelvin, oxide aided thermal diffusion of phosphorus at lower temperatures seems to be a more viable option. Therefore, an experimental process is described to diffuse phosphorus into 4H- silicon carbide at lower temperatures.
9:00 PM - B7.13
Luminescence Mechanisms in 6H-SiC Nanostructures: Evidence of Quantum Confinment Effect.
Jacques Botsoa 1 , Jean-Marie Bluet 1 , Vladimir Lysenko 1 , Olivier Marty 1 , Larbi Sfaxi 2 , Gerard Guillot 1
1 , INL, Villeurbanne France, 2 , LPSCE, Monastir Tunisia
Show AbstractThe photoluminescence (PL) of porous SiC (PSC) nanostructures obtained by electrochemical anodization etching have been discussed in literature by various authors.1-4 Radiative recombinations via surface states and impurity levels have been put forward most of the time as the main mechanisms of the observed PL signals 1-3. A first clear experimental evidence of quantum confinement was announced only recently in colloidal 3C-SiC nanocrystallites.4 We report here how the PL mechanisms related to radiative transitions via surface and impurity levels in the 6H-SiC nanocrystallites can be quenched allowing clear manifestation of quantum confinement effect.Strongly interconnected SiC (3C or 6H) nanocrystals forming a porous network were obtained by electrochemical anodization etching of a low resitivity n-type 6H-SiC wafer. The etching process took place under UV illumination using a 1:1 HF(50%)/ethanol electrolyte. The SiC nanopowder was then obtained by mechanical grinding of the formed porous layer. The nanopowder dispersed in ethanol formed colloidal suspensions. TEM micrograph reveal the existence of large nanoparticles (>10nm) and small ones (<10 nm) which are expected to exhibit quantum confinement effect. PL measurements performed on 6H-SiC porous layer and nanopowder give broad peaks with maximum emissions below the gap of the bulk substrate. PL measurements were performed on 6H-SiC dry nanopowder, on the napowder wetted with ethanol and the nanopowder after ethanol evaporation. For the dry nanopowder, subgap emissions are linked to radiative recombination processes involving N-Al donor-acceptor centres (2.65eV) as well as numerous surface states (2.3eV) appearing in the bandgap of the porous SiC nanostructures. For the wet nanopowder, a narrowing of the PL peak around the re-gion corresponding to the radiative transition between N-Al levels is observed together with an increase of the global PL intensity. The observed enhancement can be explained by the efficient electrostatic screening of surface states by ethanol molecules which enhances the role of the other radiative mechanisms.PL measurements were then performed at different stages of centrifugation of the suspension. As expected from size selection, the emission is pushed further into the UV upon centrifugation. This UV emission corresponds to nanoparticles of given sizes exhibiting quantum confinement. Furthermore, photoluminescence excitation and absorption spectra obtained on this colloidal nano-suspension give information on formed energy subbands in the 6H-SiC nanocrystals. In summary, our work answers the important question why quantum confinement effect was not clearly observed before in porous SiC nanostructures. 1.A. O. Konstantinov, et al. Appl. Phys. Lett., 66, 2250 (1995). 2.O. Jessensky, et al. Thin Solid Films, 297, 214 (1997). 3.V. Petrova-Koch, et al. Thin Solid Films, 255, 107 (1995).4.X. L. Wu, et al. Phys. Rev Lett., 94, 026102 (2005).
9:00 PM - B7.14
Ultra-rapid Reactive Chemical Mechanical Planarization (RCMP) of Silicon Carbide Substrates.
Rajiv Singh 2 1 , Arul Chakkaravarthi Arjunan 1 , Abhudaya Mishra 1 , Deepika Singh 1
2 Materials Science Engineering, University of Florida, Gainesville, Florida, United States, 1 , Sinmat, Gainesville , Florida, United States
Show AbstractPresently one of the outstanding challenges is the affordable, rapid volume production of epi-ready Silicon Carbide wafers. As Silicon Carbide isrelatively chemically inert and mechanically hard, aggressive polishing methods involving very hard particles (such as diamond, silicon carbide and alumina particles) have been used to achieve high removal rates, but such methods create a high degree of sub-surface damage and scratches. Current polish rates are typically <100 nm/h for Si faced 6H-SiC substrate. Polishing processes based on softer particles such as colloidal silica have shown promise with reduced sub-surface damage and optical surface finish; however the extremely slow nature of the process makes it unsuitable for low cost production technology. We have developed novel ultra-rapid reactive CMP (RCMP) process for planarization of Silicaon carbide substrates. This RCMP process is >10 times faster than the current state of the art methods. Removal rates between 1µm/h to 5µm/h, along with atomically smooth damage-free surfaces with RMS roughness ~1Å has been achieved. Electrical and materials characterization tests using MOS devices have indicated that such surfaces show enhanced epigrowth characteristics and fewer polishing related defects compared to substrates that are polished by standard CMP process. Due to its ability to create excellent surfaces for epi-growth and rapid polishing capability, the RCMP process is also ideal for polishing of Silicon Carbide substrates.
9:00 PM - B7.15
Ohmic Contacts to Wurtzite Silicon Carbide Using Polarization Technology.
Choudhury Praharaj 1
1 , Global Communication Semiconductors, Torrance, California, United States
Show AbstractWe present theoretical calculations for ohmic contact technology to wurtzite Silicon Carbide using thin Indium Gallium Nitride and Aluminium Indium Nitride cap layers. Spontaneous and piezoelectric polarization in Indium Gallium Nitride and Aluminium Indium Nitride cap layers gives rise to bound interface sheet charge density of the order of 1013 electrons per cm2, and built-in electric fields of the order of MV per cm. For Si-face p-type SiC, the large compressive strain in very thin InGaN and AlInN cap layers results in negative sheet charge densities and much lower tunneling widths for holes compared to bulk contacts. For C-face p-type SiC, pseudomorphic nitride layers yield no benefit over bulk contacts since positive interface sheet charge densities repel holes and give higher contact resistances. However, thick, relaxed cap layers lead to spontaneous polarization-based negative charge densities that attract holes, leading to lower contact resistances. The contributions of the heavy, light and split-off band holes to the total tunneling flux is taken into account in our calculations. All tunneling probabilities are calculated within the Wentzels-Kramers-Brillouin approximation. The presence of the appropriate cap layers leads to several orders of magnitude improvement in tunneling transmission probabilities, and in many cases, makes ohmic technology to SiC feasible. While the major difficulties are encountered contacts to p-type SiC, the effect of cap-based polarization technology on contacts to n-type layers is also discussed in this paper. Our calculations have relevance to contact technology for bipolar devices built from wide band-gap wurtzite semiconductors like heterojunction bipolar transistors, light-emitting diodes and lasers.