Andrew C. Kummel University of California-San Diego
Heiji Watanabe Osaka University
Iain Thayne University of Glasgow
Prashant Majhi SEMATECH/Intel
I1: Si MOSFET
Wednesday PM, April 07, 2010
Room 2012 (Moscone West)
9:00 AM - I1.1
Interfaces Chemistry and Lanthanum Diffusion in Poly-Si/TiN/La2O3/HfSiON/SiON/Si Stacks.
Rachid Boujamaa 1 2 3 , Nevine Rochat 2 , Roland Pantel 1 , Chantal Trouiller 1 , Eugenie Martinez 2 , Olivier Renault 2 , Blanka Detlefs 4 , Sylvain Baudot 1 , Virginie Loup 2 , Francois Martin 2 , Mickael Gros-Jean 1 , Francois Bertin 2 , Catherine Dubourdieu 3 Show Abstract
1 , STMicroelectronics, 850, rue Jean Monnet, 38926 Crolles France, 2 , CEA, LETI, MINATEC, F38054 Grenoble France, 3 , LMGP, CNRS, Grenoble INP, 3 parvis L. Néel, BP 257, 38016 Grenoble France, 4 , European Synchrotron Radiation Facility, 6 rue Jules Horowitz, F-38000 Grenoble France
Down-scaling of CMOS transistors for integrated circuits of the 32 nm technological node and below requires the implementation of new materials and more complex device structures. One of the best solutions is to integrate High-k dielectrics such as hafnium-based oxides and metal gates to reduce power consumption. However, keeping suitable threshold voltages (Vth) for CMOS in High-K Metal Gate device is challenging. To overcome this problem, capping layers are incorporated into the gate stack in order to modulate the gate work function. La2O3 capping layers have been reported to provide Vth shifts towards the nFET band edge, yielding the necessary decrease of the effective work function of the gate. The Vth shift is understood to be originating from La-induced dipoles at bottom-High-k interface. Up to now, studies have been focused on HfO2/SiO2 stacks. In this work, we analysed the stability and the interface chemistry of La2O3 capping layers inserted on HfSiON/SiON stacks and more particularly to the interdiffusion phenomenon that occurs at high temperature.The samples studied consist of Poly-Si (60 nm)/TiN (6.5 nm)/ La2O3 (0, 0.4, 1 nm)/ HfSiON (1.7 nm)/SiON (1.5 nm)/Si stacks with or without annealing. The gate is composed of Poly-Si deposited at 600°C on a TiN and an ultra-thin La2O3 capping layer deposited both using Physical Vapor Deposition (PVD). Deeper below the gate, an amorphous HfSiON gate dielectric is deposited using Metal Organic Chemical Vapor Deposition (MOCVD) on a thin interface layer (IL) SiON. Since the Vth shift is ruled by the amount of La atoms, none, 0.4 and 1 nm-thick La2O3 layers were processed. Samples consisting of the stack without La2O3 capping layers serve as a reference. To investigate diffusion of lanthanum in the full stack a spike annealing for 1.5s at 1065°C is performed on some samples. Such an anneal is usually performed as a dopant activation anneal.To evaluate the process conditions on the gate stack morphology, HRTEM analysis was performed. Chemical properties and structural changes were also investigated using EELS, SIMS depth profiles and FTIR-ATR techniques. The results show a clear evidence of down-diffusion of La atoms toward the HfSiON and SiON layers after the annealing process as well as the formation of La silicate structure. It was also found that formation of LaSixOy structure is accompanied with consumption of the IL, which may suggest that the postdeposition annealing caused lanthanum diffusion into the bottom HfSiON interface forming La-O-Si bonds, key to Vth tuning.Complementary Hard X-ray PhotoElectron Spectroscopy (HAXPES) analyses have been carried out at the European Synchrotron Radiation Facilities (ESRF) in order to study the composition and interfacial chemistry of the La2O3 layer. These results will also be presented.
9:15 AM - I1.2
Exploration of Higher-k Dielectrics for the Advanced Gate Stacks Using Combinatorial Pulsed Laser Deposition.
Martin Green 1 , Kao-Shuo Chang 1 2 , Peter Schenck 1 , Ichiro Takeuchi 2 Show Abstract
1 Materials Science and Engineering, NIST, Gaithersburg, Maryland, United States, 2 , U of Maryland, College Park, Maryland, United States
HfO2-based materials have been suggested to replace SiO2 dielectrics to reduce leakage current density (JL). However, with further scaling for advanced gate stacks, there is an increasing need to explore new dielectrics with dielectric constant (κ) > 20 (higher-k) to enhance the performance of devices. The goal of this research is to join the thin film deposition techniques of pulsed laser deposition (PLD) with combinatorial methodology to rapidly and systematically explore higher-κ gate dielectrics. Combinatorial methodology enables efficient generation of a comprehensive and uniform set of samples, and allows rapid screening as well. In our combinatorial screening approach for finding a higher-κ dielectric material, we have focused our study on ternary systems derived from HfO2, Y2O3, TiO2, and Al2O3, using libraries synthesized by PLD. In-situ metal-oxide-semiconductor capacitors (MOSCAPS) were created for electrical measurements, using a shadow mask. The dielectric constant (κ) of the individual component films have been extracted for reference. Using reflectometry, and an automated capacitance-voltage (C-V) probe station, we were able to map the composition, thickness, and capacitance across the library. Thus, the dielectric constant can be systemically extracted. We found, for example, that compositions rich in TiO2 and Y2O3 had higher κ (~ 100) than the other compositions in a HfO2-Y2O3-TiO2 ternary system, and could potentially replace HfO2 for advanced gate stack applications. In addition, by changing processing parameters, such as substrate temperature during deposition, and oxygen partial pressure, we are able to manipulate the dielectric constant of a film. We have observed TiO2, for example, κ ~ 30 at 600 °C, and 100 mTorr, while κ ~ 100 at 400 °C, and 60 mTorr, indicating microstructure dependent properties.
9:30 AM - I1.3
Cerium Dioxide High-k Thin Films Derived from Sol Gel Route as a Gate Dielectric in Advanced HK/MG Stacks.
Ashok Mahajan 1 , Anil Khairnar 1 , Vijaya Toke 1 Show Abstract
1 Dept of Electronics, North Maharashira University, Jalgaon, Maharashtra, India
Development of novel high-k/metal gate (HK/MG) stacks are highly desirable for the fabrication of CMOS devices for ultra large scale integrated (ULSI) circuits technology. Among the different high-k materials, now a days the CeO2 has achieved considerable attention to be used as a potential candidate for gate dielectric applications due to its excellent interface capabilities with the underlying semiconductor and with the top metal in the stack. In the present study, cerium dioxide thin films have been deposited on Si (100) substrates by the Sol-Gel spin coating technique wherein, the Cerium (III) chloride heptahydrate is used as a source of Ce with ethanol as a solvent.The citric acid is used to accelerate the rate of reaction. The deposited films were characterized by Ellipsometer (Phylips SD 1000) to study the refractive index and thickness. The equivalent oxide thickness (EOT) determined for the as deposited CeO2 thin films is in the range of 1.19 nm to 1.79 nm and the refractive index of 3.615 results in the optical dielectric constant of 13.2496. These deposited CeO2 films on Si substrate with lower EOT and compatible interface properties realizes its suitability to be used as gate dielectrics (HK) in HK/MG stacks for CMOS technology. The FTIR and electrical characterizations employed to study the chemical composition and dielectric constant, leakage current density respectively will be discussed in detail in full manuscript.
9:45 AM - I1.4
Oxygen Vacancy Mediated Dielectric Breakdown in High-k Gate Stacks.
Blanka Magyari-Kope 1 , Yoshio Nishi 1 Show Abstract
1 Electrical Engineering, Stanford University, Stanford, California, United States
The reliability of the high-k gate stack becomes a significant challenge with the continuous scaling of the metal-oxide-semiconductor-field-effect-transistors, due to the ultrathin oxides and defects in the gate stack. One of the key problems associated with ultrathin oxide layers is the degradation of the gate oxides under electrical stress, due to traps generated by defects, most probably defect levels corresponding to oxygen vacancies present in these materials. Therefore, the detailed understanding of the effect of oxygen vacancies both in the bulk oxides and at metal-HfO2, HfO2-SiO2 and SiO2-Si interfaces on the local structure, and electronic structure is crucial. First principles methods based on density functional theory and non-equilibrium Green’s function calculations are employed to provide a physical model of the breakdown mechanism; the thermodynamic stability, defect trap energies and interface vacancy segregation probabilities are calculated. Model systems that incorporate the atomistic description of a conductive filament formation starting from several layers in the gate oxides, including the interfaces are investigated. The thermodynamically most stable sites and the ones with a higher probability to attract more vacancies are identified and the effect on the tunneling current is calculated.
10:00 AM - **I1.5
Identifying Atomic Structure of the Electrically Active Defects in Gate Dielectric Stacks.
Gennadi Bersuker 1 Show Abstract
1 , SEMATECH, Austin, Texas, United States
The introduction of metal oxides (high-k dielectrics) for gate dielectric applications raises new issues for characterization due to their specific material properties, which are fundamentally different from the conventional silicon dioxide gate dielectric. Understanding reliability mechanisms is further complicated by the fact that high-k gate stacks usually represent multi-layer structures, with strong interaction between the materials forming the layers. This presents new challenges for interpreting electrical measurements, which, in general, are sensitive to even small concentrations of the electrically active defects. In this study, we connect electrical characteristics of metal/high-k (HK) gate stacks to specific atomic defects in the dielectric films. In particular, we focus on identifying defects nature by matching their structural parameters extracted from electrical measurements to those obtained by ab initio calculations. By using a recently developed analysis approach for random telegraph noise (RTN) and 1/f noise data, which takes into consideration multi-phonon relaxation processes induced by the charge trapping/detrapping in the dielectric, we have extracted characteristics of the traps in the interfacial SiO2 layer in HK devices. It is shown that the electron capture/emission times may be controlled by the trap structural relaxation (caused by the trapped electrons) rather than by the electron tunneling to/from the trap as generally assumed. Such strong dependency on defect relaxation energy allows for reliable extraction of its value, which can be used as a defect identifier along with the defect energy and capture cross-section characteristics. Complementary modeling of the gate leakage current evolution in HK devices during electrical stress using the same approach yields characteristics of the traps in the interfacial SiO2 layer contributing to the trap-assisted tunneling process (TAT). Based on the values obtained by RTN and TAT measurements, the electrically active defects are tentatively assigned to oxygen vacancies in various charged states; their structures and electronic characteristics studied by ab initio calculations were reported in the literature. In all cases, stress-induced traps were generated exclusively in the interfacial layer of the HK stacks, consistent with earlier findings that HK dielectrics are more stable than SiO2 relative to defect generation. Based on these findings, as well as an earlier TEM/EELS study of the elemental composition of the breakdown path, we propose that the breakdown path formation/evolution in the interfacial layer is associated with the growth of an oxygen-deficient filament facilitated by the grain boundaries of the overlaying high-k film. A proposed physical model successfully describes the temperature-dependent evolution of interfacial layer degradation through various breakdown phases.
10:30 AM - I1.6
Structures, Defects, and Electrical Properties of Amorphous Hafnia and Hafnium Silicates.
Chin-Lung Kuo 1 , Tsung-Ju Chen 1 Show Abstract
1 Materials Science and Engineering, National Taiwan University , Taipei Taiwan
In this study we have performed first principles molecular dynamics simulations to generate atomic structure models of amorphous hafnium oxides and hafnium silicates via a rigorous melt-and-quench scheme. The PBE0 hybrid density functional, which is expected to give improved prediction for the band gap, is adopted for the analysis of the electronic properties of materials. According to our structure models, the density of amorphous HfO2 is predicted to be 8.6 g/cm3, the average coordination number of O atom is around 3.06, and that of Hf atom is about 6.1, all smaller than that predicted by previous calculations. The band gap and static dielectric constants of a-HfO2 are predicted to be 5.51 eV and 22.7, respectively, in good agreement with recent experiments. The O vacancy formation energy is predicted to be around 9.05 to 10.17 eV, much higher than that in α-quartz. For hafnium silicates, our calculations show that the band gap of its crystalline form is much higher than that of the amorphous counterpart. The static dielectric constants of hafnium silicates are found to decrease nonlinearly with the Si concentration, consistent with most experimental observations. Our calculations also show that the O vacancy formation energies in hafnium silicates depend only on the local bonding configurations, rather than the silicon concentrations. In addition, we also investigate the structures of excess Si atoms in both crystalline and amorphous HfO2. Our results show that excess Si atoms can be easily incorporated into the hafnium oxide bond network with sizable energy gain. Several stable configurations of excess Si atoms in hafnium oxide have been identified, and their bonding and energetics will be demonstrated. Furthermore, the influence of the excess Si atoms on the electrical and dielectric properties of the HfO2 films has been investigated and will also be presented.
10:45 AM - I1.7
Initial ALD on Hydroxylized Si (001) Surface for Al2O3 Thin Film Growth With Tri-methylaluminum: A First Principles Study.
Dae_Hee Kim 1 , Dae-Hyun Kim 1 , Yong-Chan Jeong 1 , Hwa-Il Seo 2 , Yeong-Cheol Kim 1 Show Abstract
1 Department of Materials Engineering, Korea University of Technology and Education, Cheonan Korea (the Republic of), 2 School of Information Technology, Korea University of Technology and Education, Cheonan Korea (the Republic of)
The gate oxide of MOSFET was realized using the ALD technique as it is possible to delicately control the uniformity and thickness of the gate oxide film due to the slow growth characteristics of ALD on Si or GaAs surfaces. Among the gate oxide materials, Al2O3 has superior physical and electronic properties, such as a high band gap, high dielectric constant, and high breakdown field. Several aluminum precursors have been employed with O2, O3, H2O, or H2O2 reactants for the growth of high quality aluminum oxide thin films using the ALD process. We studied the initial ALD of tri-methylaluminum (TMA, Al(CH3)3) on a hydroxylized Si (001) surface with a size of 4×4 for Al2O3 thin film growth using DFT. The Al atom of TMA was positioned on the O atom of –OH via the interaction of the lone-pair electrons of the O atom with the Al atom on the hydroxylized Si (001) surface. The activation energy for TMA to produce a di-methylaluminum group (DMA or –Al(CH3)2) and CH4 was 0.50 eV. The formed DMA located on the O atom migrated to the inter-dimer site without any activation energy. The activation energy for DMA to produce a uni-methylaluminum group (UMA or –AlCH3) and CH4 was 0.21 eV. The Al atom of the second TMA was positioned on the O atom of –OH. The second TMA adsorbed near the first UMA was energetically more favorable than that adsorbed away from the first UMA because of the interaction between the C atom of the second TMA and the Al atom of the first UMA. This difference of the adsorption energies of the second TMA transferred to the difference of the activation energies for its reaction to produce DMA and CH4. However, the formed second DMA, irrespective of its location, was not affected by the first UMA due to its small size. Therefore, the activation energy for the second DMA was not affected by its location.
11:15 AM - I1.8
Improvement of the Electrical Quality of LaAlO3/Si Structures Using Atomic Oxygen Treatments.
Sylvain Pelloquin 1 2 , Guillaume Saint-Girons 2 , Carole Plossu 1 , Nicolas Baboux 1 , David Albertini 1 , Genevieve Grenet 2 , Guy Hollinger 2 Show Abstract
1 Composants Nanoélectroniques, Institut des Nanotechnologies de Lyon , Villeurbanne France, 2 Hétéroépitaxie et Nanostructures, Institut des Nanotechnologies de Lyon , Ecully France
In the seek for ultimate EOTs in CMOS technology, the thermodynamic stability of the gate oxide with respect to Si is critical, because the formation of interfacial SiO2 or silicate layers inevitably leads to an increase of the EOT. In its 45 nm technology, Intel has replaced silica by HfO2 as gate oxide. This has been done at the expense of an important technological complexity (gate last process), because amorphous HfO2 films crystallize at high temperature, and because their interface with silicon is not stable during dopant activation annealing.Our goal is to prepare high-k oxide/Si systems without any interfacial layer (IL). Among various candidates, LaAlO3 (LAO) represents an interesting alternative to HfO2 for advanced CMOS technologies. LAO has a high band gap of 5.6 eV and a large conduction band offset of 1.8 eV (1.5 eV for HfO2) with respect to Si. In its bulk crystalline phase, its dielectric constant is 25. In addition, bulk LAO is stable in air, thermally stable in contact to silicon up to 1000 °C and LAO films remain amorphous at temperatures as high as 800-900 °C. This may solve recrystallization issues existing for other high-k oxides and ensures anisotropy of electrical properties.Preliminary results showed promising properties for such a system [APL 91, 192909 (2007)]. However the dielectric properties of the films still must be improved. In this presentation, we will show that the use of atomic oxygen at some steps of the LAO deposition process can strongly improve the dielectric properties of the films. The LAO films were deposited on p-type Si (100) substrates by electron beam evaporation of crystalline LAO targets. Prior to the film deposition, native SiO2 was removed from Si substrates by thermal annealing under ultra-high vacuum. LAO was deposited at 400 °C in a controlled atomic / molecular oxygen ambient (total pressure ranging from 10-6 to 10-5). Atomic oxygen was produced using a RF-plasma cell. 95×95 sq. µm Ni(3 nm)/Au(300 nm) electrodes were formed by lift-off to obtain Metal-Oxide-Semiconductor (MOS) capacitors for electrical characterization.Atomic Force Microscopy (AFM) measurements have shown that our surface preparation and deposition process lead to flat surfaces at the atomic scale. The absence of a SiO2/silicate interfacial layer was confirmed by XPS and physical thicknesses were obtained by X Ray Reflectivity.Electrical C-V and I-V measurements have shown high quality results on as-deposited samples. EOT as small as 0.5 nm where obtained with leakage currents as low as a few 10-3 A.cm-2 at |VG - VFB| = -1 V (10 times lower when compared to molecular oxygen based processes).We are now exploring further processing steps to match CMOS technology requirements. Optimal post-deposition Rapid thermal Annealing treatments are investigated to minimize the density of interface states and to check the thermal stability of the heterostructures at high temperature.
11:30 AM - **I1.9
Interfacial Layer Scaling Strategies for Metal Gate / High-k Stacks on Silicon.
Martin Frank 1 , Takashi Ando 1 , Changhwan Choi 1 , Kisik Choi 2 , Chiara Marchiori 3 , Jean Fompeyrine 3 , Vijay Narayanan 1 Show Abstract
1 , IBM T.J. Watson Research Center, Yorktown Heights, New York, United States, 2 , GLOBALFOUNDRIES Inc., Yorktown Heights, New York, United States, 3 , IBM Research GmbH, Zürich Research Laboratory, Rüschlikon Switzerland
We will review high-k/channel interfacial layer scaling as a versatile strategy for end-of-the-roadmap scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) incorporating metal nitride gate electrodes and hafnium-based high-k gate dielectrics on silicon channels. Focus is on gate-first technology, i.e. on a fabrication sequence that includes a dopant activation anneal at 1000C or more. We will discuss multiple process options for interlayer scaling, demonstrating equivalent oxide thickness (EO