Symposium Organizers
Andrew C. Kummel University of California-San Diego
Heiji Watanabe Osaka University
Iain Thayne University of Glasgow
Prashant Majhi SEMATECH/Intel
I1: Si MOSFET
Session Chairs
Wednesday PM, April 07, 2010
Room 2012 (Moscone West)
9:00 AM - I1.1
Interfaces Chemistry and Lanthanum Diffusion in Poly-Si/TiN/La2O3/HfSiON/SiON/Si Stacks.
Rachid Boujamaa 1 2 3 , Nevine Rochat 2 , Roland Pantel 1 , Chantal Trouiller 1 , Eugenie Martinez 2 , Olivier Renault 2 , Blanka Detlefs 4 , Sylvain Baudot 1 , Virginie Loup 2 , Francois Martin 2 , Mickael Gros-Jean 1 , Francois Bertin 2 , Catherine Dubourdieu 3
1 , STMicroelectronics, 850, rue Jean Monnet, 38926 Crolles France, 2 , CEA, LETI, MINATEC, F38054 Grenoble France, 3 , LMGP, CNRS, Grenoble INP, 3 parvis L. Néel, BP 257, 38016 Grenoble France, 4 , European Synchrotron Radiation Facility, 6 rue Jules Horowitz, F-38000 Grenoble France
Show AbstractDown-scaling of CMOS transistors for integrated circuits of the 32 nm technological node and below requires the implementation of new materials and more complex device structures. One of the best solutions is to integrate High-k dielectrics such as hafnium-based oxides and metal gates to reduce power consumption. However, keeping suitable threshold voltages (Vth) for CMOS in High-K Metal Gate device is challenging. To overcome this problem, capping layers are incorporated into the gate stack in order to modulate the gate work function. La2O3 capping layers have been reported to provide Vth shifts towards the nFET band edge, yielding the necessary decrease of the effective work function of the gate. The Vth shift is understood to be originating from La-induced dipoles at bottom-High-k interface. Up to now, studies have been focused on HfO2/SiO2 stacks. In this work, we analysed the stability and the interface chemistry of La2O3 capping layers inserted on HfSiON/SiON stacks and more particularly to the interdiffusion phenomenon that occurs at high temperature.The samples studied consist of Poly-Si (60 nm)/TiN (6.5 nm)/ La2O3 (0, 0.4, 1 nm)/ HfSiON (1.7 nm)/SiON (1.5 nm)/Si stacks with or without annealing. The gate is composed of Poly-Si deposited at 600°C on a TiN and an ultra-thin La2O3 capping layer deposited both using Physical Vapor Deposition (PVD). Deeper below the gate, an amorphous HfSiON gate dielectric is deposited using Metal Organic Chemical Vapor Deposition (MOCVD) on a thin interface layer (IL) SiON. Since the Vth shift is ruled by the amount of La atoms, none, 0.4 and 1 nm-thick La2O3 layers were processed. Samples consisting of the stack without La2O3 capping layers serve as a reference. To investigate diffusion of lanthanum in the full stack a spike annealing for 1.5s at 1065°C is performed on some samples. Such an anneal is usually performed as a dopant activation anneal.To evaluate the process conditions on the gate stack morphology, HRTEM analysis was performed. Chemical properties and structural changes were also investigated using EELS, SIMS depth profiles and FTIR-ATR techniques. The results show a clear evidence of down-diffusion of La atoms toward the HfSiON and SiON layers after the annealing process as well as the formation of La silicate structure. It was also found that formation of LaSixOy structure is accompanied with consumption of the IL, which may suggest that the postdeposition annealing caused lanthanum diffusion into the bottom HfSiON interface forming La-O-Si bonds, key to Vth tuning.Complementary Hard X-ray PhotoElectron Spectroscopy (HAXPES) analyses have been carried out at the European Synchrotron Radiation Facilities (ESRF) in order to study the composition and interfacial chemistry of the La2O3 layer. These results will also be presented.
9:15 AM - I1.2
Exploration of Higher-k Dielectrics for the Advanced Gate Stacks Using Combinatorial Pulsed Laser Deposition.
Martin Green 1 , Kao-Shuo Chang 1 2 , Peter Schenck 1 , Ichiro Takeuchi 2
1 Materials Science and Engineering, NIST, Gaithersburg, Maryland, United States, 2 , U of Maryland, College Park, Maryland, United States
Show AbstractHfO2-based materials have been suggested to replace SiO2 dielectrics to reduce leakage current density (JL). However, with further scaling for advanced gate stacks, there is an increasing need to explore new dielectrics with dielectric constant (κ) > 20 (higher-k) to enhance the performance of devices. The goal of this research is to join the thin film deposition techniques of pulsed laser deposition (PLD) with combinatorial methodology to rapidly and systematically explore higher-κ gate dielectrics. Combinatorial methodology enables efficient generation of a comprehensive and uniform set of samples, and allows rapid screening as well. In our combinatorial screening approach for finding a higher-κ dielectric material, we have focused our study on ternary systems derived from HfO2, Y2O3, TiO2, and Al2O3, using libraries synthesized by PLD. In-situ metal-oxide-semiconductor capacitors (MOSCAPS) were created for electrical measurements, using a shadow mask. The dielectric constant (κ) of the individual component films have been extracted for reference. Using reflectometry, and an automated capacitance-voltage (C-V) probe station, we were able to map the composition, thickness, and capacitance across the library. Thus, the dielectric constant can be systemically extracted. We found, for example, that compositions rich in TiO2 and Y2O3 had higher κ (~ 100) than the other compositions in a HfO2-Y2O3-TiO2 ternary system, and could potentially replace HfO2 for advanced gate stack applications. In addition, by changing processing parameters, such as substrate temperature during deposition, and oxygen partial pressure, we are able to manipulate the dielectric constant of a film. We have observed TiO2, for example, κ ~ 30 at 600 °C, and 100 mTorr, while κ ~ 100 at 400 °C, and 60 mTorr, indicating microstructure dependent properties.
9:30 AM - I1.3
Cerium Dioxide High-k Thin Films Derived from Sol Gel Route as a Gate Dielectric in Advanced HK/MG Stacks.
Ashok Mahajan 1 , Anil Khairnar 1 , Vijaya Toke 1
1 Dept of Electronics, North Maharashira University, Jalgaon, Maharashtra, India
Show AbstractDevelopment of novel high-k/metal gate (HK/MG) stacks are highly desirable for the fabrication of CMOS devices for ultra large scale integrated (ULSI) circuits technology. Among the different high-k materials, now a days the CeO2 has achieved considerable attention to be used as a potential candidate for gate dielectric applications due to its excellent interface capabilities with the underlying semiconductor and with the top metal in the stack. In the present study, cerium dioxide thin films have been deposited on Si (100) substrates by the Sol-Gel spin coating technique wherein, the Cerium (III) chloride heptahydrate is used as a source of Ce with ethanol as a solvent.The citric acid is used to accelerate the rate of reaction. The deposited films were characterized by Ellipsometer (Phylips SD 1000) to study the refractive index and thickness. The equivalent oxide thickness (EOT) determined for the as deposited CeO2 thin films is in the range of 1.19 nm to 1.79 nm and the refractive index of 3.615 results in the optical dielectric constant of 13.2496. These deposited CeO2 films on Si substrate with lower EOT and compatible interface properties realizes its suitability to be used as gate dielectrics (HK) in HK/MG stacks for CMOS technology. The FTIR and electrical characterizations employed to study the chemical composition and dielectric constant, leakage current density respectively will be discussed in detail in full manuscript.
9:45 AM - I1.4
Oxygen Vacancy Mediated Dielectric Breakdown in High-k Gate Stacks.
Blanka Magyari-Kope 1 , Yoshio Nishi 1
1 Electrical Engineering, Stanford University, Stanford, California, United States
Show AbstractThe reliability of the high-k gate stack becomes a significant challenge with the continuous scaling of the metal-oxide-semiconductor-field-effect-transistors, due to the ultrathin oxides and defects in the gate stack. One of the key problems associated with ultrathin oxide layers is the degradation of the gate oxides under electrical stress, due to traps generated by defects, most probably defect levels corresponding to oxygen vacancies present in these materials. Therefore, the detailed understanding of the effect of oxygen vacancies both in the bulk oxides and at metal-HfO2, HfO2-SiO2 and SiO2-Si interfaces on the local structure, and electronic structure is crucial. First principles methods based on density functional theory and non-equilibrium Green’s function calculations are employed to provide a physical model of the breakdown mechanism; the thermodynamic stability, defect trap energies and interface vacancy segregation probabilities are calculated. Model systems that incorporate the atomistic description of a conductive filament formation starting from several layers in the gate oxides, including the interfaces are investigated. The thermodynamically most stable sites and the ones with a higher probability to attract more vacancies are identified and the effect on the tunneling current is calculated.
10:00 AM - **I1.5
Identifying Atomic Structure of the Electrically Active Defects in Gate Dielectric Stacks.
Gennadi Bersuker 1
1 , SEMATECH, Austin, Texas, United States
Show AbstractThe introduction of metal oxides (high-k dielectrics) for gate dielectric applications raises new issues for characterization due to their specific material properties, which are fundamentally different from the conventional silicon dioxide gate dielectric. Understanding reliability mechanisms is further complicated by the fact that high-k gate stacks usually represent multi-layer structures, with strong interaction between the materials forming the layers. This presents new challenges for interpreting electrical measurements, which, in general, are sensitive to even small concentrations of the electrically active defects. In this study, we connect electrical characteristics of metal/high-k (HK) gate stacks to specific atomic defects in the dielectric films. In particular, we focus on identifying defects nature by matching their structural parameters extracted from electrical measurements to those obtained by ab initio calculations. By using a recently developed analysis approach for random telegraph noise (RTN) and 1/f noise data, which takes into consideration multi-phonon relaxation processes induced by the charge trapping/detrapping in the dielectric, we have extracted characteristics of the traps in the interfacial SiO2 layer in HK devices. It is shown that the electron capture/emission times may be controlled by the trap structural relaxation (caused by the trapped electrons) rather than by the electron tunneling to/from the trap as generally assumed. Such strong dependency on defect relaxation energy allows for reliable extraction of its value, which can be used as a defect identifier along with the defect energy and capture cross-section characteristics. Complementary modeling of the gate leakage current evolution in HK devices during electrical stress using the same approach yields characteristics of the traps in the interfacial SiO2 layer contributing to the trap-assisted tunneling process (TAT). Based on the values obtained by RTN and TAT measurements, the electrically active defects are tentatively assigned to oxygen vacancies in various charged states; their structures and electronic characteristics studied by ab initio calculations were reported in the literature. In all cases, stress-induced traps were generated exclusively in the interfacial layer of the HK stacks, consistent with earlier findings that HK dielectrics are more stable than SiO2 relative to defect generation. Based on these findings, as well as an earlier TEM/EELS study of the elemental composition of the breakdown path, we propose that the breakdown path formation/evolution in the interfacial layer is associated with the growth of an oxygen-deficient filament facilitated by the grain boundaries of the overlaying high-k film. A proposed physical model successfully describes the temperature-dependent evolution of interfacial layer degradation through various breakdown phases.
10:30 AM - I1.6
Structures, Defects, and Electrical Properties of Amorphous Hafnia and Hafnium Silicates.
Chin-Lung Kuo 1 , Tsung-Ju Chen 1
1 Materials Science and Engineering, National Taiwan University , Taipei Taiwan
Show AbstractIn this study we have performed first principles molecular dynamics simulations to generate atomic structure models of amorphous hafnium oxides and hafnium silicates via a rigorous melt-and-quench scheme. The PBE0 hybrid density functional, which is expected to give improved prediction for the band gap, is adopted for the analysis of the electronic properties of materials. According to our structure models, the density of amorphous HfO2 is predicted to be 8.6 g/cm3, the average coordination number of O atom is around 3.06, and that of Hf atom is about 6.1, all smaller than that predicted by previous calculations. The band gap and static dielectric constants of a-HfO2 are predicted to be 5.51 eV and 22.7, respectively, in good agreement with recent experiments. The O vacancy formation energy is predicted to be around 9.05 to 10.17 eV, much higher than that in α-quartz. For hafnium silicates, our calculations show that the band gap of its crystalline form is much higher than that of the amorphous counterpart. The static dielectric constants of hafnium silicates are found to decrease nonlinearly with the Si concentration, consistent with most experimental observations. Our calculations also show that the O vacancy formation energies in hafnium silicates depend only on the local bonding configurations, rather than the silicon concentrations. In addition, we also investigate the structures of excess Si atoms in both crystalline and amorphous HfO2. Our results show that excess Si atoms can be easily incorporated into the hafnium oxide bond network with sizable energy gain. Several stable configurations of excess Si atoms in hafnium oxide have been identified, and their bonding and energetics will be demonstrated. Furthermore, the influence of the excess Si atoms on the electrical and dielectric properties of the HfO2 films has been investigated and will also be presented.
10:45 AM - I1.7
Initial ALD on Hydroxylized Si (001) Surface for Al2O3 Thin Film Growth With Tri-methylaluminum: A First Principles Study.
Dae_Hee Kim 1 , Dae-Hyun Kim 1 , Yong-Chan Jeong 1 , Hwa-Il Seo 2 , Yeong-Cheol Kim 1
1 Department of Materials Engineering, Korea University of Technology and Education, Cheonan Korea (the Republic of), 2 School of Information Technology, Korea University of Technology and Education, Cheonan Korea (the Republic of)
Show AbstractThe gate oxide of MOSFET was realized using the ALD technique as it is possible to delicately control the uniformity and thickness of the gate oxide film due to the slow growth characteristics of ALD on Si or GaAs surfaces. Among the gate oxide materials, Al2O3 has superior physical and electronic properties, such as a high band gap, high dielectric constant, and high breakdown field. Several aluminum precursors have been employed with O2, O3, H2O, or H2O2 reactants for the growth of high quality aluminum oxide thin films using the ALD process. We studied the initial ALD of tri-methylaluminum (TMA, Al(CH3)3) on a hydroxylized Si (001) surface with a size of 4×4 for Al2O3 thin film growth using DFT. The Al atom of TMA was positioned on the O atom of –OH via the interaction of the lone-pair electrons of the O atom with the Al atom on the hydroxylized Si (001) surface. The activation energy for TMA to produce a di-methylaluminum group (DMA or –Al(CH3)2) and CH4 was 0.50 eV. The formed DMA located on the O atom migrated to the inter-dimer site without any activation energy. The activation energy for DMA to produce a uni-methylaluminum group (UMA or –AlCH3) and CH4 was 0.21 eV. The Al atom of the second TMA was positioned on the O atom of –OH. The second TMA adsorbed near the first UMA was energetically more favorable than that adsorbed away from the first UMA because of the interaction between the C atom of the second TMA and the Al atom of the first UMA. This difference of the adsorption energies of the second TMA transferred to the difference of the activation energies for its reaction to produce DMA and CH4. However, the formed second DMA, irrespective of its location, was not affected by the first UMA due to its small size. Therefore, the activation energy for the second DMA was not affected by its location.
11:15 AM - I1.8
Improvement of the Electrical Quality of LaAlO3/Si Structures Using Atomic Oxygen Treatments.
Sylvain Pelloquin 1 2 , Guillaume Saint-Girons 2 , Carole Plossu 1 , Nicolas Baboux 1 , David Albertini 1 , Genevieve Grenet 2 , Guy Hollinger 2
1 Composants Nanoélectroniques, Institut des Nanotechnologies de Lyon , Villeurbanne France, 2 Hétéroépitaxie et Nanostructures, Institut des Nanotechnologies de Lyon , Ecully France
Show AbstractIn the seek for ultimate EOTs in CMOS technology, the thermodynamic stability of the gate oxide with respect to Si is critical, because the formation of interfacial SiO2 or silicate layers inevitably leads to an increase of the EOT. In its 45 nm technology, Intel has replaced silica by HfO2 as gate oxide. This has been done at the expense of an important technological complexity (gate last process), because amorphous HfO2 films crystallize at high temperature, and because their interface with silicon is not stable during dopant activation annealing.Our goal is to prepare high-k oxide/Si systems without any interfacial layer (IL). Among various candidates, LaAlO3 (LAO) represents an interesting alternative to HfO2 for advanced CMOS technologies. LAO has a high band gap of 5.6 eV and a large conduction band offset of 1.8 eV (1.5 eV for HfO2) with respect to Si. In its bulk crystalline phase, its dielectric constant is 25. In addition, bulk LAO is stable in air, thermally stable in contact to silicon up to 1000 °C and LAO films remain amorphous at temperatures as high as 800-900 °C. This may solve recrystallization issues existing for other high-k oxides and ensures anisotropy of electrical properties.Preliminary results showed promising properties for such a system [APL 91, 192909 (2007)]. However the dielectric properties of the films still must be improved. In this presentation, we will show that the use of atomic oxygen at some steps of the LAO deposition process can strongly improve the dielectric properties of the films. The LAO films were deposited on p-type Si (100) substrates by electron beam evaporation of crystalline LAO targets. Prior to the film deposition, native SiO2 was removed from Si substrates by thermal annealing under ultra-high vacuum. LAO was deposited at 400 °C in a controlled atomic / molecular oxygen ambient (total pressure ranging from 10-6 to 10-5). Atomic oxygen was produced using a RF-plasma cell. 95×95 sq. µm Ni(3 nm)/Au(300 nm) electrodes were formed by lift-off to obtain Metal-Oxide-Semiconductor (MOS) capacitors for electrical characterization.Atomic Force Microscopy (AFM) measurements have shown that our surface preparation and deposition process lead to flat surfaces at the atomic scale. The absence of a SiO2/silicate interfacial layer was confirmed by XPS and physical thicknesses were obtained by X Ray Reflectivity.Electrical C-V and I-V measurements have shown high quality results on as-deposited samples. EOT as small as 0.5 nm where obtained with leakage currents as low as a few 10-3 A.cm-2 at |VG - VFB| = -1 V (10 times lower when compared to molecular oxygen based processes).We are now exploring further processing steps to match CMOS technology requirements. Optimal post-deposition Rapid thermal Annealing treatments are investigated to minimize the density of interface states and to check the thermal stability of the heterostructures at high temperature.
11:30 AM - **I1.9
Interfacial Layer Scaling Strategies for Metal Gate / High-k Stacks on Silicon.
Martin Frank 1 , Takashi Ando 1 , Changhwan Choi 1 , Kisik Choi 2 , Chiara Marchiori 3 , Jean Fompeyrine 3 , Vijay Narayanan 1
1 , IBM T.J. Watson Research Center, Yorktown Heights, New York, United States, 2 , GLOBALFOUNDRIES Inc., Yorktown Heights, New York, United States, 3 , IBM Research GmbH, Zürich Research Laboratory, Rüschlikon Switzerland
Show AbstractWe will review high-k/channel interfacial layer scaling as a versatile strategy for end-of-the-roadmap scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) incorporating metal nitride gate electrodes and hafnium-based high-k gate dielectrics on silicon channels. Focus is on gate-first technology, i.e. on a fabrication sequence that includes a dopant activation anneal at 1000C or more. We will discuss multiple process options for interlayer scaling, demonstrating equivalent oxide thickness (EOT) of 0.4-0.6 nm in all cases. The carrier mobility impact of interlayer scaling will be addressed. The first class of approaches is based on increasing the dielectric constant of the interlayer. This can be achieved by nitrogen incorporation before or after high-k deposition, by process-induced metal silicate formation, or by deposition of a high-k bottom interlayer such as SrO that acts as a barrier against silicon oxidation.The second class of approaches is based on process-induced thinning (‘scavenging’) of the interlayer during the dopant activation anneal, either by an oxygen sink within the high-k layer or at the metal/high-k interface, or alternatively by a remote oxygen sink within the nitride gate electrode.
12:00 PM - I1.10
Stability of Rare-earth Scandate Dielectrics on Si(100).
Matthew Copel 1 , Nestor Bojarczuk 1 , Lisa Edge 1 , Supratik Guha 1 , Barry Linder 1
1 , ibm, Yorktown Hts, New York, United States
Show AbstractRare earth scandates are potential successors to HfO2, purportedly offering higher dielectric constants while remaining amorphous to high temperatures [1]. However, when in contact with silicon, silicate formation can drive decomposition into rare earth silicate and scandium oxide [2,3]. In this talk we report results for TbScO3/Si(100) devices fabricated by molecular-beam deposition in an oxygen ambient.Using medium energy-ion scattering (MEIS), we find that the two compounds of the scandate dielectric have much different reactivities with SiO2; pure Sc2O3/SiO2/Si(100) is inert toward silicate formation, while pure Tb2O3/SiO2/Si(100) readily reacts to form a silicate. This difference in reactivity drives phase separation during high temperature processing.When TbScO3 is deposited on an oxidized Si substrate, heating the sample causes the Tb oxide to react with the SiO2, while Sc oxide does not react. As a result, the Sc depth profile observed with MEIS becomes skewed toward the sample surface. Meanwhile, a Tb-rich layer can be found near the Si/dielectric interface. The SiO2 interfacial layer is incorporated into the silicate during the reaction, leaving a direct silicate/Si(100) interface. Similar results are found for DyScO3, indicating that the phase separation observed with MEIS is not a peculiarity of TbScO3, but a trend for rare-earth scandates. Strategies for reducing phase separation will be discussed.Electrical results for TbScO3/Si(100) show that with strict control of interfacial Si oxidation, competitive equivalent oxide thicknesses can be attained. Our results suggest that scandates are promising materials for gate dielectrics. However, there is room for future work in understanding the electrical implications of silicate formation, phase separation, and choice of rare-earth element.This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.1) C. Zhao, et al, Appl. Phys. Lett. 86, 132903 (2005).2) L. F. Edge, et al, Appl. Phys. Lett. 89, 062902 (2006).3) C. Adelmann, et al, Appl. Phys. Lett. 92, 112902 (2008).
12:15 PM - I1.11
Optimization of Composition Ratio in La–Al–O Gate Dielectrics for Advanced Metal/Higher–k Devices.
Hiroaki Arimura 1 , Takashi Ando 2 1 , Stephen Brown 2 , Andrew Kellock 3 , Alessandro Callegari 2 , Matthew Copel 2 , Richard Haight 2 , Heiji Watanabe 1 , Vijay Narayanan 2
1 , Graduate School of Engineering, Osaka University, Suita, Osaka, Japan, 2 , IBM T. J. Watson Research Center, Yorktown Heights, New York, United States, 3 , IBM Almaden Research Center, San Jose, California, United States
Show AbstractLanthanum aluminate (La-Al-O) is one of the most promising higher-k candidate materials for future complementary metal oxide semiconductor (CMOS) devices. However, the impact of La/Al composition ratio on equivalent oxide thickness (EOT) scaling and leakage current reduction has not been fully investigated yet. Previously, the use of Al and La incorporation for p- and n-FETs has been demonstrated [2, 3]. This implies the possibility of the flatband voltage (Vfb) tuning by changing the La/Al atomic ratio. In this study, we fabricated La-Al-O dielectrics with various La/Al compositions and investigated the electrical properties in a sub-1 nm EOT region.We fabricated MOS capacitors with TiN/La-Al-O/SiO2/Si gate stack using an in situ process. Al was deposited on SiO2 by sputtering, followed by La deposition. Then, in situ oxidation was carried out at room temperature to form La-Al-O. The La/Al composition was tuned by changing the thickness of each La and Al layer. This unit cycle was repeated until the total thickness reached the target, and then, a thin TiN layer was deposited by reactive sputtering without breaking vacuum. Thick TiN or poly-Si was deposited and subsequent annealings were performed.The absorption spectra obtained by vacuum ultraviolet (VUV) spectroscopy revealed that the bandgap energy (Eg) of the La-Al-O dielectrics increased with increasing the Al atomic ratio. The La-Al-O (La/Al=46/54) showed both a wide Eg (6.7 eV) and a high k-value (k~23) exceeding HfO2 and La2O3. The relationship between gate leakage current (4.9×10-2 A/cm2) and EOT (0.80 nm) for the La-Al-O with the optimized composition (La/Al=75/25) showed the advantage over HfO2 and La2O3 even after 1000°C annealing. Furthermore, the effect of nitridation of the La-Al-O layer on reducing both EOT and leakage current was revealed. Regarding Vfb controllability, it was found that the thermal budget after the La-Al-O formation plays a significant role in addition to the La/Al atomic ratio. In the temperature range below 475°C, a wide Vfb change (~1.2 V) was observed by changing the La/Al atomic ratio. The Vfb shift depending on the thermal budget in this mild temperature regime can be explained by activation of interface dipole and/or disappearance of fixed charges. On the contrary, the Vfb tuning range was reduced by 400 mV toward the Si conduction band edge after the 1000°C anneal. We attribute this transition to the La diffusion into the SiO2 layer. Our learnings highlight the importance of the optimization of the La/Al atomic ratio as well as a precise control of the subsequent thermal budget to implement the La-Al-O higher–k dielectrics for the future CMOS devices.This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.[1] M. Suzuki et al., J. Appl. Phys. 103, 034118 (2008).[2] H. S. Jung et al., VLSI Symp. Tech. Dig., 2005, pp. 232–233.[3] V. Narayanan et al., VLSI Symp. Tech. Dig., 2006, pp. 224–225.
12:30 PM - **I1.12
Remote Control of High-k Si Gate Stack Properties.
Naoto Umezawa 1
1 , National Institute for Materials Science, Ibaraki Japan
Show AbstractThe quality of the gate stacks in field-effect transistors (FETs) is mainly dominated by the two factors, i.e., the concentration of charged defects in an oxide layer and the oxide/silicon interfacial structure. Here we suggest new strategies for the reliability control of FETs. Firstly, a multivalent oxide has been successfully used for the reduction of charged defects in a high-permittivity (high-κ) oxide. Oxygen concentration in a dielectric oxide is relevant to the formation of charged defects, and thus the oxygen chemical potential μ(O) must be carefully optimized in the fabrication process. Our computational and thermodynamic investigations suggest that a multivalent oxide such as Ce-oxide act as an oxygen reservoir when deposited on a high-κ oxide, playing an important role in keeping μ(O) unchanged throughout the oxide film. This attributes the co-existence of CeO2 and Ce2O3 in such a multivalent oxide, which absorbs or exhales oxygen atoms depending on the environment. This condition is described by the formula, μ(Ce2O3) + μ(O) = 2μ(CeO2) where μ(CeO2) and μ(Ce2O3) are chemical potentials of CeO2 and Ce2O3, which were calculated from an enthalpy of formation of each compound. Our computational result based on the first-principles calculations showed that μ(O) determined by the condition gives a very small concentration of charged defects in La2O3. This clearly indicates that the deposition of a CeOx layer on top of the La2O3 would greatly reduce the formation of charged defects. The theoretical model has been validated by our experimental measurements for the flat-band voltages (Vfb) of La2O3–based gate oxides with and without the deposition of a CeOx layer. The result clearly showed that the charged defects are greatly reduced in CeOx/La2O3 compared to La2O3. This result suggests that the quality of a high-κ oxide can be remotely controlled by stacking a multivalent material on top of the high-κ oxide. The theoretical model is not restricted for the combination between La2O3 and CeOx but applicable to predicting the best multivalent oxide for a given high-κ oxide. The second application of the concept “remote control” is the oxide/silicon interfacial design. A recent requirement for the use of a high-κ oxide poses a new challenge in achieving an atomically abrupt interface between a high-κ oxide and a silicon substrate without a SiO2 interfacial layer. Our first-principles calculations exhibit doping with donors into HfO2 significantly increases the oxygen concentration, leading a great possibility of scavenging oxygen atoms from the neighboring SiO2 layer. This prediction has been supported by our experimental results for tantalum-doping into HfO2/SiO2/Si stacks. It was clearly shown that the thickness of the SiO2 layer is significantly decreased as depositing a tantalum oxide on top of HfO2.
I2: Novel Devices
Session Chairs
Wednesday PM, April 07, 2010
Room 2012 (Moscone West)
2:30 PM - **I2.1
High Mobility Channel Materials and Their Integration on Silicon.
Eugene Fitzgerald 1
1 DMSE, MIT, Cambridge, Massachusetts, United States
Show AbstractHigh mobility channels are a key aspect of continuing to improve MOSFET devices. Strained silicon, strained Ge channels will be reviewed with most of the talk focusing on the challenges of III-V channels, which offer some of the highest electron mobility in the practical semiconductors. Since high mobility electrons in III-V’s have been known for a long time, the key materials issues are the dielectric/III-V interface and the integration of III-V materials on silicon. We will review our research in both of these areas. Interestingly, low-hanging fruit produced by this research direction can have impact in high efficiency solar and integration of existing III-V devices with silicon CMOS. It is likely that a practical path to wide-range adoption of III-V channels will involve synergies with these additional applications areas.
3:00 PM - I2.2
Ultra-shallow NiPt Silicide Contacts for Sub-10 nm MOSFETs.
Bin Yang 1 , Paul Solomon 2 , Christopher D'Emic 2 , Zhen Zhang 2 , Chrisitan Lavoie 2 , Yun Wang 3 , Yu Zhu 2 , Dae-gyu Park 2
1 , GlobalFoundries, Yorktown Heights, New York, United States, 2 T.J. Waston Research Center, IBM, Yorktown Heights, New York, United States, 3 , Ultratech, San Jose, California, United States
Show AbstractAs devices scale and become more three-dimensional in nature, silicide contacts must also scale in thickness to accommodate the progressively shallower junctions. The silicide contact resistivity (ρc) becomes a dominant factor in parasitic resistance. To meet the requirements of future devices, ultra-thin silicides with low ρc and shallow, activated, high-concentration doping profiles are required. We previously demonstrated ρc below 1×10-8 Ω-cm2 using NiPt silicide [1] and ultra-fast annealing [2]. Here we extend these techniques to study silicide contacts of thicknesses as small as 4 nm. In this work, we focus on shallow NiPt silicide contacts on p+Si and have achieved very low contact resistivity in the mid 10-9 Ω-cm2 range by increasing the active dopant concentration near the surface with pre-silicide boron implant and laser annealing (LSA). 4 nm-thick NiPt silicide contacts are accomplished on p+Si with unprecedented contact resistivity of 4×10-9 Ω-cm2, which far exceeds ITRS requirements down to sub-10 nm MOSFET dimensions, thus promoting exploration of novel device structures with smaller contact areas.In principle, the same methodology can be applied to reduce contact resistivity for shallow contacts on n+Si.Acknowledgments: This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.[1] K. Ohuchi et al., IEDM Tech. Dig., 2007. [2] F. Pagette et al., MRS 2008.
3:15 PM - I2.3
Study of Metal/High-k (ALD-Al2O3 ) Interfaces.
Lior Kornblum 1 , Michael Lisiansky 2 , Yakov Roizin 2 , Moshe Eizenberg 1
1 Department of Materials Engineering, Technion - Israel Institute of Technology, Haifa Israel, 2 , Tower Semiconductors Ltd. P.O. Box 619, Midgal haEmek Israel
Show AbstractSuccessful integration of high-k dielectrics with metal gate electrodes is a crucial bottleneck for the advancement of the microelectronics industry. The high-k/metal interface is where the electrical properties of the gate are determined, thus making it the source of much scientific and technological interest. Al2O3(alumina) was selected as a high-k dielectric for this study. It is attractive especially for flash memory applications because of its high band gap and stability.Atomic Layer Deposited (ALD) alumina films were deposited on thermal oxide grown on (100) p-Si wafers followed by 900°C 30s rapid thermal processing at N2. Capacitors were formed by e-beam deposition of metals through a shadow mask. Post Deposition Anneal (PDA) was done at 400°C for 30 min at 10-6 Torr. High resolution transmission electron microscopy (HR-TEM) and high angle annular dark field (HAADF) scanning-transmission electron microscopy (STEM) imaging modes were used for microstructure characterization.Capacitance-Voltage (C-V) results show a flat band voltage (VFB) span larger than 1 V with Al, Ni and Pt as gate metals. This span is larger than that anticipated according to previous reports[1],[2]. Based on these results, Pt-Al bi-layers were used to achieve controlled VFB within this span, which is attributed to intermixing of the two elements.Furthermore, Ta was investigated as a gate electrode as well. Ta gate electrodes exhibit abnormal electrical behavior seen in increased accumulation capacitance (Cox) and increased VFB with respect to the results with other metals. Time of Flight Secondary Ion Mass Spectrometry results show a widening of the TaO signal at the interface post PDA, indicating intermixing or reaction. This is further supported by HR-TEM cross-section imaging and Z-sensitive HAADF STEM imaging, both showing a ~1 nm interface layer (IL) at the alumina/Ta interface. The formation of an IL can explain the increase in Cox of the Ta gated sample. The reduction of alumina by Ta, creating a Ta-oxide IL with a higher k value than alumina can increase the effective capacitance. The increase of VFB can be attributed to a possible preferred orientation of the Ta films - known to have an anisotropic work function. Alternatively, the VFB can be explained by the formation of the IL, resulting in charge transfer of surface dipoles[3-5].[1] Y.C. Yeo, et al., J. Appl. Phys. 92, 7266 (2002)[2] W. Mönch, J. Vac. Sci & Tech. B, 17, 1867 (1999)[3] H.C. Wen et al., J. Appl. Phys., 98, 043520 (2005)[4] H.N. Alshareef, et al., Thin Solid Films, 515, 1294 (2006)[5] L. Pantisano, et al., Appl. Phys. Let. 88, 243514 (2006)
3:30 PM - **I2.4
Tunneling MOSFETs Based on III-V Staggered Heterojunctions.
Peter Asbeck 1 , Lingquan Wang 1 , Siyuan Gu 1 , Yuan Taur 1 , Edward Yu 2
1 ECE, UCSD, La Jolla , California, United States, 2 ECE, University of Texas, Austin, Austin, Texas, United States
Show AbstractA critical problem for the progression of CMOS electronics to the nanoscale is the reduction of power density, while at the same time preserving high speed performance. One of the most promising approaches is to aggressively reduce the power supply voltage by making use of a novel device, the tunneling FET (TFET), which is a MOSFET that operates by tunnel-injection of carriers from source to channel, rather than by conventional thermionic emission. TFETs benefit from steep (sub-60mV/dec) gate turn-on characteristics. Among many possible TFET configurations [1-4], a TFET design based on staggered heterojunctions is particularly promising, since the choice of materials for the injector (source) and channel allow optimization of the tunneling probability at the heterojunction. This paper describes analysis and simulation of MOSFETs based on the GaAlSb / InGaAs material system. The energy difference between the valence band of the injector and the conduction band of the channel can be tailored over a wide range, from negative values (offset band lineup) to values in excess of 1eV. We find by simulation that for optimal values of effective heterojunction bandgap near 0.2eV, the resulting MOSFETs are capable of delivering >0.5mA/mm while maintaining on-off ratio greater than 10,000 over a voltage swing of 0.3V. III-V MOSFET design entails a variety of considerations that differ from the Si case: 1) higher peak velocity and ballistic injection velocity [5,6]; 2) reduced density of states, leading to lower current levels at a fixed fermi level vs Si [5,6]; 3) need for electrostatic confinement to shield the drain potential in small FETs, which is difficult to achieve with the larger wavefunction spread typical of III-Vs [7]; 4)"source starvation" in ballistic FETs, associated with the difficulty of maintaining thermal equilibrium in the source during ballistic current injection [5]; 5) oxide issues and interface characteristics [8,9]. This paper describes numerical simulations of device characteristics, and tradeoffs in device design in relation to band offsets, doping levels, and gate geometry.[1] J. Appenzeller et al., IEEE TED., vol. 52, pp. 2568-2576, Nov. 2005; [2]Q. Zhang et al IEEE EDL 27, 297 (2006); [3] O.M. Nayfeh et al., IEEE EDL,29,468, 2008; [4] W. Choi et al., IEEE EDL, 28, 743, 2007; [5] M. Fischetti et al J.Comp.Electr.1569-8025,2009; [6] M. Rodwell et al, IEEE IPRM 1, 2008; [7]Taur and Ning, Fundamentals of Modern VLSI devices, [8] P. McIntyre et al, Microelectr. Eng. 86, 1536 (2009) [9] M. Passlack et al, IEEE EDL 26, 713 (2005).
4:00 PM - I2.5
Transport Properties for Si Nanowire-channel MOSFETs Formed With Electron-beam-lithographically Patterned Ultra-narrow <100> and <110> Si Wires.
Sejoon Lee 1 , Youngmin Lee 2 , Han Tae Ryu 2 , You-mee Hyun 2 , Deuk Young Kim 2 , Hyunsik Im 2 , Toshiro Hiramoto 3
1 Quantum-functional Semiconductor Research Center, Dongguk University, Seoul Korea (the Republic of), 2 Department of Semiconductor Science, Dongguk University, Seoul Korea (the Republic of), 3 Institute of Industrial Science, University of Tokyo, Tokyo Japan
Show AbstractThe influence of quantum-mechanical narrow-channel-effect, which strongly depends on both the charge polarity and the direction of the narrow-channel, on the electron transport properties for Si nanowire-channel field-effect transistors (NW-FETs) has been investigated. Si NW-FETs were fabricated on a SOI substrate in the form of conventional three-dimensional Si MOSFETs. Si nanowire-channels oriented with <100> and <110> directions were patterned by using the electron-beam-lithography techniques, and the width (WNW) of Si nanowire-channel was varied from ~1.25 nm to ~16.25 nm (step: ~2.5 nm). The length of the channel was fixed to be 200 nm. For measurements of electron transport properties, the key parameters including the threshold voltage (Vth), subthreshold slope (S-factor), transconductance (gm), and drain-induced barrier lowering (DIBL) factor, showed to have strong dependence on the WNW of Si nanowire-channel; i.e., the key parameters for the NW-FETs were observed to be significantly dependent on the variation of WNW. Namely, with decreasing WNW, the increase of Vth, decrease of S-factor, decrease of gm, and increase of DIBL factor were clearly observed. These results are confirmed to be attributed to the quantum-mechanical narrow-channel effect and/or the variation of electrostatic force in the nanowire-channels. In particular, for NW-FETs consisting of the Si nanowire-channel with the WNW less than 3.75 nm, the above phenomena were observed to become very significant. In addition, it was also observed that the effects of quantum-mechanical narrow-channel effect on the transport properties for NW-FETs are closely correlated with the carrier polarity and the direction of the nanowire-channel. According to the calculation of energy band for <100> and <110> Si nanowires and the extraction of macroscopic model of the device, those features are confirmed to originate from a fact that quantum-confinement effects including a subband modulation and a variation of electrostatic potential profiles rely on both the charge polarity and the direction of the nanowire-channel. The impact of quantum-mechanical narrow-channel effects and its correlation with for transport properties for each Si NW-FET; i.e., <110> Si n-NW-FET, <100> Si n-NW-FET, <110> Si p-NW-FET, and <100> Si p-NW-FET, are to be discussed. And also, based on trade-off relationships in WNW-dependent transport properties for above four types of devices, we suggest the design guideline for the high performance Si NW-FETs.*Corresponding authorTel: +82-2-2260-3954 / Fax: +82-2-2260-3945 / E-mail:
[email protected]4:30 PM - I2.6
Compositional and Thermal Characterization of Amorphous Ta-W-Si-B Gates.
Melody Grubbs 1 , Xiao Zhang 2 , Michael Deal 2 , Yoshio Nishi 2 , Bruce Clemens 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Electrical Engineering, Stanford University, Stanford, California, United States
Show AbstractA rising concern with polycrystalline gates for MOSFETs is that device variability could become a problem as the gate dimensions scale and become comparable to the grain size. A reason for this concern is illustrated by work from C. Fall, et al. which shows that the tungsten work function ranges from 4.44 eV to 5.26 eV depending on the crystallographic orientation of the grain. [1] Amorphous metal alloy gates are being investigated here in order to determine whether work function variability can be reduced in nano-scale MOS devices if the different grain orientations are eliminated. Also, since integration via gate-first processing is desirable, an array of refractory transition metal-metalloid glasses containing Ta, W, Si, and B were chosen as the gate materials to be developed in this research. Note that some metallic glasses with the compositional form (TaxW(1-x))80Si10B10 have been shown to crystallize well above 1000°C. [2]The purpose of this study is to determine how the Ta/W ratio and the metalloid concentration affect the crystallization temperature and chemical stability of Ta-W-Si-B alloys. In order to accomplish this, the following Ta-W-Si-B alloys were deposited by four-target, dc co-sputtering onto 13Å of SiO2: (TaxW(1-x))80Si10B10 (20 < x < 60), (Ta0.33W0.66)(100-x)SixBx (2.5 < x < 12.5), Ta28W57Si10B5, and Ta28W57Si5B10. Through x-ray diffraction (XRD) and a series of anneals at 800, 900, 1000, and 1100°C, we have demonstrated that these materials remain mostly or completely amorphous for at least 10 minutes at 900°C. Also, since Ta28W57Si10B5 was shown through XRD to have a higher crystallization temperature than Ta28W57Si5B10, we have concluded that Si is more necessary than B for high temperature stable Ta-W-Si-B alloys. We hypothesize that this is the case because Si inhibits metal diffusion better than B due to its larger atomic radius. Additionally, SIMS was performed on select alloys in order to determine whether B diffuses through the oxide layer during annealing. We found that there was no difference between the unannealed samples and the ones annealed at 800°C; however, 900 and 1000°C Ta50W30Si10B10 samples showed significant B diffusion. However, for the Ta28W57Si10B5 sample annealed for 10 minutes at 1000°C, there was significantly less B diffusion. We will also report on the effective work functions of these alloys, the thermal and structural characteristics of an array of (Ta0.33W0.66)(90-x)Si10Bx compositions, and the effectiveness of a TaN diffusion barrier layer. We also determine whether C and N can replace B in our amorphous alloys and whether Ta-W-Si-C and Ta-W-Si-N alloys are suitable for gate first processing. [1]. C. J. Fall, et al. Theoretical Maps of Work-Function Anisotropies. APS. Phys. Rev. B, Vol. 65 (2001) 045401-1 – 045401-6[2]. T. Yoshitake, et al. Preparation of Refractory Transition Metal-Metalloid Amorphous Alloys and Their Thermal Stability. Mat. Sci. and Eng., 97 (1988) 269-271
4:45 PM - I2.7
Controlling Peripheral Leakage Currents in Ultra-narrow MOSFETs Using a Penta-Gate Approach.
Mustafa Akbulut 1 , Faruk Dirisaglik 1 , Helena Silva 1 , Ali Gokirmak 1
1 Electrical Engineering, University of Connecticut, Storrs, Connecticut, United States
Show AbstractWidth scaling of MOSFET structures is hampered by non-scaling peripheral drain-to-source and drain-to-substrate leakages caused by defects and fixed charges on the interface of the active region and the Shallow Trench Isolation (STI) [1].
Penta-Gate MOSFET employs a tri-gate structure built on bulk Si with an additional buried poly-Si side-gate structure that wraps around the body, separated from the body by a thin oxide. The side-gates are most effective at the either side of the active area, like two additional gates. These gates, controlled independently from the top gate, are utilized to accumulate the active area near the body-STI interface by electrostatically drawing the majority carriers from the substrate. In an NMOS transistor, for example, this means applying negative bias on the side-gates to attract holes [2].
In ultra-narrow devices, the effect of side-gates goes beyond the passivation of interface charges and can be used to accumulate the whole body, alleviating short-channel effects and tuning the threshold voltage [2].
Three-Dimensional device simulations using Sentaurus TCAD tools were employed for Penta-Gate structures with widths and lengths of as small as 15 nm. Decrease in off-current by up to two orders of magnitude was observed with changing bias on the side-gates; in addition to significant improvements in Subthreshold Slope (SS) when compared to a bulk Si tri-gate transistor with the same dimensions. Furthermore, minimum currents in fA regime have been attained in simulation of devices with 30 nm gate-length, while maintaining high on-currents.
Experimental results with sub-70 nm devices also indicate a strong Imax/Imin ratio of ~109, as well as a low SS, supporting the bid of Penta-Gate transistors as a low-power device.
As the scaling pushes the sub-22 nm gate length, Penta-Gate MOSFETs provide reduction in non-scaling leakage currents, as well as suppression of short channel effects in ultra-narrow devices, helping the width scaling with possible low-power applications [2].
References:
[1] P. Sallagoity, M. Ada-Hanifi, M. Paoli and M. Haond, "Analysis of width edge effects in advanced isolation schemes for deep submicron CMOS technologies," Electron Devices, IEEE Transactions on, vol. 43; 43, pp. 1900-1906, 1996.
[2] A. Gokirmak and S. Tiwari, "Threshold voltage tuning and suppression of edge effects in narrow channel MOSFETs using surrounding buried side-gate," Electronics Letters, vol. 41; 41, pp. 157-158, 2005.
5:00 PM - **I2.8
A Self-aligned Epitaxial Regrowth Process for Sub-100-nm III-V FETs.
Mark Rodwell 1 , Andrew Carter 1 , Greg Burek 1 , Mark Wistey 3 1 , Brian Thibeault 1 , Ashish Baraskar 1 , Uttam Singisetti 1 , Eun Kim 2 , Byungha Shin 2 , Joel Cagnon 1 , Yong-Ju Lee 5 1 , Susanne Stemmer 1 , Paul McIntyre 2 , Arthur Gossard 1 , Chris Palmstrom 1 , Bo Yu 4 , Denns Wang 4 , Peter Asbeck 4 , Yuan Taur 4
1 ECE, UCSB, Santa Barbara, California, United States, 3 Electrical Engineering, Notre Dame, South Bend, Indiana, United States, 2 Materials Department, Stanford University, Palo Alto, California, United States, 5 , Intel, Beaverton, Oregon, United States, 4 Electrical Engineering, UCSD, San Diego, California, United States
Show AbstractBecause of the low electron effective mass and the high resulting carrier velocities, MOSFETs with InGaAs channels are being investigated for potential application in VLSI circuits at scaling generations beyond 22 nm. In addition to formidable challenges faced in developing gate dielectrics with the necessary low interface state density, transistors must be built with ~ 20 nm gate lengths, ~5 nm channel thicknesses, and source and drain contacts of ~20 nm width separated by no more than 10-20 nm from the gate edges. In the ballistic transport limit, a FET with ~0.6 nm EOT gate dielectric would show ~5 mS/micrometer transconductance and 1.5 mA/micrometer drain current at 300 mV gate overdrive; hence even 20 Ohm-micron source and drain access resistivities would reduce the drive current by 10%. Given contacts 20 nm wide, source and drain contact resistivities should thus be below 0.4 Ohm-micron^2. At 300 mV gate overdrive, the inversion charge density is ~2.5E12/cm^2, hence the source electron density should exceed 5E12/cm^2 to avoid source starvation; this corresponds to 1E19/cm^3 in a 5 nm thick channel. The source and drain regions must be very heavily doped, yet the extrinsic source and drain junctions must be at most a few nm deep in order to obtain steep subthreshold slope and low drain-induced barrier lowering. To meet these electrical and structural requirements, the transistor design and process flow must differ markedly from that of III-V transistors now used in microwave amplification. Nor can silicon MOS processes be used, given that III-V materials have characteristics different from silicon and can tolerate only much lower process temperatures.Addressing these requirements, we have developed a process for fabrication of self-aligned III-V MOSFETs. The process has self-aligned in-situ source/drain Ohmic contacts and self-aligned N+ source/drain n+ regions formed by epitaxial regrowth. The epitaxial dimensions are small, as is required for 22 nm gate length MOSFETs; with a 5 nm thick channel confined below by a heterojunction, and the n++ source/drain junctions do not extend below the 5 nm channel.In this gate-first process, thin 5 nm InGaAs channels are grown by MBE and alumina gate dielectric deposited by ALD. The gate electrode is a sputter-deposited refractory metal patterned by reactive-ion etching, and device electrodes are separated by dielectric sidewalls. Self-aligned InAs source/drain N+ regions are defined by epitaxial (migration enhanced epitaxy, MEE) regrowth. These are doped at 4E19/cm^3, are 60 nm thick, and show 18 Ohm sheet resistivity. Source/drain contacts self-aligned to the gate are formed by in-situ blanket molybdenum deposition and a patterned by height-selective etching. Mesa isolation and pad contact complete the process. A device with 200 nm gate length showed 0.95 mA/micrometer current density at Vgs=4.0 V, and 0.45 mS/micrometer peak transconductance.
5:30 PM - I2.9
Tuneable CMOS and Current Mirror Circuit with Double-gate Screen Grid Field Effect Transistors.
Yasaman Shadrokh 1 , Kristel Fobelets 1 , Enrique Velazquez-Perez 2
1 Electronic and Electrical Engineering, Imperial College, London United Kingdom, 2 Departmento de Fisíca Aplicada, Universidad de Salamanca, Salamanca Spain
Show AbstractAs CMOS is scaling down with the aim of increasing operation speed and packing density, improved gate control is needed to manipulate the switching voltage as well as the gain factor of inverters. These requirements have driven research on Field Effect Transistors (FETs) towards devices with multiple gate configurations. One novel FET with multiple gates is the Screen Grid FET (SGrFET) where the gate system consists of cylinders inside the channel, on SOI, perpendicular to the current flow. This novel FET has shown promise in low power analogue applications and in digital circuits where its high functionality can be exploited to minimize the number of devices. In this work we illustrate, using 2D TCAD (Medici), that independently gated SGrFETs can be used to shift the output transfer characteristics of CMOS circuits and to construct a tunable current mirror with gain factor control.Two different configurations of double-gate SGrFETs are proposed and optimised for improved control over their CMOS switching characteristics. It was shown that the way in which the gates of the SGrFET are connected is essential for optimal operation of the inverter. Complete switching with good noise margins is achieved when the gates are connected across the width of the FET (CAW). FETs with gates connected along the length of the channel (CAL) show poor switching characteristics and poor noise margins for certain input values. The CMOS circuit in CAW configuration shows better switching characteristics as long as the control input voltage is kept smaller than VDD/2. The CAL configuration outperforms the CAW only in off-switch time delay. This improved performance is limited to a certain range of voltages applied to one gate row. To improve the CAW configuration further, the gate geometry can be adapted such that the gate-drain capacitance is reduced. This can be done for instance by increasing the gate cylinder oxide thickness at the drain side using the same fabrication technique as proposed in [1] and increasing the distance between gate cylinders and the drain contact. A tuneable current mirror circuit with CAW connected SGrFETs can be obtained using a single gate metal process. Tuneable current mirrors that use the multi-unit cell SGrFET have two features of merits. The first is that the gain factor can be increased by using SGrFET as a single gate device and increasing the number of the unit cells. The second merit is that the output current can also be tuned by using double gate SGrFET. A multi-cell SGrFET delivers a gain factor larger than one, while low output impedance can be obtained by an increase in gate diameter without increasing the number of devices.[1] R. S. M. Masahara, L. Witters, G. Doornbos, V. H. Nguyen, G. Van den bosch, and K. D. C. Vrancken, F. Neuilly, E. Kunnen, M. Jurczak, S. Biesemans IEEE Electron Device Letters, vol. 28, pp. 217-219, 2007.
5:45 PM - I2.10
A New SiGeC Vertical MOSFET: Single-device CMOS (SD-CMOS).
Carlos Augusto 1 , Lynn Forester 1
1 , Quantum Semiconductor LLC, San Jose, California, United States
Show AbstractA new type of silicon-based Vertical MOSFET concept is presented - Single-Device CMOS (SD-CMOS) - in which the same structure can be operated as NFET or as PFET, depending on the biasing conditions [1]. SD-CMOS offers new possibilities for CMOS integration schemes that are simpler - requiring only 5 masks for the “Front-End” - and less costly to manufacture, than any integration scheme requiring the fabrication of two devices with opposite polarities. In epitaxially grown Vertical MOSFETs, the source, channel and drain can have atomically sharp interfaces, well controlled doping, and channel length controlled by the epitaxial process rather than by lithography and ion-implantation. With epitaxial growth, it is straightforward to do bandgap engineering by incorporating films such as Si1-xGex, and/or Si1-yCy and/or Si1-x-yGexCy, into any of the aforementioned regions. Suitable band offsets at the source/channel interface [2] can suppress DIBL, which is a key limitation to CMOS scaling.These advantages of Vertical MOSFETs are crucial for future CMOS technology nodes, such as 22nm and below.SD-CMOS has a metallic drain region with work-function close to the mid-gap energy of the channel material, which can be a homogenous material, a random alloy, or a superlattice. The source region has a very narrow bandgap, achievable with (Si1-yCy)m-(Si1-xGex)n superlattices, whose mid-gap level is aligned with that of the channel region, and with band offsets with the channel region that are nearly symmetric for the conduction and valence bands. The source contact is a metal with a work-function close to the mid-gap level of the source and channel regions, which in turn are aligned with the work-function of the drain. The potential barrier, for electrons and holes from the source contact to the source region, is required to be just a few KT. For operation as NMOS and PMOS with nearly symmetric threshold voltages, the work-function of the gate electrode is also aligned with the mid-gap energy level of the channel.SD-CMOS is unique due to its band alignments: symmetric band edges, from source to drain, with respect to the mid-gap energy (the “mirror” line). Such configuration can only be obtained in the absence of doping, which if present would immediately break that symmetry. The conduction and valence band edges are required to be asymmetric with respect to a cross-section line crossing the channel through the middle of the gate.The conduction (valence) band offset between source and channel sets the barrier height for electrons (holes) in the OFF condition for NMOS (PMOS), while applying a voltage at the gate leads to the accumulation of electrons (holes) at the source/channel interface, thereby pushing the Fermi-Level in the source above (below) the conduction (valence) band edge of the channel for the ON condition.Band diagrams and a CMOS fabrication flow for SD-CMOS will be presented.[1] US Patent 6,674,099[2] US Patent 5,914,504
Symposium Organizers
Andrew C. Kummel University of California-San Diego
Heiji Watanabe Osaka University
Iain Thayne University of Glasgow
Prashant Majhi SEMATECH/Intel
I3: Ge MOSFET I
Session Chairs
Thursday AM, April 08, 2010
Room 2012 (Moscone West)
9:00 AM - I3.1
Epitaxial Dy2O3 Thin Films Grown on Ge(100) Substrates by Molecular Beam Epitaxy.
Md. Nurul Kabir Bhuiyan 1 , Mariela Menghini 1 , Jin Won Seo 2 , Jean-Pierre Locquet 1
1 Department of Physics and Astronomy, Katholieke University Leuven, Celestijnenlaan 200D, B-3001, Leuven Belgium, 2 Department of Metallurgy and Materials Engineering, Katholieke University Leuven, Kasteelpark Arenberg 44, B-3001, Leuven Belgium
Show AbstractFor the fabrication of a high speed transistor a high mobility (high-μ) Ge(100) substrate is important due to both higher electron and hole mobilities than that of Si. As GeO2 films are thermodynamically unstable at high temperatures, the integration of epitaxial crystalline high dielectric constant (high-κ) thin films on Ge substrates could be possible without any interfacial layers. High-κ Dysprosium oxide (Dy2O3) is a promising candidate among lanthanide metal oxides as an insulator for the fabrication of future generation electronic technologies due to less hygroscopic nature of oxide. The challenge is to grow epitaxial Dy2O3 thin films on high-μ Ge(100) substrates because the lattice mismatch between the bulk Dy2O3 (10.66Å) and the Ge substrate (5.646 Å) is about -5.6 % when the double Ge unit-cell is taken into account.In this contribution, epitaxial Dy2O3 thin films are directly grown on high-μ Ge(100) substrates by MBE for the first time. Structural, chemical, surface morphological and interfacial properties of the Dy2O3 thin films are investigated in detail by in situ RHEED and ex situ XRD, XRR, XPS, AFM and cross-sectional TEM. RHEED and XRD data suggest that single crystalline cubic Dy2O3 films grow epitaxially on Ge(100) substrates with (110) orientation. The epitaxial-relationship is identified to Dy2O3(110)∥Ge(100) and the films are fully relaxed. XRR and AFM images show that the surface of the Dy2O3 films are uniform and smooth with root mean square (rms) roughness of about 4Å. Epitaxial quality and interfacial properties of the films are discussed based on XPS spectra and TEM images.
9:15 AM - I3.2
Unique Axial Ge/Si Heterostructure Nanowire Materials and Devices.
Shadi Dayeh 1 , Jianyu Huang 2 , Aaron Gin 2 , S. Picraux 1
1 Center for Integrated Nanotechnologies, Los Alamos National Laboratory, Los Alamos, New Mexico, United States, 2 Center for Integrated Nanotechnologies, Sandia National Laboratory, Albuquerque, New Mexico, United States
Show AbstractWhile new materials and device concepts are being developed to extend CMOS device scaling beyond the 22 nm node, the potential of combining Si/Ge heterostructure materials with the dimensionality of semiconductor nanowires (NWs) remains to be explored. The vapor-liquid-solid mechanism allows modulation of doping and alloy composition in the axial NW direction which is the direction of transport for surround-gate NW FETs. This provides an additional degree of freedom for band-gap engineering in the transport direction, which when added to Ge compatibility for integration with Si technology, makes Ge-Si axial NW heterostructures advantageous over other existing material and device possibilities, in particular for tunnel FETs. Prior works have provided early demonstration of less than 20 % composition modulation in Ge-Si axial NW heterostructures. In this contribution, we demonstrate 100 % composition modulation of p+-i-n Ge-Si axial NW heterostructures suitable for high performance heterostructure tunnel FETs (H-TFETs), i.e. high on-currents provided by the Ge source and low-off currents provided by the Si drain. We also show the increased solubility of Ge over Si in liquid Au at constant temperature and pressure, leads to a low concentration tail from the interface for Ge into Si prior to achieving 100 % Si composition, the length of which scales with the NW diameter. By controlling the sequence and timing of precursor switching and temperature ramp, Au diffusion at the heterointerface and NW kinking are eliminated, and uniform NW morphology is attained. For NWs with Si segments in excess of ~ 300 nm length atop a p+-Ge segment, a <111>/<211> twin nucleates at the edge of Si for some NWs and leads to ~ 19° kink in the growth direction, with the twin propagating axially up to the Au tip. The morphology of these NWs provides a natural marker to place the surround gate in close proximity to the Si source and at the p+-i junction for enhanced H-TFET performance. H-TFET results for these p+-i-n structures will be presented.
9:30 AM - I3.3
Structure of Hf Based High-k Dielectric Thin Films on Ge Substrates.
Mehmet Sahiner 1 , Michelle Jamer 1 , Jeffrey Serfass 1 , Samuel Emery 1 , Joseph Woicik 2
1 Physics, Seton Hall University, South Orange, New Jersey, United States, 2 , National Institute of Standards and Technology, Gaithersburg, Maryland, United States
Show AbstractThe local structure of the HfO2 and HfxZr1-xO2 (x=0.25-0.90) high-k dielectric thin films on Ge substrates were studied using x-ray absorption fine-structure spectroscopy. Hf based high-k dielectric thin films were prepared by pulsed laser deposition with systematic variation of the deposition conditions such as substrate temperature, partial oxygen pressure, laser fluence. The local structural variations around the Hf atom were investigated by quantitative multiple scattering analysis and modeling of the x-ray absorption spectroscopy data acquired at the National Synchrotron Light Source of Brookhaven National Laboratory. The stabilized structural phases of thin films of HfO2 and HfxZr1-xO2 on Ge substrates and the dependence of these phases to substrate temperature during deposition exhibit distinct contrasts with the structural phases observed when Si is used as the substrate1. HfO2 thin films on Si substrates go through a tetragonal to monoclinic phase transition with increasing deposition substrate temperatures (100-400oC). On the other hand, HfO2 thin films on Ge substrates lock in a non-equilibrium tetragonal phase at substrate temperatures in this range. Quantitative XAFS modeling to the Ge system will be presented and possible explanations for this Si versus Ge substrate effect on the thin film structure will be discussed.1M. Alper Sahiner, J. C. Woicik, P. Gao, P. McKeown, M. C. Croft, M. Gartman, B. Benapfl, Thin Solid Films 515, 6548 (2007).
9:45 AM - I3.4
In-situ MEIS Study of Reduction and Desorption of Native Oxides on Ge During Atomic Layer Deposition.
Hang Dong Lee 1 3 , Tian Feng 1 3 , Lei Yu 1 3 , Daniel Mastrogiovanni 2 3 , Alan Wan 2 3 , Torgny Gustafsson 1 3 , Eric Garfunkel 2 3
1 Physics and Astronomy, Rutgers University, Piscataway, New Jersey, United States, 3 Laboratory for Surface Modification, Rutgers University, Piscataway, New Jersey, United States, 2 Chemistry, Rutgers University, Piscataway, New Jersey, United States
Show AbstractThe integration of high-k dielectrics into devices based on high mobility channel materials (such as Ge, GaAs and InGaAs) has been difficult due to the poor quality of the channel/oxide interface. This is related to the high density of defects present at such interfaces, which leads to Fermi-level pinning. Our integrated tool that combines ALD growth with characterization by medium energy ion scattering spectroscopy (MEIS) allows us to grow dielectric films and to characterize them in situ.Several studies have shown the reduction of native oxides on GaAs and InGaAs during atomic layer deposition (ALD) of dielectrics [1, 2]. Recently, we have shown that the reduction of the majority of native oxides from GaAs substrate follows reactions with a trimethylaluminum (TMA) precursor [3]. We now report results also for Ge substrates. We have determined elemental depth profiles in native oxides and ALD-deposited Al2O3 layers on Ge substrates. Films were also analyzed by x-ray photoelectron spectroscopy (XPS).MEIS and XPS measurements show that after one single TMA pulse (without oxygen exposure) a substantial amount of the native oxides are reduced and there is concomitant growth of a 3Å Al2O3 film. We have also observed the complete removal of the native oxides beyond the MEIS detection limit after > 450 oC preheating of the substrate. There is significant C accumulation during the removal of the native oxides. This is less important on H2O2 treated substrates.[1] P. D. Ye et al., Appl. Phys. Lett. 84, 434 (2004)[2] C. L. Hinkle et al, Appl. Phys. Lett. 92, 071901 (2008)[3] Hang Dong Lee et al., Appl. Phys. Lett. 94, 222108 (2009)
10:00 AM - **I3.5
Strontium Germanide Interlayer for High-k/Ge MISFETs.
Yoshiki Kamata 1 , Akira Takashima 2 , Yuuichi Kamimuta 1 , Tsutomu Tezuka 1
1 , MIRAI-Toshiba, Kawasaki Japan, 2 , Toshiba Corporation, Kawasaki Japan
Show AbstractHigh-k/Ge gate stacks are very promising for future nanoscale LSIs, but surface passivation of the Ge substrate constitutes a major technical issue [1, 2]. In many cases, interfacial Ge oxide exists at the high-k/Ge interface. Although some reports have pointed out that an interface between a thick GeO2 layer and a Ge substrate exhibits superior interface properties [3], complete absence of interfacial Ge oxide layer at the high-k/Ge interface is likely to be necessary for achieving the thin EOT below 0.5nm required in ITRS and for sustaining the thermal stability in high-k/Ge gate stacks [4]. In this talk, a new approach to form EOT-scalable high-k/Ge gate stack with a Sr germanide (SrGeX) interlayer [5] will be discussed. Physical analyses reveal that thermally stable amorphous SrGeX layer existed at LaAlO3/Ge interface without diffusing of Sr and Ge atom into high-k film after annealing at 400oC. A promising EOT scalability is confirmed at around EOT of 1nm. A record high peak hole mobility of 481cm2/Vsec for the high-k/Ge p-MISFETs has been obtained in LaAlO3/SrGeX/Ge p-MISFET. These results suggest the applicability of this new formation technique of the interfacial SrGeX layer to future scaled high-k/Ge MISFETs. This work was supported by NEDO. [1] Y. Kamata, Tutorial Note, Tutorial H, 2008 MRS Spring Meet. [2] Y. Kamata, et al., Materials Today 11 30 (2008) [3] Y. Nakakita, et al., Tech Dig. IEDM 877 (2008) [4] Y. Kamata, et al., MRS Symp. Proc. 1155 C02-04 (2009) [5] Y. Kamata, et al., Tech Dig. Symp. VLSI Tech. 78 (2009)
10:30 AM - I3.6
Evolution of Interface Properties During Atomic Layer Deposition of Rare Earth-based High-k Dielectrics on Si, Ge and III-V Substrates.
Luca Lamagna 1 , Claudia Wiemer 1 , Silvia Baldovino 1 2 , Alessandro Molle 1 , Michele Perego 1 , Sylvie Schamm-Chardon 3 , Pierre-Eugene Coulon 3 , Marco Fanciulli 1 2
1 Laboratorio MDM, CNR-INFM, Agrate Brianza Italy, 2 Dipartimento di Scienza dei Materiali, Università degli Studi di Milano-Bicocca, Milano Italy, 3 CEMES-CNRS and Université de Toulouse, nMat group, Toulose France
Show AbstractIn the effort to integrate new dielectrics on novel channel materials, the investigation of the oxide/semiconductor interface properties is still a matter of debate [1]. Although atomic layer deposition retains an established consideration for its accurate control in film thickness and composition, it is now clear that such a chemical deposition method involves a variety of possible interfacial reactions with the substrate that may be determinant for the electrical performances [2]. Indeed, physical and chemical interfacial details might vary as a result of combining different growth parameters and surface preparations.In this work we report on atomic layer deposition of rare earth-based oxides (i.e. La-doped ZrO2 and Er-doped HfO2) on various semiconductors. The growth of high-k dielectrics was studied on Si and then transferred on Ge and III-V substrates specifically addressing the interface formation and modification during the deposition. In this respect, an in situ monitoring, performed with spectroscopic ellipsometry, provides insights on the very early stages of the deposition [3]. The analysis of the actual formation of the first nanometers of the film reveals different growth behaviors depending on the starting surface, like nucleation delay or substrate oxidation. To elucidate this aspect, the role of the surface preparation is specifically addressed by comparing films grown on H-terminated Si(100), native oxide free Ge(100) and III-V semiconductor compounds (GaAs(100), InxGa1-xAs(100)). Thorough diagnostic of the oxide and interfaces features has been performed on a wide range of oxide stoichiometries (1–50% La or Er) in order to support the in situ study. The growth rates are discussed with regard to the interface evolution, the oxide stoichiometry and also to the final crystallographic structure. X-ray reflectivity and spectroscopic ellipsometry were extensively combined to extract the high-k and interfacial layer thickness supporting atomic structure images, obtained by high-resolution transmission electron microscopy. A distinct amorphous interfacial layer was observed on Si(100) being, on the contrary, ruled out on Ge(100). Si and Ge diffusion throughout the high-k were evidenced by Time of Flight Second Ion Mass Spectroscopy and Electron Energy Loss Spectroscopy. A direct deposition approach or the use of intentional ultra thin interface passivation layers were examined atop III-V materials. Complementary compositional and electrical characterizations of the stacks further support the interfacial details study.[1] M. Houssa, E. Chagarov, A.C. Kummel, MRS bullettin 34, 504-513 (2009)[2] W. Tsai, N. Goel, S. Koveshnikov, P. Majhi, W. Wang, Microelect. Eng. 86, 1540 (2009)[3] E. Langereis, S.B.S. Heil, H.C.M. Knoops, W. Keuning, M.C.M. van de Sanden, and W.M.M. Kessels, J. Phys. D: Appl. Phys. 42, 073001 (2009)
10:45 AM - I3.7
Schottky Barrier Height of Metal Contacts on n-type Germanium With and Without Ge3N4 Interlayers.
Ruben Lieten 1 2 , Valeri Afanas'ev 3 , N. Thoan 3 , Stefan Degroote 1 , Gustaaf Borghs 1
1 , IMEC, Leuven Belgium, 2 , Lawrence Berkeley National Laboratory, Berkeley, California, United States, 3 Department of Physics, University of Leuven, Leuven Belgium
Show AbstractLow source and drain resistances are of crucial importance to obtain high channel current in SiGe based high-frequency devices. However, for n-channel SiGe MOSFETs it is getting increasingly difficult to obtain Ohmic regime with increasing Ge concentration. In the limiting case of pure n-type Ge, the contact characteristics are quasi independent of the metal work function and show rectifying behavior. It is suggested that intrinsic Ge interface states cause Fermi level pinning thus making the metal/Ge barrier height insensitive to the metal work function. In the present work, by using metal/n-Ge contacts as prototype system, we will show that introduction of a Ge3N4 interlayer unpins the Ge Fermi level yielding the desirable Ohmic contacts. It has been shown previously for metal/Si contacts that imposing an ultrathin insulator between low-work function metals and silicon, can substantially reduce the Schottky barrier of the junction and decrease the junction resistance. With this approach a Schottky barrier height for Mg on n-type Si was demonstrated of 0.2 V, a reduction of the effective barrier height by approximately 0.25 V. Recently we have shown that a similar approach can be used for n-type Ge. A few monolayers of crystalline Ge3N4 effectively reduce the barrier height of Al contacts on n-type Ge from 0.6 to below 0.3 eV.In the present work we accurately measure the Schottky barrier height of bare metal contacts on n-type Ge(001) and Ge(111) by low temperature (77 K) capacitance-voltage (C-V) measurements. Subsequently we compare the influence of a few monolayers of crystalline and amorphous Ge3N4 on the Schottky barrier height of metal contacts on n-type Ge. Where bare metal contacts on n-type Ge show severe Fermi level pinning, both amorphous and epitaxial Ge3N4 are found to effectively unpin the Fermi level. Al contacts on amorphous and epitaxial Ge3N4 show barrier heights of respectively ≤ 0.03 ± 0.05 eV and 0.08 ± 0.1 eV. These barrier heights are the lowest reported for metal contacts on n-type Ge. We also show that the Fermi level is unpinned and a linear dependency exists between barrier height and metal work function. Ge3N4 interlayers therefore allow changing the barrier height by the work function of the metal. Where the formation of epitaxial Ge3N4 requires temperatures above 600 °C, amorphous layers of Ge3N4 can be formed at much lower temperatures. As no post-deposition annealing is necessary, amorphous Ge3N4 can be used to form Ohmic contacts on n-type Ge at low temperatures and can easily be transferred to the SiGe alloys of different composition.
11:15 AM - I3.8
Oxidation Mechanism at Ge/GeO2 interfaces: An ab initio Study.
Shoichiro Saito 1 , Takuji Hosoi 1 , Heiji Watanabe 1 , Tomoya Ono 1
1 Graduate School of Engineering, Osaka University, Suita, Osaka, Japan
Show AbstractAs the down-scaling of Si metal-oxide-semiconductor (MOS) devices is approaching its technological and fundamental limits, numerous attempts have been made to explore or design alternative channel materials. Ge has attracted more attention recently for future advanced MOS devices, especially for high-speed circuit due to the intrinsic carrier mobility. To realize such high-performance Ge MOS devices, one of the most critical issues is to fabricate atomically well-controlled Ge/GeO2 interfaces since Ge/GeO2 interfaces exist even in Ge/high-k interfaces. Very recently, it is experimentally found that Ge/GeO2 interfaces exhibits a lower defect density than Si/SiO2 interface [1]. In addition, the current author’s group also achieved high-quality Ge/GeO2 interfaces by conventional thermal treatment of Ge substrates [2]. In the case of the oxidation process of Si, it has been reported that Si-atom emission occurs at the Si/SiO2 interface to release the stress even though the dangling bonds remain and the emitted Si atom would be the other interface defects, such as interstitial atoms [3]. However, the formation mechanism of defects at the Ge/GeO2 interface during its oxidation process has not revealed yet. In this study, the first-principles calculation for the defect formation at the Ge/GeO2 interface during the oxidation process was implemented. We compared the formation energies of the dangling bond defects at the Ge/GeO2 and Si/SiO2 interfaces in terms of the total energy calculation. Our result indicates that the dangling bond defects at Ge/GeO2 interfaces are rarely generated during the oxidation process. We analyzed the flexibility of the O-Ge-O bonding angles in the bulk GeO2 and revealed that the O-Ge-O bonding angles are more flexible than the O-Si-O ones since the O-Ge-O bonding angles are distorted from the ideal tetrahedral structure more significantly than the O-Si-O ones. Therefore, the higher flexibility of the O-Ge-O bonding networks reduces the stress due to the lattice mismatch between Ge and GeO2, leading to the larger formation energy of the dangling bond defects at the Ge/GeO2 interface [4]. Our first-principles study supports the experimental result that a lower interface trap density will be realizable in the Ge/GeO2 interface and implies that Ge is the strong candidate for the channel material in next generation devices due to the low defect density at its interface as well as the high carrier mobility. [1] H. Matsubara, et al. Appl. Phys. Lett. 93, 032104 (2008). [2] T. Hosoi, et al. Appl. Phys. Lett. 94, 202112 (2009). [3] H. Kageshima and K. Shiraishi, Phys. Rev. Lett. 81, 5936 (1998). [4] S. Saito, et al. Appl. Phys. Lett. 95, 011908 (2009).
11:30 AM - **I3.9
Quality of GexSi1-x/Oxide Interfaces in Terms of Intrinsic Defects: ESR Probing and Electrical Activity.
Andre Stesmans 1 , Valery Afanas'ev 1
1 , University of Leuven, Leuven Belgium
Show AbstractAmong the numerous routes explored1 to meet the relentless strive to scaling down devices within the Si-based metal-oxide-semiconductor (MOS) technology, enhancement of charge carrier mobility µ takes a fundamental position. Although its enhancement has been pursued fundamentally (i.e., through application of physical stress), Si faces ultimate limits, from where the attention to the introduction of intrinsically higher µ semiconductors, such as Ge or III-V materials. With respect to Ge, interesting here is the notable experience acquired in depositing insulators of high dielectric constant for application to Si in replacement of the conventional SiO2 gate insulator. This offers in parallel the potential to surmount a key problem with Ge, i.e., providing an alternative for the less stable GeO2(x) native insulator, thus attaining two goals at once if realized by a high dielectric constant insulator.A crucial element in successful MOS application is the ultimate quality of the semiconductor/insulator interface, where detrimental interface traps should be reduced to the (sub) 1010 cm-2 level, still a key issue for Ge MOSFETs. For Ge, achieving low interface trap density appears not straightforward: Intense research has exposed basic differences between the seemingly isomorphic interfaces Si and Ge would form with oxides. This also includes the fact that that conventional electron spin resonance (ESR) has failed to resolve interfacial Ge dangling bond (DB) type defects in Ge/oxide heterostructures, this in contrast with the well known Si/SiO2 case where, as exposed by ESR, interfacial Si DBs constitute a major bath of detrimental defects. The presentation will deal with a comparative analysis of the properties and nature of the interfaces of Ge-based heterostructures, in particular, GexSi1-x/SiO2, Ge/GeOx, and Ge/Si/SiO2, as probed by occurring paramagnetic point defects using multi-frequency ESR spectroscopy. We will report on the observation in (100)Si1-xGex/SiO2 entities of an unknown non-trigonal Ge paramagnetic interface defect, denoted GPb1, of unique properties such as less common C2v symmetry. Aspects of thermal passivation by hydrogen are addressed. The properties of the center are discussed within the context of the thus far elusive role of interfacial Ge DB defects in Ge/insulator heterostructures, encompassing theoretical inferences and putative electrical impact. A basic step will imply detailed comparison of electrical results on interface traps in the GexSi1-x/SiO2 using a pseudo MOSFET approach with ESR data. While revealing the electron trap nature of the GPb1 centers, monitoring of the trap behavior enabled to determine the trap level in the bandgap. The results of theoretical modeling, using a first-principles approach, of the advanced defect model will be addresses as well. 1 See, e.g., J. Robertson, Eur. Phys. J. Appl. Phys. 28, 265 (2004).
12:00 PM - I3.10
Chemical Stability of Lanthanum Germanate Passivating Layer on Ge Upon Metal or High-k Deposition.
Dimitra Tsoutsou 1 , Yerassimos Panayiotatos 1 , Andreas Sotiropoulos 1 , Georgia Mavrou 1 , Sotiria Galata 1 , Evangelos Golias 1 , Athanasios Dimoulas 1
1 MBE Laboratory, NCSR DEMOKRITOS, Athens Greece
Show AbstractThe development of a suitable Ge surface passivation methodology prior to high-k dielectric deposition still remains a key challenge for the development of p and n-channel MOSFETS. Although GeO2 is a natural choice, this oxide is unstable reacting with Ge substrate to give volatile GeO which sublimes leaving behind a defective interface [1]. To this direction, we have recently investigated [2], the passivating properties of a lanthanum germanate (LaGeOx) layer, which was produced by the oxidation of a La-covered Ge surface. La changes the surface chemistry so that a stable LaGeOx compound is favored against the competing reaction of GeO2 with Ge resulting in suppression of GeO and nearly ideal electrical characteristics [3, 4].However, the moderate k value of LaGeOx (~12) [5] and the rather poor insulating properties imply that the compound can only be used as a thin (~1nm) passivating layer, rather than the oxide dielectric in scaled metal-oxide semiconductor-devices. The deposition of a high-k dielectric (such as ZrO2 or HfO2) is therefore necessary in order to realize high-k gate stacks on Ge. To this end, the chemical stability of LaGeOx upon metal or high-k deposition was examined by in-situ X-ray photoelectron spectroscopy (XPS). Thin films (2 nm) of Zr/Hf metals and their corresponding oxides were grown at two different temperatures (Tg=RT and 250 °C) by molecular beam epitaxy (MBE) on LaGeOx/Ge. Upon Zr/Hf metal deposition, Zr 3d and Hf 4f core level analysis reveals the formation of a mixture of ZrO2(HfO2) and sub-stoichiometric ZrOx(HfOx). These results combined with Ge 3p analysis indicate the reduction of the LaGeOx compound, which is found to be more pronounced at Tg=RT, or when Hf is used instead of Zr. After deliberate metal oxidation with molecular oxygen (O2), La 3d and Ge3p spectral features point out to the re-formation of lanthanum germanate species, which however may not be of the same quality as the originally formed LaGeOx. Further investigations are needed in order to conclude whether this possible LaGeOx instability as well as the sub-stoichiometric ZrOx(HfOx) oxides, could explain the degradation [3] of electrical response in MOSCAPs with LaGeOx/HfO2(ZrO2) bilayer gate stacks.[1] A. Toriumi et al., Microel. Engin. 86, 1571 (2009)[2] A. Dimoulas et al., submitted in APL.[3] G. Mavrou et al., JAP 103, 014506 (2008); APL 93, 212904 (2008)[4] C. Rossel et al., Proceedings ESSDERC 2008 p. 79 [5] C. Andersson et al., Microel. Engin. 86, 1635 (2009)
12:15 PM - I3.11
The Ge(100)/ALD-Al2O3 Interface: Physical and Electrical Characterization.
Shankar Swaminathan 1 , Yun Sun 2 , Piero Pianetta 2 , Paul McIntyre 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 , Stanford Synchrotron Radiation Laboratory, Menlo Park, California, United States
Show AbstractOptimizing the Germanium/high-K interface for highly scaled CMOS device applications remains a significant challenge. The Ge(001)/Al2O3 interface is important in the context of providing a low interface state density, large band offsets to reduce gate leakage and thermal robustness for device processing (unlike Ge/GeO2). In particular, ALD-Al2O3 is promising as a deposited interlayer between the Ge channel and “higher”-K oxides (e.g. TiO2) that would, by themselves, have low band offsets to Ge. We will present results on the physical and electrical characterization at various stages of processing the Ge/ALD-Al2O3 interface. First, we will present a study on the surface functionalization of the Ge(100) surface prior to ALD by a hydroxyl dosing (H2O “pre-pulsing”), and the corresponding effects on capacitance-voltage behavior: reduced stretch-out, charge trapping and frequency dispersion. Second, we will summarize in situ XPS and TEM results during the subsequent ALD that reveals important findings: -OH incorporates in the Al2O3 layer, reducing its apparent dielectric constant (~7), an incubation regime precedes the formation of the coalesced dielectric layer during ALD, and precursor exposure “cleans up” the pre-pulsing-induced GeOx surface oxide which is beneficial for capacitance scaling. Third, we will present synchrotron photoelectron spectra (PES) that suggest a mechanism for the observed forming gas anneal-induced passivation of Ge/Al2O3 interfaces, similar to recent findings in Ge/GeON/ALD-HfO2 stacks[1]. These devices exhibited an excellent Dit ~ 2x1011 cm-2 eV-1, comparable to Ge/GeO2[2] and Ge/GeON [3] interface passivation schemes. Fourth, we will present results on the application of ultrathin (~ 6 – 15A) ALD-Al2O3 interlayers in Ge/TiO2 gate stacks exhibiting a low CET ~ 1.2nm, Dit ~ 4 x1011 cm-2 eV-1, hystersis < 10mV, K(TiO2) ~ 32 and low gate-leakage. Extensive temperature dependent C-V analysis to examine the nature of the apparent inversion response in the bilayer devices will be presented. Finally, we will also present synchrotron PES results on the effects of hydrogen annealing on the bilayer stacks to investigate the mechanism of the observed electrical passivation after annealing (~ 2 order reduction in Dit near midgap).[1]Y. Oshima, Y. Sun, D. Kuzum, T. Sugawara, K. C. Saraswat, P. Pianetta, and P. C. McIntyre, Journal of The Electrochemical Society 155, G304-G309 (2008).[2]D. Kuzum, T. Krishnamohan, A.J. Pethe, A.K. Okyay, Y. Oshima, S. Yun, J.P. McVittie, P.A. Pianetta, P.C. McIntyre, and K.C. Saraswat, Electron Device Letters, IEEE 29, 328-330 (2008).[3]K.K. Y. Fukuda, H. Toyota, T. Ono, Y. Nagasato, and T. Ueno, Jpn. J. Appl. Phys. 45, 7351 (2006).
12:30 PM - **I3.12
Bonding and Interface Defects at III-V Oxide Interfaces.
John Robertson 1 , Liang Lin 1
1 , Cambridge University, Cambridge United Kingdom
Show AbstractThe difficulty of passivating III-V semiconductor surfaces is well known. Work has shown that Ga,Gd oxide is a successful passivant [1], but it is desired to use oxides deposited by ALD for commercial FETs. In-situ XPS studies have been useful in understanding the growth chemistry [2]. Differences in mutual conductances for GaAs and InGaAs devices have been attributed to changes in band structure [3]. We describe how important it is to identify the causes Fermi level pinning at III-V interfaces. It is argued that these all result from interface defects, or to defects induced in the semiconductor by the oxide deposition process [4]. They are therefore extrinsic. This therefore requires first a good model of the ideal, defect-free interface. Electron counting rules are employed to describe interfaces between oxides and III-V semiconductors. The (100)GaAs face is polar. It is pointed out that such (100) interfaces cannot in general be atomically abrupt, as Harrison [5] noted before for (100) Ge-GaAs interfaces.1. R J Hill et al, IEEE EDL 28 1080 (2007)2. C L Hinkle,.. R M Wallace, Microelect Eng 86 1544 (2009) 3. P Ye, J Vac Sci Tech A 26 697 (2008)4. J Robertson, App Phys Lett 94 152104 (2009); J Robertson, L Lin, IEDM (2009)5. W A Harrison, Phys Rev B 18 4402 (1978)
I4: Ge MOSFET II
Session Chairs
Thursday PM, April 08, 2010
Room 2012 (Moscone West)
2:30 PM - I4.1
Investigation of the Physical Origin of the Improved Electrical Properties of GeO2 Dielectric by Vacuum Annealing.
Shingo Ogawa 1 , Takashi Yamamoto 1 2 , Gaku Okamoto 2 , Katsuhiro Kutsuki 2 , Takuji Hosoi 2 , Takayoshi Shimura 2 , Heiji Watanabe 2
1 Surface Analysis Laboratories, Toray Research Center, Inc., Otsu, Shiga, Japan, 2 Graduate School of Engineering, Osaka University, Suita, Osaka, Japan
Show AbstractGermanium (Ge) is one of the most likely next generation channel materials that would replace silicon (Si), because the mobility of electrons and holes in Ge is higher than in Si. Germanium oxide (GeO2) is a gate dielectric and/or buffer layer on the Ge channel. However, one of the problems with the fabrication process of integrating GeO2 into Ge-MOSFETs is the easy degradation of GeO2 in the ambient air, such as the flatband voltage (VFB) shift, anomalous minority career generation and capacitance voltage (C-V) hysteresis. Recently, one of the authors (T. H.) reported that the electrical property of Ge-MOS capacitors can be improved by in-situ vacuum annealing at 300°C prior to electrode deposition.1 In this study, we investigated the physical origin of the improved electrical properties of the GeO2 dielectric by SIMS, XPS and FT-IR analyses. GeO2 dielectrics were formed by dry oxidation at 550°C for 2 hours using a conventional furnace. Vacuum annealing of the GeO2/Ge samples was carried out under a high vacuum condition at 300°C. Static and dynamic SIMS analyses indicated that while amine and organic impurities are adsorbed on the GeO2 surface just as on the SiO2 surface,2 the impurity concentration within the GeO2 layer was much higher probably due to their higher diffusivity. In addition, a large amount of hydrogen was detected throughout the GeO2 layer. An FT-TR analysis revealed the existence of germanium hydoxide (Ge-OH) bonds in the oxides. We found that vacuum annealing at 300°C is very effective for removing these impurities in the GeO2 layer. Moreover, the Ge-O peak in the FT-IR spectra shifted toward a higher wavenumber after the vacuum annealing, indicating an increase in the film density by the vacuum annealing. These results imply that the thermal desorption of impurities (C, N, H and water) and densification of the GeO2 layers are plausible origins of the improved electrical properties of Ge-MOS devices. [1] T. Hosoi et al., Appl. Phys. Lett. 94, 202112 (2009). [2] A. Karen et al., proceeding of SIMS XI. 229 (1997).
2:45 PM - I4.2
Study of Passivation of Ge(100) Surface Using Scanning Tunneling Microscopy and Density Functional Theory.
Joon Sung Lee 1 2 , Sarah Bishop 1 , Andrew Kummel 1
1 Chemistry and Biochemistry, University of California, San Diego, La Jolla, California, United States, 2 Materials Science and Engineering, University of California, San Diego, La Jolla, California, United States
Show AbstractPassivation of a Ge surface has been a challenging process in fabrication of Ge-based MOSFET device because of the high interface defect density between Ge and Ge native oxide. Recent reports suggest two different passivation methods for Ge surfaces; (i) introducing N to form Ge nitride which suppresses Ge suboxide (GeOx) outdiffusion from the oxide/Ge interface into the high-k dielectric layer at high temperatures, and (ii) fabricating a stoichiometric GeO2 layer on the Ge surface before a high-k dielectric deposition which minimizes the dangling bonds on the Ge surface atoms. In this study, the atomic structures of Ge-N and Ge-O surface species and their effects on electronic structures were investigated using scanning tunneling microscopy (STM) and density functional theory (DFT). A Ge(100) surface was directly nitrided in a UHV chamber using the electron cyclotron resonance (ECR) plasma source with pure N2 gas. Plasma nitridation at 500°C produced an ordered structure of Ge-N adsorbates on the Ge surface free from O contaminants or Ge ad-species. DFT calculations were performed on a proposed model of the Ge subnitride ordered structure which has sp2 hybridized N atoms under the surface Ge dimers. DFT calculations of the adsorption energy are consistent with the spontaneous formation of this structure in an atomic N ambient, and the dimensions of the structure are consistent with the values obtained from STM images. The DFT calculation of the density of states shows gap states produced from the subnitride structure due to the increase of dangling bonds and the strain caused by the subsurface N atoms. This is consistent with the scanning tunneling spectroscopy (STS) data which show a Fermi level pinning near the valence band on the n-type Ge surface. Next, the oxidation of Ge(100) with H2O, O2, and GeO2 (e-beam) dosing were compared. Dark –OH adsorption sites were found on the H2O as-dosed Ge surface. Comparing to the O2 dosing of a Ge surface, which produces the equal number of O displacements and Ge ad-atoms, H2O dosing generates much less Ge ad-species. However, annealing the H2O dosed surface to 300°C transforms the dark –OH sites into the bright Ge oxide sites (GeOx) thereby removing the differences between H2O and O2 dosing. The e-beam deposition of GeO2 produces Ge ad-species and probable GeO2 adsorbate sites with very few dark O displacement sites. Annealing at 325°C forms dark Ge suboxide rows similar to the structures observed on the O2-dosed surface annealed at the same temperature. At 500°C, however, GeO2 adsorbate sites still remain while the suboxide rows disappear. DFT calculations are being performed to determine the atomic and electronic structures of –OH and GeO2 adsorbates. To accomplish the Fermi level unpinning of the Ge(100) surface, ALD of Ge nitrides and Ge oxides are being studied to form a passivation layer which does not induce Ge displacement, residual defects, or Ge suboxides.
3:00 PM - I4.3
Ultimate Ge Passivation: Process and Materials Characterization of Ultrathin Si Cap Layers Grown on Ge Substrates.
Benjamin Vincent 1 , Matty Caymax 1 , Wilfried Vandervorst 1 2 , Ventsislav Valev 3 , Thierry Verbiest 3 , Roger Loo 1
1 , IMEC, Leuven Belgium, 2 Instituut voor Kern- en Stralingsfysica, K. U. Leuven, Leuven Belgium, 3 Institute for Nanoscale Physics and Chemistry (INPAC), K. U. Leuven, Leuven Belgium
Show AbstractGe passivation is considered as one of the main challenges for integration of high mobility Ge channels in advanced MOSFETs technology. Ultra-thin (few monolayers) epitaxial Silicon grown on top of Ge channel surface has already been demonstrated as an efficient technique to improve gate stack/Ge channel interface quality. The exact quantity of Si monolayers grown, the absence of Ge within the top Si layer, and the epitaxial quality of the Si material have been highlighted as key factors for Ge MOSFETs performances. This paper focuses first on Si monolayers measurement grown on Ge. It offers next an in-depth characterization of Si cap materials quality grown on Ge with various process conditions. In order to define the most accurate technique to measure the ultra thin (1 – 10 ML) Si cap thickness on Ge, a cross calibration of numerous techniques (RBS, XPS, TXRF, SIMS, Ellipsometry, Reflectometry) is presented. RBS being considered as the calibration reference, we have determined a 1ML accuracy for Si cap thickness measurement using Spectroscopic Ellipsometry. We have next considered various Si on Ge epitaxial growth processes using Chemical Vapor Deposition and comparing different Si precursors (Silane and Trisilane), growth temperatures (350°C-500°C), and carrier gases (H2, N2). Strain relaxation has been first investigated by TEM and SHG (Second Harmonic Generation) analysis: critical thickness of plastic relaxation for Si cap on Ge has been estimated at 12 monolayers. Secondly, Ge presence in Si caps has been characterized using EXLE (EXtremely Low Energy) SIMS (150eV). The Ge content in the Si cap (for Si thicknesses in between 6-10MLs) is a factor of 10 lower if Trisilane instead of Silane is used as Si precursor. Moreover, SIMS analysis show that Ge presence in the Si cap is neither dependent on the growth temperature (350°C-500°C) or on the carrier gas (H2, N2) used for different Trisilane processes. A Ge segregation mechanism rather than an up-diffusion mechanism is then highlighted and explained. This Ge segregation is only driven by the growth mechanism which is different for the different Si precursor used. We finally focused our characterizations on point defects formation occurring during low temperatures Si cap growth processes. Thick (20nm) Si cap grown on Si0.85Ge0.15 layers with different low temperature Trisilane processes have been characterized to quantify the impact of growth rates and growth temperatures on point defects formation. SIMS and Life Time measurements on those layers have determined the best process windows for Si growth using Trisilane. This process window has also been investigated for ultra-thin Si caps on Ge using SHG analysis. In conclusion, we present a full understanding of all the critical mechanisms involved during low temperature ultrathin Si cap growth on Ge: strain relaxation, Ge segregation, point defects formation. An ultimate Ge passivation process is finally proposed.
3:15 PM - I4.4
Quantitative Observation of Ge-segregation During the Si-passivation of Ge-surfaces.
Wilfried Vandervorst 1 2 , Benjamin Vincent 1 , Matty Caymax 1 , Bastien Douhard 1 , Sebastian Koelling 1 2 , Matthieu Gilbert 1
1 spdt/mca, imec, leuven Belgium, 2 IKS, KULeuven, leuven Belgium
Show AbstractAlthough Ge is proposed as a replacement for Si, its has one significant drawback i.e. the absence of the reliable formation of a high quality Ge-oxide layer which manifests itself in poor interface characteristics and a high interface state density. Ab-initio calculations indicate that the formation of Ge-Hf bonds are responsible for energy levels in the band gap. One solution is to grow an epitaxially fully strained Si film on top of the Ge. Electrical results have indeed indicated a reduced interface trap density Nit between Ge(1 0 0) and HfO2 [1]. However the remaining value still exceeds the one from a high quality SiO2/Si interface probably linked to the Ge present at the top surface of the Si-film which might result from a surface segregation effect during growth of the Si film [2]. The quantitative analysis of the Ge-profile within the Si layer and the surface segregation requires a metrology wich has near-atomic depth resolution, high sensitivity and a high degree of quantification.Although SIMS appears the most appropriate method, near-surface transients and ion beam mixing limit the accuracy when it is used in its normal mode (energies 350- 500 eV). Depending on the energies and impact angle used, the apparent Ge-segregation peak (dis)appears and the differences in profile shape (i.e apparent indiffusion) between various Si-deposition approaches (growth temperature, gas,..) are becoming marginal.The approach used in this work, termed EXLE-SIMS relies on performing the ion beam sputtering at energies (100-150 eV) approaching the threshold for sputtering (~ 50 eV). The strongly reduced collision cascade then minimizes the broadening of the profiles and, as will be shown, distinct characteristics (surface segregation, apparent Ge-indiffusion) depending on the growth process can now be observed. The results can be interpreted in terms of the interactions (Si-Ge exchange and Ge-segregation) taking place during the growth process. As a complement to these SIMS profiles we will also present a detailed 3D-distribution of the Ge-atoms in the Si –layer based on the Atomprobe. The latter has near-atomic resolution and its quantification is matrix-free thus providing the ideal cross calibration of the SIMS results. 1 F. E. Leys, R. Bonzom, B. Kaczer, T. Janssens, W. Vandervorst, B. De Jaeger, J. Van Steenbergen, K. Martens, D. Hellin, J. Rip, G. Dilliway, A. Delabie, P. Zimmerman, M. Houssa, A. Theuwis, R. Loo, M. Meuris, M. Caymax, and M. M. Heyns, Mater. Sci. Semicond. Process. 9, 679 (2006)2 M. Caymax, F. Leys,J. Mitard, K. Martens, L. Yang, G. Pourtois, W. Vandervorst, M. Meuris, and R. Loo Journal of The Electrochemical Society, 156 _12_ H979-H985 _2009_
3:30 PM - **I4.5
Substrates and Gate Dielectrics: the Materials Issue for sub-22 nm CMOS Scaling.
Matty Caymax 1 , Florence Bellenger 1 2 , Guy Brammertz 1 , Johan Dekoster 1 , Annelies Delabie 1 , Roger Loo 1 , Clement Merckling 1 , N. Nguyen 1 , Laura Nyns 1 , Sonja Sioncke 1 , Benjamin Vincent 1 , Gang Wang 1 4 , Wilfried Vandervorst 1 3 , Marc Heyns 1 4
1 WEA, IMEC vzw, Leuven Belgium, 2 Department of Electrical Engineering, K.U.Leuven, Leuven Belgium, 4 Department of Metallurgy and Materials Engineering, K.U.Leuven, Leuven Belgium, 3 Instituut voor Kern-en Stralingsfysica, K.U.Leuven, Leuven Belgium
Show AbstractPerformance scaling of CMOS technologies beyond the 22 nm node will depend on the successful introduction of high mobility materials such as germanium and compound semiconductors on silicon substrates, which is not straightforward due to important materials incompatibilities. These semiconductors moreover necessitate new gate dielectric materials as the well-proven recipes of “hafnium-based oxides” are not working for various reasons. The lack of a stable, high-quality native oxide for both semiconductors forces materials scientists and device engineers to focus more on the interface rather than on the dielectric material it self.A first part of this paper discusses problems related to the hetero-epitaxial growth of Ge and of III/V materials on Si. By applying a low-high temperature regime, smooth layers of Ge on Si can be obtained. Because of the lattice mismatch, these layers will relax by the formation of misfit dislocations at the interface, combined with threading arms that extend to the surface. The thickness of the layer determines the final density of threading defects, even in case of confined selective growth in windows in a dielectric hard mask, unless specific measures are taken. The polar nature of III/V’s brings about additional problems of anti-phase domain nucleation. This can be solved by providing extra steps on the starting surface in combination with a “pre-deposition” of arsenic. The combination of Ge and III/V selective epitaxy on patterned wafers allows growing confined layers with a low defect density and of high quality. Moreover, by using standard shallow trench isolation as mask, a very natural integration of these materials in standard Si manufacturing can be realized.The second part of this paper deals with the growth of dielectric materials and control of the resulting interfaces. In contrast to the case of Si, both Ge and III/V surfaces are heavily prone to problems with pinning of the surface Fermi level (FLP), which prohibits an efficient control of the channel by varying gate voltages. In the case of Ge, the problem can be solved by decoupling the gate dielectric from the Ge surface by means of an ultra-thin, strained Si epi-layer, after which the well-known gate stack approaches with ALD-grown metal oxides from the Si world can be used. An alternative, promising solution is passivation with thermally grown GeO2 followed by ALD high-k, although this process requires much more care than its Si counterpart. Gate dielectrics on III/V, finally, are probably an even bigger challenge. Apart from the Ga2O+GaGdOx passivation on GaAs, no real solutions of the FLP problem are known. We will discuss the use of sulfur (from thermal treatments with H2S or in the liquid phase with (NH4)2S) in combination with ALD or MBD-grown high-k layers on both GaAs and InGaAs. This will be compared to alternative approaches based on an epitaxially grown interfacial passivation layer of Ge in combination with MBD-grown Al2O3.
4:00 PM - I4.6
Investigation of the Thermal Stability of Strained Ge Layers Grown at Low Temperature by Reduced-pressure Chemical Vapour Deposition on Si0.2Ge0.8 Relaxed Buffers.
Andy Dobbie 1 , Maksym Myronov 1 , Xue-Chao Liu 1 , Van Nguyen 1 , Evan Parker 1 , David Leadley 1
1 Department of Physics, University of Warwick, Coventry United Kingdom
Show AbstractHigh quality strained Ge (s-Ge) epitaxial layers are a promising candidate to achieve high mobility channel MOSFETs suitable for the 22 nm technology node and beyond, due to the intrinsically higher mobility of Ge compared to Si, and the additional performance enhancements from strain [1]. In order to achieve an s-Ge channel more than a few monolayers thick it is necessary to engineer a relaxed Si1-xGex buffer with a high Ge content (x > 0.5). We have recently reported high quality s-Ge layers grown by RP-CVD at low temperature (T ≤ 450 °C), on a fully relaxed Si0.2Ge0.8 buffer [2]. By using a reverse-grading approach, we achieved a high Ge composition in the buffer, with a smooth surface (rms surface roughness of ~2 nm), low threading dislocations density (~ 4 x 106 cm-2) and much thinner (~ 2.1 μm) than can be achieved with conventional linear grading [3].In this work, the thermal stability of s-Ge epilayers (up to 80 nm thick) grown on relaxed Si0.2Ge0.8 buffers has been investigated by in-situ annealing in H2 ambient at temperatures up to 650 °C. These temperatures are similar to those currently used during fabrication of advanced CMOS devices. All s-Ge layers were grown at 400 °C using GeH4 gaseous precursor. The relaxation of the annealed layers has been studied using high-resolution XRD reciprocal space maps (RSMs), and was found to depend strongly on both annealing temperature and thickness of the Ge epilayer. Strained Ge layers up to 50 nm thick remained fully strained after annealing at 450 °C, whereas after annealing at 550 °C s-Ge layers thicker than 20 nm were on the onset of relaxation; after annealing at 650 °C all s-Ge layers showed significant relaxation with defects clearly visible at the Si0.2Ge0.8/Ge interface. All annealed s-Ge layers exhibited higher surface roughness than s-Ge control samples without annealing (rms ~ 2 nm). Annealing at 450 °C resulted in only a slight increase in surface roughness (rms ~ 3 nm), almost independent of s-Ge thickness. However, annealing at 550 °C and 650 °C resulted in significant surface roughening (with maximum rms values of 5 nm and 35 nm, respectively) due to the formation of Ge islands, which were observed by AFM. At these higher temperatures, the surface roughness of the s-Ge layers was found to be thickness dependent, with a Ge smoothing effect observed for layers greater than 50 nm.These results are particularly important for the fabrication of s-Ge MOSFETs, for which the surface passivation prior to gate stack formation is critical to the performance of the device. Based on the results presented here, the thermal budget should be kept below 550 °C to avoid relaxation and roughening of the s-Ge epilayer, which could degrade the device performance.[1] M. Myronov et al APL 91, 082108 (2007)[2] M. Myronov et al E-MRS (2009)[3] V.A. Shah et al APL 93, 192103 (2008)
4:30 PM - I4.7
High Electron Mobility in Ge nMISFETs With High Quality S/D Formed by Solid Source Diffusions.
Tatsuro Maeda 1 , Yukinori Morita 1 , Shinichi Takagi 2
1 NIRC, AIST, Tsukuba, Ibaraki, Japan, 2 , The University of Tokyo, Bunkyo-ku, Tokyo, Japan
Show AbstractCompared with Ge p-channel MISFETs, poor electrical characteristics have been reported on Ge n-channel MISFETs and there is not yet a clear understanding of the causes behind the degraded electron mobility. One of the crucial problems can be the absence of high quality S/D in Ge nMISFET characteristics. Interestingly, all the electron mobility data reported previously were extracted from nMISFETs with significantly high S/D series resistance (RSD) and poor n+/p diode characteristics. Actually, it is very hard to obtain high quality S/D in the gate-first process since the activation temperatures for S/D formations in Ge should usually be very low in order to avoid the degradation of Ge gate stacks as well as device isolations. Consequently, the high quality S/D and the gate stack are not compatible in the gate-first process. In this paper, we employ the gate-last process for Ge nMISFET fabrications to realize both high quality S/D and gate stack and to investigate the Ge electron mobility in the Ge inversion layer. In order to fabricate n+ S/D regions, Sb diffusion from an Sb-doped solid source was performed instead of the conventional ion implantation technique. The sheet resistance and the electron Hall mobility of 11.6 Ω/sq and 607cm2/Vs, respectively. The excellent diode characteristics exhibiting ~1.5 x 105 on/off ratio and low reverse current density of ~4.5 x 10-4A/cm2 at 1V are also achieved. After the high quality S/D formation, HfO2 films were deposited as a gate insulator, followed by metal gate electrodes formation by a lift-off process. Thanks to the high quality S/D, we have successfully realized the decent Ge n-channel MISFET operation. The ratio of IDon/IDoff is still as low as 2.7×102 at VD = 0.01V and SS is 289mV/dec. Here, we have found that IDoff is dominated by ISUB that corresponds to the reverse junction leakage in the drain area. Therefore, measured IS can be regarded as the actual channel current. The ratio of ISon/ISoff amounts to 6.3×103 and 2.6×105 at VD = 0.01 and 1 V, respectively. The SS value of IS is 108mV/dec without any drain induced barrier lowering. The value of RSD is evaluated to be 400Ω (Lmask=100μm). Considering of the influence of RSD, the actual Ge electron mobility in the channel is evaluated precisely. We obtain higher Ge electron mobility than the Si universal electron mobility at low Eeff and achieve the highest electron mobility with the peak value of 891cm2/Vs. To our knowledge, this is one of the highest mobility reported on unstrained surface channel Ge devices. Our results indicate that high quality S/D is important to accomplish the high performance Ge n-channel MISFET operation.
4:45 PM - I4.8
B Doping in Ge: The Role of Self-interstitial Defects.
Nick Cowern 1 , Chihak Ahn 1 , Nicholas Bennett 1 , Silke Hamm 2 , Pascal Scheiblin 3
1 Electrical, Electronic and Computer Engineering, Newcastle University, Newcastle upon Tyne, Tyne and Wear, United Kingdom, 2 , Mattson Thermal Products GmbH, Dornstadt Germany, 3 CEA-Leti, Minatec, Grenoble France
Show AbstractElectrical activation of in-situ or implantation doped source/drains is a significant constraint on transconductance in Ge PMOS transistors. Defect engineering methods to enhance B activation in Ge are currently in their infancy and further improvements will require a clearer understanding of the basic mechanisms of B diffusion and defect cluster evolution. Recently, Koffel et al. [1] have reported TEM data showing the evolution and dissolution of self interstitial defects in Ge at temperatures in the range 300-600C. Bruno et al. [2] have reported B marker layer diffusion experiments showing orders of magnitude enhancements in diffusion coefficients during proton irradiation or after H implantation through the marker layers. Based on that study it was suggested that, just as in Si, B diffuses by an interstitial-driven intermittent diffusion mechanism.In this work we present experiments using amorphizing self-implantation into Ge doped with buried B marker layers. This choice of implant and target structure reflects interest in the use of pre-amorphisation for B ultrashallow junction formation in Ge, and allows a more controlled experiment on the B diffusion mechanism by eliminating the possibility that vacancy defects are involved. Since the markers are buried beyond the range of the implant, and any excess vacancies within the implant have been eliminated by amorphization, only ‘end of range’ self-interstitial defects can play a role in any transient enhanced B diffusion observed at elevated temperatures.After rapid thermal annealing of the implanted Ge samples, SIMS measurements reveal transient enhanced diffusion of B at temperatures in the range up to 700C, indicating that (i) B diffusion in Ge does occur by an interstitial-driven intermittent diffusion mechanism, as suggested by Bruno [2]; (ii) ‘end-or-range’ self-interstitial defects in Ge evolve and emit interstitials through an Ostwald ripening process, as is known to occur in Si [3]; (iii) part of the EOR defect population remains stable up to higher temperatures than defects observed by TEM [1], suggesting that a sub-set of relatively stable interstitial defects may remain after dissolution of TEM-visible defects. This last point is important as it shows the potential importance of small interstitial clusters in Ge, both as drivers of diffusion and potential sites for deactivation of B by formation of boron-interstitial clusters (BICs). The results obtained in this study offer the possibility of predictive simulation of B doping in Ge within the near future, and provide a basis for designing further improved defect engineering schemes for B activation enhancement.[1] S. Koffel, N. Cherkashin, F. Houdellier, M.J. Hytch, G. Benassayag, P. Scheiblin, and A. Claverie, J. Appl. Phys. 105, 126110 (2009) [2] E. Bruno et al., Phys. Rev. B. 80, 033204 (2009)[3] N.E.B. Cowern et al., Phys. Rev. Lett. 82, 4460 (1999)
5:00 PM - **I4.9
Challenge to High Performance Ge CMOS.
Akira Toriumi 1 2 , Choong Lee 1 , Shengkai Wang 1 , Mahoro Yoshida 1 , Toshiyuki Tabata 1 , Koji Kita 1 2 , Tomonori Nishimura 1 2 , Kousuke Nagashio 1 2
1 , University of Tokyo, Tokyo Japan, 2 , JST-CREST, Tokyo Japan
Show AbstractGermanium attracts much attention from the viewpoint of FET application using its potentially higher performance than silicon. Intrinsic challenges in Ge FETs are mainly derived from (i) interface issues involved in Ge MIS gate stacks and metal/Ge contacts, (ii) smaller band-gap penalty in p-n junction properties, and (iii) various device-integration obstacles. Furthermore, a big challenge of Ge CMOS is to achieve high electron mobility, because p-MOSFETs only have been advantageously reported so far. Intrinsic difficulties in n-MOSFETs have been also discussed in the literatures. The objective of this paper is twofold. One is to establish process concepts of controlling GeO2/Ge and Ge/metal interfaces which are critical building blocks in Ge FETs, and the other is to demonstrate the high electron mobility in Ge n-MOSFETs on the basis of above understandings. First, based on kinetic views of GeO desorption from GeO2/Ge stacks, the quality control of both GeO2 films and GeO2/Ge interfaces is discussed. The mid-gap Dit has been actually reduced down to the order of 1010 cm-2eV-1. The control of oxidation, diffusion and desorption in Ge/GeO2 system is the key for its interface improvement.Second, very high electron mobility in Ge n-MOSFETs is demonstrated. It exceeds the universal one in Si-MOSFETs. This has been achieved by taking care of Ge/GeO2 interface kinetics. It is further discussed from the temperature dependence that the mobility is still limited by remaining scattering sources even in the present high mobility channel. This fact conversely suggests us to expect much higher performance Ge CMOS by more sophisticated process control. Finally, it is shown that Ge (111) surface is better in terms of the thermal process stability as well as the lower effective mass of electron inversion layer. Although it is further required to overcome a number of technical barriers for much higher performance Ge MOSFETs, we have no hesitation in saying that Ge CMOS is a way to go for the next.
5:30 PM - I4.10
Fabrication of La-incorporated Hf-silicate Gate Dielectrics Using PVD-based in-situ Method and its Effective Work Function Modulation of Metal/High-k Stacks.
Heiji Watanabe 1 , Hiroaki Arimura 1 , Yudai Oku 1 , Masayuki Saeki 1 , Naomu Kitano 1 , Takuji Hosoi 1 , Takayoshi Shimura 1
1 Department of Material and Life Science, Osaka University, Suita, Osaka, Japan
Show AbstractLa incorporation into Hf-silicate high-k gate dielectrics was conducted using a PVD-based in-situ method. Metal Hf, La and Hf-La alloy on base SiO2 oxides received in-situ annealing to form high-quality HfLaSiO dielectrics, and subsequent deposition of metal gate electrodes was carried out to fabricate advanced metal/high-k gate stacks without breaking vacuum. The in-situ method was found to precisely control La content and its depth profile and to tune the effective work function of metal/high-k stacks. Remarkable leakage current reduction of almost 7 orders of magnitude compared with conventional poly-Si/SiO2 stacks and excellent interface properties comparable to an ideal SiO2/Si interface were also achieved at an equivalent oxide thickness of around 1.0 nm. XPS analysis revealed that, as previously suggested, effective work function modulation due to La incorporation is attributed to the interface dipole (or localized sheet charge) at the bottom high-k/SiO2 interface, which is crucially dependent on the La content at the interface. Moreover, it was found that high-temperature annealing causing interface oxide growth leads to redistribution of La atoms and forms the uppermost La-silicate layer at the metal/high-k interface by releasing the dipole moment at the bottom high-k/SiO2 interface. Based on these physical and electrical characterizations, the advantages and process guidelines for La-incorporated dielectrics were discussed in detail.
5:45 PM - I4.11
Characterization of Ultra Shallow Arsenic Implants by Grazing Incidence Absorption Spectroscopy.
Florian Meirer 1 5 , Giancarlo Pepponi 2 , Dana Zeelenberg 3 , Damiano Giubertoni 2 , Majeed Foad 4 , Ritimukta Sarangi 5 , Apurva Mehta 5 , Christina Streli 1 , Piero Pianetta 5
1 Institute for Atomic and Subatomic Physics, TU Vienna, Vienna , Vienna, Austria, 5 Stanford Synchrotron Radiation Lightsource, SLAC National Accelerator Laborator, Menlo Park, California, United States, 2 CMM, FBK - irst, Povo, Trento, Italy, 3 Applied Physics, Technical University Delft, Delft Netherlands, 4 , Applied Materials Inc., Sunnyvale, California, United States
Show AbstractKnowledge about the physics of Silicon based nanodevices is increasingly important for the development of future semiconductor technologies. The demand for device dimensions in the nm region leads to new challenges for production and characterization of components which are necessary for next generation electronic devices like microprocessors or application specific integrated circuits (e.g. CPUs). Implantation techniques capable of producing ultra shallow dopant profiles, which define the basic module of these devices, are currently very widely investigated.For measuring the dopant profile produced by these techniques, grazing incidence x-ray fluorescence analysis is a well established very powerful tool, because it is an elemental probe sensitive to the first few nanometers beneath the surface and provides qualitative depth distribution of the dopant. Using synchrotron radiation as the source of x-rays provides several additional advantages. First, the significantly higher brightness dramatically improves the signal to noise and the depth sensitivity yield much more sensitive and accurate dopant depth profiles. But even a greater advantage of synchrotron based techniques is the ability to freely change the incidence x-ray energy and hence the ability to perform grazing incidence x-ray absorption fine structure analysis. GI-EXAFS analysis shows sufficient surface sensitivity and provides the necessary structural information to understand the mechanisms of activation and deactivation of the dopant atoms on implantation techniques, and annealing and subsequent thermal treatments.In here, we will present results obtained at SSRL beam line 10-2 and 2-2 from angle and energy dependent x-ray fluorescence spectra in grazing incidence (GI-EXAFS) and some preliminary grazing exit (GE-XANES) measurements on ultra shallow arsenic implants in silicon fabricated using a range of implantation energies and (laser) annealing power.
I5: Poster Session
Session Chairs
Friday AM, April 09, 2010
Salon Level (Marriott)
9:00 PM - I5.1
Indium Segregation Mechanisms in MBE and MOVPE-grown InAlN Epilayers.
Suman-Lata Sahonta 1 , Thomas Kehagias 2 , Georgos Dimitrakopulos 2 , Josif Kioseoglou 2 , Holm Kirmse 3 , Wolfgang Neumann 3 , Christoph Giesen 4 , Michael Heuken 4 , Adam Adikimenakis 5 , Alexandros Georgakilas 5 , Philomela Komninou 2
1 Materials Science and Metallurgy, University of Cambridge, Cambridge United Kingdom, 2 Department of Physics, Aristotle University of Thessaloniki, Thessaloniki, Makedonia, Greece, 3 Institute of Physics, Humboldt University of Berlin, Berlin Germany, 4 , AIXTRON AG, Herzogenrath Germany, 5 Department of Physics, University of Crete, Heraklion Greece
Show AbstractRecent advances in III-nitride growth have allowed the fabrication of InAlN films which are lattice-matched to GaN, dramatically reducing densities of misfit-induced defects in InAlN/GaN high electron mobility transistors (HEMTs). However the film growth method strongly influences the behaviour of the In, resulting in clustering and segregation to defects. In this work, transmission electron microscopy (TEM) is used to compare the microstructure and chemical composition of InAlN films grown on (0001) GaN templates by molecular beam epitaxy (MBE) and metal-organic vapour phase epitaxy (MOVPE). MBE-grown films exhibit hexagonal columnar domains of 10 to 15 nm in diameter, regardless of epitaxial mismatch strain. Z-contrast and energy dispersive X-ray (EDX) analysis show increasing In content towards domain boundaries. Inverted pyramidal V-shaped depressions (V-defects) with a density of 7.5 x 109 cm-2 are observed on the (0001) surface of compressively-strained MOVPE-grown InAlN films. The V-defects possess {10-11} sidewall facets and originate from open-core threading dislocations. EDX reveals enrichment of In at V-defect apices, edges and the (0001) surface surrounding the V-defects. Both of these phenomena are due to the high growth temperatures employed in InAlN growth (around 600 °C for MBE and 800 °C for MOVPE), well above the dissociation temperature of the InN bond (< 550 °C), resulting in In adatoms with high surface mobility and desorption, coupled with a low sticking coefficient due to the weak In-N bond compared to the Al-N bond. The migration of In to adsorption sites of low coordination number results in the formation of an In-rich adlayer in both MBE and MOVPE growth. Two-dimensional (2D) film growth is maintained throughout MOVPE growth, whereas in-situ studies show a 2D to 3D transition in the early stages of MBE growth. For MBE growth, InAlN grows on the GaN (0001) surface as Al-rich dynamical platelets owing to rapid strong AlN bond-formation concurrent with evaporation of impinging In adatoms. At the onset of platelet coalescence, the relative relaxation at platelet edges combined with momentary tensile strain generation between coalescing platelets results in the preferential incorporation of In at platelet boundaries. This sets up a concentration gradient which is maintained throughout the film growth, resulting in the observed microstructure. In the case of MOVPE-grown InAlN, the presence of In at the dislocation core reduces its surface energy and strain energy, whilst simultaneously increasing the relative surface energy of the (0001) surface with respect to the {10-11} planes, promoting the widening of open-core dislocations into V-defects. In enrichment at V-defect edges is attributed to the migration of In along energetically-favourable pathways of low coordination number such as the <11-23> and <1-210> edges at the V-defect facet junctions and their intersections with the (0001) surface respectively.
9:00 PM - I5.10
Observation of Hole Tunneling in Work Function Measurements of Metals on O2/SiO2/Si Stacks.
Jonathan Rothschild 1 , Hagit Avraham 1 , Eran Lipp 1 , Moshe Eizenberg 1
1 Materials Engineering, Technion - Israel Institute of Technology, Haifa Israel
Show AbstractThe down-scaling of device dimensions requires new materials for the gate stack. Recently, high-K dielectrics and metals replaced SiO2 and poly-Si, respectively. Still, many problems regarding the replacement materials are left unsolved. The effective work function (EWF) of the gate electrode determines the threshold voltage and consequently the performance of the device. The most common method to measure the EWF in MOS capacitors is the capacitance-voltage method, which is both complicated and imprecise in high-K stacks. Zafar et al. 1 introduced a current-voltage (IV) method which is based on the transition from direct tunneling (DT) to Fowler-Nordheim tunneling (FNT) of electrons in thin oxide layers. The voltage of the transition, which is characterized by a peak in the dlnI/dV vs. V plot, allows extraction of the barrier height between the oxide and either the Si or the electrode. In our work we applied Zafar's method in order to characterize the EWF of metals on an HfO2/SiO2/n-Si stack. We used thin stacks of thermally grown SiO2 and atomic layer deposited (ALD) HfO2 capped by Al and Pt metal contacts. The band structure of these ALD HfO2 films was previously studied by our group and exhibited conduction- and valence- band offsets of 2.7 eV and 1.5 eV, respectively. In the current work IV measurements were performed on the capacitors and peaks were observed at gate voltage values of -0.7 ±0.1eV for Pt and -2.1 ±0.1eV for Al. These peaks indicate a transition from DT to FNT which could be attributed to two different mechanisms. The first is an electron trap-assisted tunneling current from the metal to the Si, due to defects in the HfO2 layer. This possibility is ruled out because it is determined by the barrier between the HfO2 defect level and the Si Fermi energy, and therefore the voltage difference between the observed peaks is expected to be much smaller. The second mechanism is hole tunneling from the Si to the metal through the HfO2 valence band. In this mechanism the peaks are determined by the barrier between the metal's Fermi energy and the valence band edge of the HfO2. Analyzing the results according to the latter mechanism yields EWF values of 4.5 ±0.1eV and 5.7 ±0.1eV for Al and Pt, respectively. The slight shift from published vacuum work function values can be attributed either to measurement errors or to a dipole layer at the SiO2/HfO2 interface.1. S. Zafar, E. Cartier, and E. P. Gusev, Appl. Phys. Lett. 80, 2749 (2002).
9:00 PM - I5.11
Vapor Pressure Apparatus for Metal-organic Samples.
Robert Berg 1
1 , NIST, Gaithersburg, Maryland, United States
Show AbstractA metal-organic precursor is frequently used to create an oxide or nitride layer in semiconductor devices. Vapor pressure is the precursor’s most important physical property because the compound is delivered as a vapor to the process chamber either by direct injection (flash evaporation) or by flow a carrier gas through a bubbler. The present apparatus measures the vapor pressures of metal-organic liquids in the pressure range from 10 Pa to 100 kPa and at temperatures from 25 °C to 200 °C. It uses capacitance diaphragm pressure gauges that operate at a temperature above that of the sample. The liquid part of the sample is contained in a tube whose temperature is held 2 K below that of the surrounding oven; this ensures control over the location and temperature of the liquid-vapor boundary. A thermoelectric cooler controls the sample’s temperature with a stability of 2 mK, and measurements of water’s vapor pressure agree with accepted values to within 1 % at temperatures from 30 °C to 100 °C. Challenges for measuring the metal-organic compounds include handling hazardous samples and avoiding systematic errors due to the presence of decomposition products, dissolved gases, and other impurities. To measure thermal stability, a gas chromatograph / mass spectrometer has been incorporated into the apparatus.
9:00 PM - I5.12
Nanoscale Study of the Influence of Atomic Oxygen on the Electrical Properties of LaAlO3 Thin High-k Oxide Films Deposited by Molecular Beam Epitaxy.
Wael Hourani 1 , Liviu Militaru 1 , Brice Gautier 1 , David Albertini 1 , Armel Descamps-Mandine 1 , Sylvain Pelloquin 1 , Carole Plossu 1 , Guillaume Saint-Girons 1
1 University of Lyon, Lyon Institute of Nanotechnology, Lyon France
Show AbstractThe miniaturization of the metal oxide semiconductor MOS devices following the Moore’s law has lead to the extreme thinning of the commonly used SiO2 gate oxide. However, this thinning has reached its limits because of the increase of the leakage current through the oxide, causing the degradation of the devices. Therefore, alternative high dielectric constant (high-k) oxides have been studied to replace the classical SiO2 oxide.Amorphous LaAlO3 (LAO) high-k oxide appears as an interesting candidate in replacing the SiO2 oxide; it presents a high band gap of 5.6 eV, a large conduction band offset of 1.8 eV with respect to Si and a dielectric constant of 25 in its bulk crystalline phase. Moreover, LAO is stable in air and is theoretically thermally stable in contact to silicon up to 1000 °C.On the other hand, degradation and breakdown under electrical stress is one of the important reliability concerns of gate oxides. Since the breakdown phenomenon of oxides is a highly localized phenomenon, the microscopic may provide additional information compared to the macroscopic characterization. Therefore the atomic force microscope (AFM) is used to characterize high-k oxides since its probe tip area is in the same order of magnitude as the breakdown spot, so we can avoid the problem of short circuits which can take place between macroscopic electrodes and the Si substrate during the characterization of oxides having many leakage spots. Moreover, the so-called Tunneling AFM (TUNA) is a very sensitive mode by which we can measure currents ranging from 60 fA to 120 pA.Thin LAO films were deposited on p-type Si (100) substrates (10^15 cm^-3) in an oxide-dedicated molecular beam epitaxy (MBE) reactor by electron beam evaporation of crystalline LAO targets at a substrate temperature of 400 °C in a controlled molecular O2 ambient (P(O2) ranging from 10^-8 to 10^-5 Torr). Different samples have been studied, differing in time of deposition (i.e. the oxide thickness) and the type of deposition of LAO. Current maps have been recorded simultaneously with topography in contact mode using the TUNA mode of the AFM. Spectroscopic data (Current-Voltage) have been obtained by stopping the tip over a precise region of the sample and applying Ramped Voltage Stress (RVS). Current maps and Current-Voltage curves are compared for the different growth conditions of LAO.We show that the layers’ deposition within atomic oxygen ambient leads to a better electrical characteristics of the dielectric layers, leading to a smaller amount of leakage spots in the current image, in contrary to the other samples that were deposited without atomic oxygen. This experimental fact is discussed, and may be explained by the filling of oxygen vacancies by oxygen atoms, hence reducing the density of conduction paths for electrons between the gate and the substrate through the LAO oxide.
9:00 PM - I5.13
Impact of Ge Doping on Si Substrate and Diode Characteristics.
Jan Vanhellemont 1 , Johan Lauwaert 1 , Jiahe Chen 1 2 3 , Henk Vrielinck 1 , Joan Marc Rafi 4 , Hidenori Ohyama 5 , Eddy Simoen 6 , Deren Yang 2
1 , Ghent University, Ghent Belgium, 2 , Zhejiang University, Hangzhou China, 3 , TU Dresden, Dresden Germany, 4 , CNM, Barcelona Spain, 5 , KNCT, Kumamoto Japan, 6 , IMEC, Leuven Belgium
Show AbstractIt can be envisaged that the substrates of choice for beyond the 22 nm technology node will be the 300 and 450 mm Si wafers. Besides the technical challenges to pull such large diameter dislocation free crystals with sufficient length and yield to be economically viable, there are also material related issues that have to be solved.With increasing diameter, the oxygen concentration in the crystal decreases due to the use of magnetic fields to control the melt movements. This reduces the interaction of the melt with the quartz crucible wall and the oxygen transport to the crystal. The reduced oxygen concentration and the lower thermal budget of modern device processing leads to reduced oxygen precipitation and internal gettering capacity.At the same time the size of voids in the crystal leading to the formation of COP's on the wafer surface increases with increasing crystal diameter. This is due to the decreasing pulling rate and thermal gradient. With each increase of wafer diameter, the wafer thickness over wafer diameter ratio is decreasing leading to a reduced mechanical wafer strength making it more prone to warpage and plastic deformation.One approach to reduce these problems is doping the crystal with an element that is not electrically active, enhances oxygen precipitation, reduces the vacancy concentration available for void formation and acts as a locking agent for dislocations. A typical example is doping with nitrogen which is commercially used although it is difficult to control the nitrogen concentration due to its limited solubility which is close to the detection limit of most analytical techniques. Doping with nitrogen can also lead the unwanted electrical effects during thermal treatments by the formation of thermal donors.In the present paper the beneficial effects of Ge doping on substrate and diode characteristics will be discussed and illustrated. Ge doping leads to increased oxygen precipitation during device processing leading to improved internal gettering in low oxygen content material while at the same time suppressing thermal donor formation [1]. Ge doping also influences COP formation as it leads to larger densities of smaller COP's compared to undoped Si for the same pulling conditions [2]. This is due to the Ge atoms acting as trap for vacancies close to the Si melt temperature. Further more Ge doping leads to an increased mechanical strength [3] leading a.o. to reduced wafer breakage not only during crystal wafering but also during device processing. The effect of Ge doping on diode characteristics and on radiation hardness will be illustrated [1,4,5] and correlated with detailed characterization of the formed defects using DLTS and FTIR analyses.1. J.M. Rafí et al, Physica B, in press.2. J. Chen et al, J. Cryst. Growth 306 (2007) 262.3. I. Yonenaga, J. Cryst. Growth 275 (2005) 91.4. H. Ohyama et al, Physica B, in press.5. J. Vanhellemont et al, submitted for publication in J. Cryst. Growth.
9:00 PM - I5.14
Reliability of DRAM Deep Trench Nitrided SiON Dielectric With Poly and Carbon Electrodes.
Suresh Uppal 1 , Tim Boescke 2
1 , Dublin City University, Dublin Ireland, 2 , Ersol Solar Energy AG, Erfurt Germany
Show AbstractThis paper investigates the effect of using a carbon (metallic) electrode instead of a poly-Si top electrode on the reliability of the nitrided SiON based dielectric used as a storage dielectric in the deep trench DRAM technology. Using accelerated constant voltage stressing and long term package data, Time Dependent Dielectric Breakdown (tddb) of the dielectric was studied in substrate as well as top injection modes. It is shown that the voltage acceleration for the dielectric follows a progressive power-law with an acceleration factor ~47 for top and bottom electrode injection modes. The results support the Anode Hydrogen Release model for a power law voltage acceleration of the tddb.
9:00 PM - I5.16
Effect of Boron Dose on Activation and Solid Phase Epitaxial Regrowth in Germanium.
Brad Yates 1 , Blake Darby 1 , Kevin Jones 1
1 Materials Science, University of Florida, Gainesville, Florida, United States
Show AbstractIn order to stay on pace with the scaling milestones dictated by the International Technology Roadmap for Semiconductors (ITRS), the use of germanium is being investigated as an alternative channel material for CMOS devices. In this study, we have taken a comprehensive examination of dopant activation and regrowth kinetics of B-implanted Ge. In comparison to recent articles that have studied high-energy B implants, we will discuss the effect of ultra-low energy implants on the activation characteristics. For this study, (100) Ge wafers were preamorphized (PA) with Ge (20keV, 1E14/cm2) and were subsequently implanted with 1keV B doses ranging from 1E14/cm2 to 2E15/cm2 in order to encompass peak concentrations above and below the maximum reported active dose in Ge. Samples were annealed using rapid thermal annealing over a range of temperatures. Electrical activation studies were completed by Hall Effect using the Van der Pauw method and compared to total chemical dose measurements acquired through nuclear reaction analysis. The second part of this work measured the regrowth kinetics of PA Ge as a function of B dose. Samples were isothermally annealed and the amorphous layer thickness was measured by a combination of cross-sectional TEM and ellipsometry. Results of the activation and regrowth kinetics experiments will be reported and discussed herein.
9:00 PM - I5.18
Contact Technology Using Pulsed Laser Annealing to Form Ti/Al Ohmic Contacts on n-type GaN With Lower Contact Resistance and Improved Surface Morphology.
Grace Huiqi Wang 1 , Tripathy Sudhiranjan 1 , Xincai Wang 2 , Siew Lang Teo 1 , Debbie Hwee Leng Seng 1 , Poh Chong Lim 1 , Sze Yu Tan 1 , Yong Lim Foo 1
1 , Institute of Materials Research and Engineering (IMRE), Singapore Singapore, 2 , Singapore Institute of Manufacturing Technology, Singapore Singapore
Show AbstractGallium nitride and III-V compounds have received considerable attention as it opens up new opportunities for widespread applications in electronic devices. Beyond the 22nm technology node, III-V semiconductor materials have gained considerable interest in high power and high performance devices for “more than Moore” applications.Achieving thermally stable,low resistive ohmic contacts is critical for nanoscale devices.Wide bandgap III nitride semiconductors impede achievement of low resistance and upon high temperature annealing,Ti-Al metal discontinuity results in higher contact resistivity. In this work, we adopt a novel process which employs laser annealing(LA) for metal contact formation on nGaN.Ti (35nm)/Al(150nm) contact schemes were ebeam evaporated onto nGaN. LA was carried out in purging N2 ambient using a 248nm pulsed KrF excimer laser. A systematic study of LA on contact properties was performed.Laser irradiation using multiple(1,5,10 & 20) pulses at various laser fluences in the range of 0.18 to 0.7Jcm−2 was carried out to study the effects of repeated irradiation on Ti/Al.Measurement of current-voltage (I-V) through the metal contacts to nGaN is linear even at sufficiently large current(100mA).Ohmic contact is formed. The advantage of using LA,was that it reduced the barrier height more effectively than RTA, thus resulting in lower contact resistivity.0.52J cm−2 5 pulses LA reduced the bulk resistivity(ρ)of the film to 4.8e-6ohm-cm as compared to RTA at 8700C,30s[9.5e-4ohm-cm].Lower ρ is attributed to minimal reaction of GaN with TiAl during the short duration irradiation.Increasing laser energy from 0.3Jcm−2 to 0.52Jcm−2 improved ρ from 7.2e-5 ohm-cm to 4.8e-6 ohms-cm. However ρ degraded at higher laser energy of 0.7 Jcm−2 (1.3e-5ohm-cm). At 0.7Jcm−2, due to a larger melt depth,Ga interaction with Al, induced surface roughening and increased sheet resistance. Repeated irradiation at 0.52Jcm−2 also increased ρ (1 pulse [4.3e-6ohms-cm],5 pulses[4.8e-6 ohms-cm]and 20 pulses[1.2e-5ohms-cm]. It similarly promoted deeper Al diffusion. SIMS and RBS analysis are adopted to study the diffusion mechanisms of Ti and Al in GaN after LA.TEM is performed to investigate the morphological changes in Ti/Al. XRD effectively determines the Ti-Al interfacial reactions at various laser fluences. At an optimal laser fluence of 0.52J cm−2 5 pulses, Al was completely consumed to form AlTi,Al2Ti and Al3Ti intermetallic phases that exhibit higher melting points and lower diffusivities than Al. This is vital as excessive Al diffusion is responsible for rough surface and higher ρ. Contact resistance lowering is also attributed to increased content of Al3Ti and AlTi. AFM scan further reveals rms roughness ~0.5nm after LA. Ti/Al on GaN with a smooth morphology and improved electrical stability was achieved with LA. In conclusion, contact formation by pulsed laser irradiation is promising for integration with III-V substrates for future device applications.
9:00 PM - I5.19
Modelling the Si(110) Surface.
Veronika Brazdova 1 2 , David Bowler 1 2
1 London Centre for Nanotechnology, University College London, London United Kingdom, 2 Department of Physics & Astronomy, University College London, London United Kingdom
Show AbstractSilicon has been immensely important in condensed matter physics, surface science and industrial applications. The Si(001) and Si(111) surfaces have been intensively studied, and the elucidation of their complex reconstructions has advanced the study of their surface properties. Si(110) has been less intensively studied, but also shows interesting scientific and technological properties. First, it exhibits a complex stepped (16x2) reconstruction, whose atomic structure is still not fully understood (proposed structures do not fit all available experimental data). Second, recent developments in CMOS transistor technology (e.g., FinFETs[1] and structures grown by patterned ALE[2]) are either grown on or create Si(110) surfaces. The growth process involves gas sources which will leave hydrogen and possibly silicon on the sidewalls, and understanding how these species diffuse on Si(110) is vital to controlling growth. We will present results of comprehensive density functional theory studies on the diffusion of Si and H adatoms on Si(110)-(1x1), as well as of the driving mechanisms behind the surface reconstruction. The diffusion studies are a necessary starting point for understanding the growth of features with (110) sidewalls; the Si adatom diffusion will also feed into the studies of Si(110)-(16x2), as the formation of this reconstruction seems to involve significant amounts of mass transport. Barriers and structures resulting from diffusion will be presented, and their implications for growth and reconstruction will be discussed. We will discuss the implication of Si atom adsorption and surface defect formation on the reconstruction of the surface.References[1] Mizuno, T.; Sugiyama, N.; Tezuka, T.; Moriyama, Y.; Nakaharai, S.; Tak-agi, S. IEEE Trans. Electron Devices 2005, 52, 367.[2] Suda, Y.; Hosoya, N.; Miki, K. Appl. Surf. Sci. 2003, 216, 424-430.
9:00 PM - I5.2
USJs Formation Combining He and Si Implantation With Plasma Immersion Ion Implantation in Silicon.
Ming Xu 1 3 , Rachid Daneche 2 , Esidor Ntsoenzok 3 , Gabrielle Regula 1 , Bernard Pichaud 1
1 , IM2NP CNRS , Marseille France, 3 , CNRS-CEMHTI, Orleans France, 2 , CIM-PACA , Marseille France
Show AbstractTo stick with the ever shrinking dimensions of the electronic devices for their very large scale integration in order to increase their performances, many ways to create USJs have been designed. All of them aim to tackle the so-called transient enhanced diffusion of the dopant, due to unavoidable creation of self interstitials during the doping step performed by ion implantation. Recently, silicon on insulator coupled with Si implantation [1, 2] or carbon co-implantation with Si [3], were proposed. Our approach deals with the formation of cavities, induced by He implantation at 10keV or 50 keV both with a dose of 5×1016 He cm-2 followed by thermal annealing at 800°C for one hour in a conventional furnace under Ar atmosphere, as self interstitial diffusion barrier. Then, a high quantity of vacancies was introduced in the sample at various distances from the surface, by Si implantation at the energy range 180keV-300keV and dose 1015cm-2 -1016 cm-2, to determine the most pertinent implantation parameters: indeed, a compromise must be set since the surface plays a huge role in vacancy annihilation. The Si implantation energy was chosen high enough to get two separated rich regions, one of self interstitials and the other of vacancies. Eventually, the sample was immersed in a BF3 plasma and implanted 1.2 keV and 5×1015 cm-2. The dopant activation was performed at 1000°C for 1s to 20s. For comparison, junctions were also formed by co-implanting He and B or Si and B. The achieved junction depths, measured by secondary ion mass spectrometry was from 7nm for both tri-implantion and He B co-implantation while a depth of 26 nm was reported for Si and B co-implantation. Electrical characterization and further studies to get a better insight on the role of the fluorine are under progress. [1] J. J. Hamilton, N. E. B. Cowern, J. A. Sharp, K. J. Kirkby, E. J. H. Collart, B. Colombeau, M. Bersani, D. Giubertoni, A. Parisini, Appl. Phys. Lett, 89, 042111 (2006)[2] A. J. Smith, N. E. B. Cowern, R. Gwilliam, B. J. Sealy, B. Colombeau, E. J. H. Collart, S. Gennaro, D. Giubertoni, M. Bersani, M. Barozzi, Appl. Phys. Lett, 88, 082112 (2006)[3] B. J. Pawlak, T. Janssens, B. Brijs, and W. Vandervorst, E. J. H. Collart, S. B. Felch, N. E. B. Cower, Appl. Phys. Lett. 89, 062110 (2006).
9:00 PM - I5.20
Micro Probe Carrier Profiling of Ultra-shallow Structures in Advanced Materials.
Trudo Clarysse 1 , Alain Moussa 1 , Brigitte Parmentier 1 , Pierre Eyben 1 , Bastien Douhard 1 , Wilfried Vandervorst 1 2 , Peter Nielsen 3 , Rong Lin 3
1 , IMEC, Leuven Belgium, 2 Dept. of Physics-IKS, KU Leuven, Leuven Belgium, 3 , Capres A/S, Kongens Lyngby Denmark
Show AbstractThe performance of most electronic devices relies on the precise tailoring of the carrier distribution in the semiconductor. For earlier CMOS technologies, the spreading resistance probe (SRP) was a reliable tool to extract quickly one-dimensional carrier depth profiles to be compared with the total dopant concentration as measured by secondary ion mass spectrometry (SIMS). This allowed extracting the integrated active dose and the activation degree (if mobility information is available). For today’s and future technologies, involving sub-30 nm dopant profiles, SRP has, however, become obsolete, due to its too large contacts (1-2 μm) and large separations (20-40 μm) leading to very large correction factors (>1000) and the need for many correction schemes addressing various artifacts (carrier spilling, surface damage, 3D current flow, etc.) [1]. Moreover its application to new high-mobility materials such as Germanium or III-V is hampered by excessive probe penetration (20-30 nm), contact resistance problems, etc.. For III-V, the Electrochemical Capacitance Voltage tool is in principle a possible alternative, but also has limitations of its own for ultra-shallow junctions (accurate etching rate control, carrier spilling, etc.) [2]. Hence at present there is no reliable concept for profiling carrier distributions in new materials.In this paper, we will present a very promising new approach towards carrier profiling. The latter is based on the micro four point probe (M4PP) which was introduced to measure surface sheet resistances with virtually zero-penetration and high accuracy (< 1%) on very localized structures [3]. For this purpose M4PP uses very low force, small Ni contacts (10-50 nm) with separations down to 1.5 μm. When measuring the sheet resistance along a beveled structure, the sheet resistance versus depth information can be translated directly into a resistivity or carrier depth profile. The low force (10-5 N), which implies much less pressure induced carrier spilling than SRP, the fact that the four point probe concept itself is independent of contact resistance and does not rely on any physical modeling corrections, make this concept particularly advantageous for Ge, GaAs and InGaAs structures where SRP is not applicable. Issues relating to bevel surface roughness, starting point definition, dependence of dynamic range of the raw data on the measurement settings, sampling volume, smoothing, etc. will be discussed. A comparison will be made with SIMS, SRP and Scanning Spreading Resistance Microscopy [4] on sub-100 nm structures in Ge, GaAs and InGaAs materials. Ref.:[1]T.Clarysse, et al. Mater. Sci. Rep. R 47 (2004) 123-206[2]T.Clarysse et al, Mater. Sci. in Semic. Proc. 11 (2008) 259 [3]D.H. Petersen, et. al., J. Vac. Sci. Technol. B 26 (2008) 362 [4]P.Eyben et al., in “Scanning Probe Microscopy, Electrical and Electromechanical Phenomena at the Nanoscale”, ed. S. Kalinin and A. Gruverman (Springer,2007), Vol. 1, Chapt. 2, p. 31
9:00 PM - I5.21
Vacuum Deposition of Low-k Polymer Films With Low Creep and Low Loss.
Jose Anguita 1 , Ravi Silva 1
1 Advanced Technology Institute, University of Surrey, Guildford United Kingdom
Show AbstractLow dielectric constant (low-k) materials development is of escalating importance, since the RC delays pose a fundamental limitation in the continuous scaling down of devices. The International Technology Roadmap for Semiconductors (ITRS) defines a requirement for reducing current k-values to 1.9-2.3 for interlevel structures for the year 2015. It further concludes that “manufacturable solutions are not yet known”, and it is speculated that this has led to “multiple-core” strategies. Long-established plasma deposited ceramic dielectrics show high k-values and mechanically rigid films, often with poor thermal match to their substrates, susceptible to adhesion failures. Existing spin-on polymers are more flexible, but require the use of solvents, which result in loss at operating frequencies above 1GHz, even after hard curing. Lastly, current ultralow-k (ULK) materials are porous ceramic materials that become brittle with the porosity, and require multiple prolonged and unreliable curing stages at elevated temperatures. We present a single-stage, solvent-free and room temperature PECVD process for depositing a highly crosslinked polymer material either as a continuous low-k film or as a porous ULK film, with k-values of 2.1 and 1.4 respectively. These values are in line with ITRS requirements for future commercial applications for the next decade. Unlike organo-silicate glass and spin-on low-k polymer materials, no post-deposition curing stages are necessary. The crosslinked polymer exhibits hybrid mechanical properties between ceramics, such as thermal stability to 500°C and near-zero creep displacement, whilst maintaining flexibility and near stress-free growth conditions attributed to polymers. This allows accommodating thermal mismatch, whilst also allowing for CMP BEOL processes that are necessary for device fabrication. Such mechanical processes become spoiled when using typical polymer materials, due to creep displacement. Furthermore, no solvent (or water) is used in the growth, allowing for low-loss operation at higher frequencies, and eliminating curing requirements and associated complications.We report the porosity in the ULK film is achieved by operating the PECVD chamber in a process regime that favours a diffusion-limited aggregation process for film growth, and show film thickness values circa ½ millimetre with high deposition rate, around 20µm.min-1. We show successful growth of this film to several millimetres thick, without adhesion failures. We show the ability to operate the PECVD chamber in this regime is a result of the plasma dynamics, and therefore can be extended to introduce porosity in other material systems such as silicon-based materials, and also eliminate the porogen removal curing stages from current ULK materials. The process is environmentally friendly and chlorine free.
9:00 PM - I5.22
Structural and Electrical Properties of ALD Deposited Er-HfO2 for Gate Dielectric Applications.
Claudia Wiemer 1 , Luca Lamagna 1 , Silvia Baldovino 1 2 , Michele Perego 1 , Olivier Salicio 1 , Sylvie Schamm-Chardon 3 , Pierre-Eugene Coulon 3 , Marco Fanciulli 1 2
1 Laboratorio MDM, CNR-INFM, Agrate Brianza, Mi, Italy, 2 Dipartimento di Scienza dei Materiali, Università degli Studi di Milano-Bicocca, Milano Italy, 3 CEMES CNRS and Université de Toulouse, nanoMat group, Toulouse France
Show AbstractDoped high dielectric constant (high-k) oxides open new scaling perspectives for logic and memory devices. Actually, the insertion of a dopant element within the metallic sub-lattice of HfO2 has been demonstrated to stabilize metastable crystallographic structures [1]. Crystallization of HfO2 in polymorphs different than the monoclinic enhances the oxide dielectric constant. In particular, doping HfO2 with a rare earth element has been calculated to stabilize the cubic phase for dopant percentages above 9.9% [1]. The case of Er-doped HfO2 is of particular interest, since Er has one of the highest electronegativities and of the lowest ionic radii of the lanthanide series, therefore presenting a reduced tendency for hydroxide formation. Er-doped HfO2 films have been deposited on Si(100) by atomic layer deposition (ALD) using (iPrCp)3Er and (MeCp)2HfMe(OMe), respectively as Er and Hf source, and O3 as oxygen source. Different chemical compositions were explored by tuning the ALD pulses ratio. The Er/Hf chemical content was measured by total reflection X-ray fluorescence, and its uniformity within the layer thickness was checked by time of flight secondary ion mass spectroscopy. The film thickness was measured by spectroscopic ellipsometry, X-ray reflectivity and transmission electron microscopy.Different crystallographic structures were obtained by varying the Er content. Selected area electron diffraction patterns and X-ray diffraction analysis revealed that, within the fluorite structure, phase stability upon annealing up to 900°C in N2 is verified on Si for Er content as low as 8%.C-V characteristics are measured on MOS structures including Er-HfO2. As a general trend, for Er percentages below 8% the k value or Er-HfO2 decreases due to the increase of the monoclinic phase content, differently, the interface state defects decreases with decreasing Er content. Dielectric constant values even higher than the one calculated for the fluorite polymorph of HfO2 [2] have been extracted, therefore confirming both the stabilization of the cubic phase and the beneficial role on the dielectric response of the Er3+ ions inserted within the metallic sub-lattice. As compared with pure HfO2 crystallized in the monoclinic phase, lower leakage currents for comparable equivalent oxide thickness (EOT) are measured for films with 15% Er content, due to the increased physical thickness of the high-k layer. On the other hand, the introduction of Er3+ results in the creation of oxygen vacancies that partially compensate the negative fixed charges present in the oxide, as deduced from the plot of the flat band voltage shifts towards EOTs.References:[1] C. K. Lee, E. Cho, H. S. Lee, C. S. Hwang, and S. Han, Physical Review B 78, 012102 (2008).[2] Xinyuan Zhao and David Vanderbilt, Physical Review B, 65, 233106, (2002).
9:00 PM - I5.23
Atomic Imaging of the Unpinning and Passivation of a Compound Semiconductor Surface During Atomic Layer Deposition.
Jonathon Clemens 1 , Evgueni Chagarov 1 , Andrew Kummel 1 , Martin Holland 2 , Ravi Droopad 3
1 Chemistry and Biochemistry, University of California, San Diego, La Jolla, California, United States, 2 Electronics and Electrical Engineering, University of Glasgow, Glasgow, Scotland, United Kingdom, 3 Physics, Texas State University-San Marcos, San Marcos, Texas, United States
Show AbstractFormation of an unpinned, atomically smooth high-κ oxide-semiconductor interface is a key challenge in the development of III-V MOSFET technology. Atomic layer deposition (ALD) of Al2O3 has been used successfully on InGaAs with a low interfacial density of states.1 Many of the high performance n-channel enhancement mode InGaAs MOSFETs have been fabricated using ALD for the Al2O3 gate oxide.2 This shows that the metal ALD precursor, trimethylaluminum (TMA) is unusually favorable for growth of Al2O3 on InGaAs. The reaction of TMA on the group III rich (4 × 2) reconstructions of the InAs(0 0 1) and InGaAs(0 0 1) surfaces is studied using scanning tunneling microscopy (STM), scanning tunneling spectroscopy (STS), and density functional theory (DFT). These (4 × 2) III-V surface reconstructions consist of rows of group III atoms in the [1 1 0] direction that are separated by trough regions that contain group III dimers.3 After 200 °C annealing temperatures, individual bonding sites for TMA are identified with STM. At low coverage, the TMA dimer undergoes dissociative chemisorption into two dimethylaluminum (DMA) molecules and occupies adjacent bonding sites in the trough region of the III-V surfaces, bridging the group III rows. At higher coverages, a site selective, self-terminated ordered reconstruction is observed that forms rows in the [-1 1 0] direction with domain sizes on the order of a few thousand Å2 and very low RMS roughness (~1 Å). The bonding geometry of DMA on these surfaces is modeled using DFT and is shown to satisfy tetrahedral covalent bonding requirements of the substrate; the surface reconstruction does not require displacement of substrate atoms. Most importantly, STS experiments show that complete monolayer coverage of DMA on InGaAs(0 0 1)-(4 × 2) removes the surface Fermi level pinning that is present on the clean semiconductor surface. This is consistent with successful electronic passivation of the InGaAs(0 0 1)-(4 × 2) surface by initiating ALD growth of Al2O3 with a “metal-first” ALD precursor reaction.1 H. C. Chiu, L. T. Tung, Y. H. Chang, Y. J. Lee, C. C. Chang, J. Kwo, and M. Hong, Appl. Phys. Lett. 93 202903 (2008).2 Y. Xuan, Y. Q. Wu, and P. D. Ye, IEEE Elec. Dev. Lett. 29 294 (2008).3 D. L. Feldwinn, J. B. Clemens, J. Shen, S. R. Bishop, T. J. Grassman, A. C. Kummel, R. Droopad, and M. Passlack, Surf. Sci. 603 3321 (2009).
9:00 PM - I5.24
Atomic Layer Deposition of Higher-k Dielectrics of Hafnium-Lathanum-Titanate Oxide.
Shih Wei Yu 1 , Jyun Yi Wu 1 , Ming Ho Lin 1 , Che Hao Chang 2 , Tai Bor Wu 1
1 Material Science and Engineering, National Tsing-Hua University, HsinChu Taiwan, 2 , Taiwan Semiconductor Manufacturing Company, Ltd., HsinChu Taiwan
Show AbstractHigh-k materials have attracted great attention for their applications in nano-scaled CMOS structures and memory. However, with the trend of scaling down in International Technology Roadmap for Semiconductors (ITRS), seeking for higher-k dielectric oxides will be the key to meet the requirement for 22 nm and 15 nm node of CMOS technology.In this study, we deposited Hfnium-Lathanum-Titanate (HLTO) films in stacks and alloy structure with several composition of La/Ti ratios via atomic layer deposition (ALD) technique. The electrical characteristics were measured in C-V and I-V relations, and the microstructure of thin films was inspected by transmission electron microscopy (TEM), X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS).This new high-k materials exhibit better properties than traditional HfO2 thin film which display higher permittivity and lower EOT.
9:00 PM - I5.26
Defect-free GaP Growth on Si(001) Substrates for III/V Device Integration.
Kerstin Volz 1 , Andreas Beyer 1 , Wiebke Witte 1 , Igor Nemeth 1 , Bernardette Kunert 1 , Wolfgang Stolz 1
1 Department of Physics and Materials Science Center, Philipps University Marburg, Marburg Germany
Show AbstractIn order to realize true monolithic integration of III/V devices on Si substrates, a defect-free nucleation layer is of outmost importance. As CMOS industry nowadays focuses on exactly oriented (001) Si substrates, the integration of a III/V semiconductor based device structure, employing either lattice relaxed III/V layers for high electron mobility devices or the pseudomorphically strained, active direct-band gap material Ga(NAsP) for optic devices, also has to be pursued on this substrate type. The III/V nucleation layer we use is GaP-based due to the similar lattice constants of GaP and Si. Besides the known challenges of III/V on IV heteroepitaxy, like charge neutrality of the interface, cross-diffusion of dopants and slight differences in lattice constant and thermal expansion coefficient, nucleation on exact Si substrates furthermore poses the challenge of the formation of antiphase domains. These form as the exactly oriented Si suface is covered with monoatomar steps and they can either be allocated on {111} lattice planes, eventually self-annihilating each other, or can lie on {110} lattice planes, propagating through the complete III/V epitaxial layer. The present paper will correlate the structural properties of GaP/Si nucleation layers to the metal organic vapour phase epitaxial growth (MOVPE) conditions and give examples of III/V device layers grown on these nucleation layers.Prior to the deposition of the heteroepitaxial III/V layer, a 500nm thick Si-buffer is grown by VPE using Silane. The GaP layer is grown with triethylgallium (TEGa) and the more efficiently decomposing metal organic group-V-source tertiarybutyl phosphine (TBP). The MOVPE growth conditions of thin GaP layers on Si substrate have been varied systematically, e.g. growth temperature, TBP/TEG vapour phase ratio and sequence of the first III/V coverage layer. Main investigation technique for the III/V layers on the Si substrates was transmission electron microscopy, as this method, when special techniques are employed, allows for the detection of all possible defects, which eventually arise when growing GaP on Si.Under optimized growth conditions a two dimensional GaP-nucleation is achieved, which facilitates the deposition of high quality III/V device materials on Si substrates. There is a strong correlation between the development of antiphase boundaries and the III/V growth conditions, the Si-surface pre-treatment and the wafer miscut, which will be discussed in detail.In summary, we will present and discuss ways and mechanisms for defect-free GaP thin films on exact Si(001) substrates and show how these nucleation layers can serve as substrates for the integration of III/V devices on silicon.
9:00 PM - I5.27
Atomic Scale Modeling of High-k/Ge Gate Stack Passivation.
Evgueni Chagarov 1 , Andrew Kummel 1
1 Chemistry Department, UCSD, La Jolla, California, United States
Show AbstractDensity Functional Theory Molecular Dynamics (DFT-MD) calculations were performed to compare the atomic basis of passivation of the a-ZrO2/Ge(100) and a-HfO2/Ge(100) gate oxide interface by GeO2, GeON, and GeN. Recent results from several groups have shown that reasonable p-MOSFETs can be fabricated with a-ZrO2/GeO2/Ge(100) or ZrO2/GeON/Ge(100) gate stacks in which GeO2 or GeON passivation layers greatly improve the C-V characteristics. DFT-MD was used to first simulate the formation of the a-GeO2, a-GeON, and a-GeN layers by placing 2 monolayer (2ML) O and N atoms on the Ge(100) surface and, subsequently, annealing at 700K, cooling, and relaxing the passivated surface. An amorphous ZrO2 (or a-HfO2) slab was placed on top of the GeO2/Ge(100) stack, annealed at 700K, cooled, and relaxed. All three passivation layers reduce the density of midgap states in the oxide/Ge slab, but the GeO2 produces the lowest density of midgap states while GeON produce the lowest interfacial dipole. In the unpassivated ZrO2/Ge(100) or a-HfO2/Ge(100), Ge makes bonds to O and Zr/Hf. However, in the GeO, GeON, and GeN passivated stacks, the Ge-Zr/Hf bonds have been eliminated. The removal of Ge-Zr/Hf bonds correlates with an improvement in the electronic structure. It is known that N improves the diffusion resistant of the interface to Ge incorporation into the oxide so there is a tradeoff between oxygen and nitrogen content in the passivation layer. This will be tested in future work to guide further improvement in the passivation of high-k/Ge gate stacks.
9:00 PM - I5.28
X-ray Studies of Strain Patterns in Strained Si on Insulator.
Matthew Bibee 1 2 , Apurva Mehta 2 , Piero Pianetta 1 , Sean Brennan 2
1 Applied Physics, Stanford University, Stanford, California, United States, 2 , Stanford Synchrotron Radiation Laboratory, Menlo Park, California, United States
Show AbstractWe present an examination of the detailed strain state of strained Si on insulator (sSOI). sSOI is a promising substrate for future generations of CMOS technology in which a thin (10-100nm) surface layer of biaxially strained Si allows improved transistor performance through increased carrier mobility, while an underlying SiO2 layer provides electrical insulation. We used synchrotron x-ray reflectivity measurements to characterize layer thickness, density, and roughness, and high resolution x-ray diffraction to examine amount and uniformity of strain in sSOI wafers. These measurements suggest that the wafers exhibit small spatial non-uniformities in strain, likely in the form of nanometer-scale strain gradients. High temperature (1000-1200°C) annealing studies were performed on the wafers to explore the relationship between the strain state and relaxation behavior of the strained Si layer. By improving our understanding of the initial strain state of SOI and its alteration during annealing, we hope to provide insights into the mechanisms of strain relaxation and defect formation in sSOI.
9:00 PM - I5.4
TEM Analysis of Amorphous Layers Created by Ge Self Implantation.
Blake Darby 1 , Brad Yates 1 , Kevin Jones 1
1 Materials Science and Engineering, University of Florida, Gainesville, Florida, United States
Show AbstractRecently, Ge has received renewed interest as an alternate channel material in complementary metal oxide semiconductor devices. Ge has notably different amorphization kinetics than Si due to a lower melting point and bond strength. Upon ion implantation, Si is known to exhibit a lower threshold damage density at reduced temperatures. Unlike Ge, Relatively minor variations (30°C) below room temperature can produce significant increases in amorphization depths in Si. For this study, (100) Ge wafers were self implanted at 20 keV at both 173°K and 293°K with doses varying between 1E13 Ge/cm2 and 2E15 Ge/cm2. Cross sectional transmission electron microscopy was used to measure both the amorphous layer thickness and crystalline amorphous interface roughness. For both implant temperatures, partial amorphization was observed at 2E13 Ge/cm2 and continuous amorphization at 5E13 Ge/cm2. The amorphous depths in this temperature range differed by less than 2nm. Results show that it is possible to reduce the crystalline amorphous interface roughness by increasing the dose and lowering the implant temperature; however, increasing the dose also increases surface roughness as confirmed by AFM. Further work needs to be completed to determine the optimal dose to ensure minimal interfacial and surface roughness.
9:00 PM - I5.5
Investigation of Wet Etch of Sub-nm LaOx Capping Layers for CMOS Applications.
Mo Jahanbani 1 , Hui-feng Li 1 , Tat Ngai 2 , Joel Barnett 3 , Martin Rodgers 1 , Steve Benette 1 , Daniel Franca 1 , Corbet Johnson 1 , Steven Gausepohl 1 , Joseph Piccirillo 1 , Bill Taylor 2
1 College of Nanoscale Science and Engineering, SUNY AT ALBANY, Albany, New York, United States, 2 , SEMATECH, Albany, New York, United States, 3 , SEMATECH, Austin, Texas, United States
Show AbstractWith the Si CMOS devices continued scale down to sub-40nm region, high permittivity gate dielectric and metal gate stacks have begun to replace the traditional SiO2 gate oxide and poly Si gate. The introduction of high k gate dielectric and metal gate stack raised new challenges in modulating MOSFET threshold voltage. LaOx cap layer has been shown to be a promising candidate for work function tuning to reduce the NFET threshold voltage in low standby power CMOS devices. During the processing, high k gate dielectrics at PFET area needs to be protected from LaOx deposition and only high k gate dielectrics at NFET area is exposed to LaOx deposition. After LaOx diffused into high k at NFET area, LaOx on top of PFET needs to be etched in the subsequent processing. The etch requires to remove the LaOx and underneath mask at PFET and keep the high k gate dielectrics on NFET active area undamaged. This poses a big challenge to the choice of the etch process. The underneath mask also had an impact on the subsequent LaOx etch. In this paper we investigated wet etch of LaOx using amorphous and TiN as the underneath blocking layer. TiN is a more suitable mask candidate than amorphous Si for LaOx etch. XPS showed LaOx diffused into amorphous Si and made the subsequent a-Si etch difficult.
9:00 PM - I5.6
Metrology for Extracting Work Functions of Ta-C-N Metal Gate Electrodes for the Advanced Gate Stack Using Combinatorial Methodology.
Kao-Shuo Chang 1 2 , Martin Green 1 , Peter Schenck 1 , Ichiro Takeuchi 2 , Cherno Jaye 3 , Daniel Fischer 1 3 , Sven Van Elschocht 4
1 Materials Science and Engineering, NIST, Gaithersburg, Maryland, United States, 2 , U of Maryland, College Park, Maryland, United States, 3 , Brookhaven National Lab, Upton, New York, United States, 4 , IMEC, Leuven Belgium
Show AbstractContinued Moore’s Law scaling of integrated circuit devices has given rise to gate stack problems such as high leakage current density (JL) in SiO2 dielectrics, and depletion in polycrystalline silicon (poly-Si) metal gates. Thus, there has been much research on advanced materials to replace SiO2 and poly-Si. The goal of this research is to join the thin film deposition techniques of radio frequency (RF) sputtering with combinatorial methodology to rapidly, systematically, and reliably explore metal gate electrodes. Combinatorial methodology enables efficient generation of a comprehensive and uniform set of samples, and allows rapid screening as well. In an approach to finding a novel metal gate material, Ta-C-N films draw attention because they possess several attractive properties, such as tunable work function (Φm), high conductivity, high thermal stability, and chemical inertness. We are trying to establish a reliable metrology to extract Φm for Ta-C-N on HfO2/SiO2 dielectric stacks. In an attempt to minimize experimental variation from run to run, we deposit metal gate combinatorial film libraries on top of a 3nm HfO2 film, which is on top of a SiO2 film of continuously varying thickness. This allows us to systematically extract Φm of metal gates from a single combinatorial library sample. An optimal forming gas annealing (FGA) condition was identified for the gate stack to reduce the interface state density (Dit). We have demonstrated the effectiveness of our strategy by extracting Φm (~ 4.3 eV) of TaN, consistent with the literature values. The stability of the gate stacks under different thermal budgets (FGA, 900 °C, and 1000 °C rapid thermal anneals (RTAs)) was studied using high resolution transmission electron microscopy (HRTEM), which reveals the Ta-C-N/HfO2/SiO2/Si gate stack a good thermal stability up to 950 °C. Ta-C-N metal gate measurements have been made, and Φm is found to be ~ 5 eV after 900 °C RTA.
9:00 PM - I5.7
Comparison of Pt and SrRuO3 Electrodes for SrTiO3 Thin Film Capacitors on Silicon Substrates.
Sebastian Schmelzer 1 , Dennis Braeuhaus 1 , Ulrich Boettger 1 , Susanne Hoffmann-Eifert 2 , Paul Meuffels 2 , Rainer Waser 1 2
1 Institute for Materials in Electrical Engineering and Information Technology, RWTH Aachen University of Technology, Aachen Germany, 2 IFF, Institute of Electronic Materials, Research Center Jülich, Jülich Germany
Show AbstractFollowing the ITRS, near future DRAM cell capacitors necessitate dielectric materials with a relative permittivity considerably higher than 50. Dielectric materials as Al2O3, HfO2 or Ta2O5 then run into limitations due to their moderate permittivity values. These facts make SrTiO3 (STO) with its bulk permittivity of more than 300 to one of the most promising candidates for future applications. Another important limitation is the leakage current density, which should be in the range of 10-7 A/cm2 to meet the demand for DRAM applications. The mechanisms limiting the current in these materials are not completely understood yet, but are certainly linked up with the electrode material.In this work, we compare the properties of STO thin film capacitors with either Pt or SrRuO3 (SRO) electrodes. We used oxidized silicon substrates for the SRO-STO-SRO capacitors and an additional ZrO2 adhesion layer for the Pt-STO-Pt capacitors. The films were prepared by RF sputtering in a self-built PVD vacuum chamber equipped with a 1” multi sputter gun. With this equipment we are able to deposit layer sequences of up to three different materials without breaking the vacuum condition. The deposition was performed in pure argon atmosphere at a process pressure of about 10-2 mbar and at a substrate temperature of 550°C. The quite low deposition rates of 0.1-2 nm/min enabled the reproducible fabrication of capacitors with a STO thickness of 40 nm down to below 10 nm. After patterning the top electrode layer, we used various capacitor areas for the electrical characterization.The roughness of the sample surface we investigated by atomic force microscopy (AFM). On the one hand, we were able to produce SRO electrodes with a very low RMS (root mean square) roughness value of about 0.2 nm. On the other hand, the Pt electrodes showed a significantly higher roughness in the range of 1 nm RMS. To determine the relative permittivity value of the STO films, we performed C-V measurements using a HP 4284 A LCR meter. The dependence of the permittivity on the applied electric field was characteristic as it is well-known for STO since the 1960s. The peak values exceed 200 for several samples with SRO electrodes even at a STO thickness of down to 10 nm. The samples with Pt electrodes showed lower permittivity values, which we suppose to be caused by the higher electrode roughness that acts like an interfacial passive layer, as it is described in literature. With SRO electrodes, we were able to obtain a leakage current density in the range of 10-7 A/cm2 at an applied electric field of 500 kV/cm and a STO film thickness of about 10 nm. The leakage current decreased for increasing STO film thickness and vice versa. The samples with Pt electrodes showed the same overall behavior, but at a higher level and culminated in short-circuited capacitors even at 15 nm STO film thickness.
9:00 PM - I5.8
Profiling Different Kind of Generated Defects at Elevated Temperatures in Both SiO2 and High-k Dielectrics.
Sahar Sahhaf 1 2 , Robin Degraeve 1 , Mohammed Zahid 1 , Guido Groeseneken 1 2
1 , imec, Leuven Belgium, 2 ESAT, KULeuven, Leuven Belgium
Show AbstractDue to internal heating, the operating temperature of advanced CMOS technology is considerably higher than ambient room temperature. Several stress-induced degradation phenomena, that limit the circuit reliability, are accelerated as compared to room temperature. Understanding these thermally stimulated degradation mechanisms, is generally accepted as a critical issue in reliability projections. We characterize the generated defects at elevated temperatures in a 6 nm layer SiO2 and also in a selected high-k dielectric stack i.e. 1/3 nm SiO2/HfSiO (EOT= 1.6 nm) which is a promising replacement for leaky SiO2 in DRAM peripheral transistors. In order to study the energy spectrum of the defects generated during stresses at 75°C and 200°C, two techniques are applied: for the thin high k layer, the energy spectrum is obtained by plotting the ratio of the change in leakage current to the initial tunnel current as a relative metric for defect generation. The peaks in the resulted SILC spectrum are attributed to different energetically distributed defects. At low temperatures, the generation of energetically deep traps is dominant while at high temperatures, more energetically shallow traps participate in the leakage current and the breakdown process.In thick SiO2 layers, the SILC spectroscopy technique cannot reveal the true energy profile of defects due to the following reasons: 1) the underlying mechanism of the leakage current at high gate voltages (Fowler-Nordheim tunneling) differs from the initial tunnel current and therefore their ratio has no physical meaning. 2) At low voltages, the energetically shallow traps are not accessible resulting in incomplete defect scanning.In order to have detailed information on the trap density profile and trap energy level in 6 nm SiO2, we use the recently developed Trap Spectroscopy by Charge Injection and Sensing (TSCIS) which relies on a controlled charging of defects by direct tunneling as a function of charging time (tcharge) and charging voltage (Vcharge). Also in this case we identify more energetically deep traps generated at low temperatures while at high temperatures, homogeneously distributed defects in a wide energy range are observed. The identified differences between the defects generated at low and high temperatures are more pronounced in the high-k stack. Consequently, the simple Arrhenius law cannot be used to extrapolate Time-Dependent Dielectric Breakdown (TDDB) data from high to low temperature or vice versa in materials used for End-of-Roadmap Scaling of CMOS Devices.
9:00 PM - I5.9
Electrical Characteristics of Crystalline Gd2O3 Film on Si (111): Impacts of Growth Temperature and Post Deposition Annealing.
Gang Niu 1 , Bertrand Vilquin 1 , Nicolas Baboux 2 , Guillaume Saint-Girons 1 , Carole Plossu 2 , Guy Hollinger 1
1 , INL-ECL, Ecully, Rhone-Alpes, France, 2 , INL-INSA, Lyon France
Show AbstractThe continuous scaling of the gate dielectric thickness requires high-k metal oxide as an alternative to SiO2 for future CMOS (Complementary Metal Oxide Semiconductor) technology. Recently, the epitaxy of crystalline oxides on silicon attracted intensive researches due to their epitaxial nature that potentially results in an interface without (or with a very few) dangling bonds, which could lead to a low interface trap density and consequently, to a high carrier mobility. Gadolinium oxide (Gd2O3) is identified as one of the most promising candidates because of its i) high dielectric constant of 20, ii) high bandgap of 5.3eV, iii) thermodynamical stability on silicon even at high temperature, and iv) very small lattice mismatch(only 0.44%) with Si (one Gd2O3 unit cell on two Si unit cells). Gottlob et al. reported for the first time a fully functional n-MOSFET with a TiN/Gd2O3/Si (001) system1. At the same time, the reliability and stability of the Gd2O3 dielectric still remains acute and requires further investigations.In the present work, we demonstrate a good quality epitaxial single domain Gd2O3 film on p-type Si (111) substrate with an abrupt interface. The choice of Si (111) is based on two reasons: i) Gd2O3 is mono-domain on Si(111) while it exhibits bi-domain structure on Si (001) surface and ii) Gd2O3/Si (111) could be used as a template to integrate ferroelectric or multiferroic materials with hexagonal structure (for example YMnO3) on silicon. The crystallographic characterization of the Gd2O3 film was investigated by X-ray Diffraction (XRD) and Transmission Electron Microscopy (TEM). We have studied the impact of growth temperature on the electrical properties of Gd2O3 by performing electrical measurements on an Au/Ni/Gd2O3/Si MOS structure. The Equivalent Oxide Thickness (EOT) values were extracted by fitting the experimental capacitance-voltage data with realistic quantum simulations. We find that the sample grown at 700°C shows the smallest EOT ~0.7nm with a leakage current 3.6×10-2A/cm2 at |Vg-VFB|=1V, which is in good agreement with the recommendation of International Technology Roadmap for Semiconductors (ITRS) for the 32nm node. However, for the as-deposited sample grown at optimal conditions (700°C), the positive flatband voltage VFB shift with respect to theoretical value reveals the existence of negative charges in the bulk dielectric. To address this problem, we have performed Post Deposition Annealing (PDA) in different conditions, including a 200°C PDA in a tubular furnace and a 400°C Rapid Thermal Annealing (RTA) under oxygen or nitrogen atmosphere. The PDA could effectively reduce the VFB while affects EOT very slightly. Furthermore, the samples demonstrate relative good stability of electrical properties when undergone the annealing treatments. [1] H.D.B. Gottlob et al., Solid-State Electron. 50 (2006) 979–985.
Symposium Organizers
Andrew C. Kummel University of California-San Diego
Heiji Watanabe Osaka University
Iain Thayne University of Glasgow
Prashant Majhi SEMATECH/Intel
I6: III-V MOSFET
Session Chairs
Friday AM, April 09, 2010
Room 2012 (Moscone West)
9:00 AM - I6.1
Atomic Mechanism of Flat-band Voltage Shifts by La, Sr, Al, Nb and V Induced Dipole Layers.
Liang Lin 1 , John Robertson 1
1 Electrical Engineering Department, University of Cambridge, Cambridge United Kingdom
Show AbstractIn high-K metal gate CMOS technology, the metal oxide 'capping layer' is often used to shift threshold voltages towards zero, e.g. La2O3 for NMOS and Al2O3 for PMOS. The shift effect is reported to correlate with dipole that occurs at the lower high-K: SiO2 interface, rather than with Fermi level unpinning at the upper gate: high- K interface [1]. However, the cause of the dipole is still contentious. It has been attributed to oxygen vacancies, bond dipoles, group electro-negativities, or to oxygen ion density, but only by empirical models. In order to understand the mechanism at an atomic level, we built a supercell containing HfO2:SiO2 interfaces, then substitute atoms such as La, Al, Sr, Nb and V at Hf or Si sites, with oxygen vacancies or interstitials where needed for charge balance. The supercells were relaxed using CASTEP total energy package. Electronic structures were calculated and the valence band offsets (VBO) were derived from the local density of states of HfO2 and SiO2 well away from the interface. According to formation energy comparison, capping layers atoms are attracted to the lower high-K: SiO2 interface due to silicate formation. La and Sr dopants at the interface shift VBO in the opposite direction than Al, Nb and V, as seen experimentally. The shift correlates with the metal electronegativity, but it does not correlate with the metal valency or oxygen ion density. We found that interfacial sites cause the shift not bulk sites. This is because bulk dipoles cancel on average, whereas interfacial dipoles do not due to the different local screening constants.[1] Y Yamamoto, K Kita, K Kyuno, A Toriumi, Jpn J App Phys 46 7251 (2007)
9:15 AM - I6.2
Density Functional Theory Simulations of Amorphous High-k Oxides on a Compound Semiconductor Alloy: a-Al2O3/InGaAs(4x2)(100), a-HfO2/InGaAs(4x2)(100), a-HfO2/OH/InGaAs(4x2)(100) and a-ZrO2/InGaAs(4x2)(100).
Evgueni Chagarov 1 , Andrew Kummel 1
1 Chemistry Department, UCSD, La Jolla, California, United States
Show AbstractThe structural properties of a-Al2O3/In0.5Ga0.5As, a-ZrO2/In0.5Ga0.5As, a-HfO2/In0.5Ga0.5As and a-HfO2/OH/In0.5Ga0.5As interfaces were investigated by density-functional theory (DFT) molecular dynamics (MD) simulations. Realistic amorphous a-Al2O3,a-HfO2 and a-ZrO2 samples were generated using a hybrid classical-DFT MD “melt-and-quench” approach. The amorphous oxide samples were placed on the group III-rich InGaAs(100)-4x2 surface and annealed at 700K-1100K with DFT-MD to investigate bond formation and dangling bond passivation using the realistic atomic interaction provided by DFT modeling along the atomic motion provided by molecular dynamics. For all the oxides, bonding of the oxide to the semiconductor can result in intermixing and electronic pinning. However, gentle processing can result in oxide/InGaAs interfaces which do not intermix since there is no thermodynamic driving force for intermixing. For favorable oxide/semiconductor bonding, the a-Al2O3/InGaAs and a-HfO2/OH/InGaAs interfaces demonstrated unpinned Fermi level and low interface intermixing. The unpinned interfaces are formed when annealing of the interfaces generally results in formation of M-As (M=Al, Hf, or Zr), O-In/Ga bonds and removal of In,Ga, and As dangling bonds. Pinning results mainly from substrate group III atoms being pulled into the oxide or oxide metal atoms being pulled into the substrate during interface bond formation. Experimentally, the key to forming these interfaces will be using oxide deposition techniques which do not displace surface atoms while forming M-As and O-In/Ga bonds. The presented DFT MD simulations demonstrated strong correlation to experimental measurements.
9:30 AM - I6.3
GaAs Surface Self-cleaning Effect Using Dimethylaluminumhydride.
Hong-Liang Lu 1 , Xiao-Liang Wang 2 , Masakazu Sugiyama 1 3 , Yukihiro Shimogaki 2
1 Department of Electronic Engineering, The university of Tokyo, Tokyo Japan, 2 Department of Materials Engineering, The University of Tokyo, Tokyo Japan, 3 Institute of Engineering Innovation, The University of Tokyo, Tokyo Japan
Show AbstractCompound semiconductors such as GaAs and other III-V materials have the potential to replace silicon as the channel material in metal-oxide-semiconductor field-effect transistors (MOSFETs) due to their high electron mobility. However, for the successful realization of GaAs-based MOSFETs, there are still a number of fundamental issues to be solved. A key challenge is the development of a high-quality and thermodynamically stable insulator on GaAs with a low density of interfacial trap states (Dit) or a good interfacial layer comparable to that of SiO2/Si interface. The high Dit associated with dielectric/GaAs interface causes Fermi level pinning at midgap which inhibits formation of accumulation or inversion layers. The removal of surface species such as As-O bonds, Ga-O bonds, elemental As, and As and Ga antisites has been shown to be critical for unpinning the Fermi level. It is also demonstrated a self-cleaning effect on the reduction and removal of surface oxides from GaAs or InGaAs substrate by ALD of Al2O3 using trimethylaluminum (TMA). Such a self-cleaning phenomenon is found to be affected by oxidation state as well as metal organic precursor. Recently, we have developed Al2O3 deposition using dimethylaluminumhydride [(CH3)2AlH, DMAH] and oxygen. The DMAH replaces a methyl group in TMA with H and may provide stronger surface self-cleaning reaction in the growth of Al2O3 on GaAs. In the present work, the variation of amount of native oxides on GaAs surface as a function of DMAH exposure time is investigated by X-ray photoelectron spectroscopy (XPS). The self-cleaning of GaAs surface, which is oxidation of DMAH on the surface, is responsible for the observed reduction of native oxides. It is shown that higher oxide states are more easily eliminated from the GaAs surface. In addition, Ga oxides are found to have lower ligand-exchange reactivity with DMAH than As oxides, leading to preferential reduction of As oxides than Ga oxides. After exposure to DMAH for 10 s, the HCl-treated GaAs surface is free of any native oxides. Nevertheless, the residual elemental As can not be eliminated. The metallic Al formation upon exposure to excessive amount of DMAH supports that only oxygen in the native oxides reacts with DMAH.
9:45 AM - I6.4
Thermal Stability, Band Offsets, Bonding and Interface States of GaAs:HfO2 Interface.
Weichao Wang 1 , Ka Xiong 1 , Geunsik Lee 2 , Min Huang 2 , Robert Wallace 1 2 , Kyeongjae Cho 1 2
1 Materials Science and enginering, Multiscale simulation lab, Richardson, Texas, United States, 2 Department of Physics, Multiscale Simulation Lab, Richardson, Texas, United States
Show AbstractAs the downscaling of complementary metal oxide semiconductor (CMOS) transistors continues, III-V compound semiconductors have been investigated as promising n-type MOS field effect transistor channel material due to its higher bulk electron mobility and higher breakdown voltage compared to Si [1-2]. However, integrating III-V materials into surface channel MOS devices has been a challenging problem as the interface quality between the channel and the gate oxide is rather poor leading to many problems such as frequency dispersion of capacitance, low electron mobility, and instability of device operations. This challenge has led to considerable work on understanding the nature of these native oxides and hence controlling their formation by engineering the interface chemistry [3-5].In this work, a theoretical study of the structural and electronic properties of GaAs:HfO2 interface is reported. We found a Ga-O bonding interface with two oxygen vacancies is the most stable interface due to its low formation energy compared to other Ga-O bonding interface structures. With gradually decreasing the interfacial O content from 100% to 30%, we found that valence band offsets can be increased up to 2 eV. Further analysis on the electronic structures indicates that interface gap states originate from interfacial Ga dangling bonds and a strong electron affinity competition between interfacial As and O. Our calculated results show that the reduction of the Ga oxidation state is helpful to suppress the interface states, consistent with the experimental results.This work was supported by FUSION/COSAR project.Reference1.M. W. Hong, J. Kwo, A. R. Kortan, J. P. Mannaerts, and A. M. Sergent, Science 283, 1897 (1999)2.M. Passlack, M. Hong, and J. P. Mannaerts, Appl. Phys. Lett. 68, 1099 (1996).3.M. J. Hale, S. I. Yi, J. Z. Sexton, and A. C. Kummel, J. Chem. Phys. 119, 6719 (2003).4.C. L. Hinkle, A. M. Sonnet, E. M. Vogel, S. McDonnell, G. J. Hughes, M. Milojevic, B. Lee, F. S. Aguirre-Tostado, K. J. Choi, H. C. Kim, J. Kim, and R. M. Wallace, Appl. Phys. Lett. 92, 071901 (2008).5. C. L. Hinkle, A. M. Sonnet, M. Milojevic, F. S. Aguirre-Tostado, H. C. Kim, J. Kim, R. M. Wallace, and E. M. Vogel, Appl. Phys. Lett. 93, 113506 (2008).
10:00 AM - **I6.5
Germanium Integration on Silicon for High Performance MOSFETs and Optical Interconnects.
Krishna Saraswat 1
1 Electrical Engineering, Stanford University, Stanford, California, United States
Show AbstractSi CMOS technology has dominated the microelectronics industry, with continued scaling. However, future Si CMOS scaling is reaching practical and fundamental limits. To go beyond these limits on Si based devices, novel materials and structures are being aggressively studied. Ge shows much promise as an alternative to Si for both electronic and optical devices. Its high carrier mobility has the promise to provide better performance in MOSFETs. Replacement of Si channel by Ge requires several critical issues to be solved, including high quality gate dielectric for surface passivation. Direct formation of a high-k dielectric on Ge has not given good results in the past. Ge oxidation by ozone or oxygen plasma to grow GeO2 provides a good quality interface layer before the deposition of a high-K dielectric. Electrical and physical characterizations and stability analysis demonstrates high quality Ge/insulator interface with low interface trap density. Ge PMOS have been shown to have better performance than Si PMOS with this technique. In the past Ge NMOS showed poor performance, however, recently high electron inversion mobility has been demonstrated by careful engineering of the gate dielectric.The scaling paradigm is also threatened by interconnect limits including excessive power dissipation, insufficient bandwidth, and signal latency for both off-chip and on-chip applications. Many of these obstacles stem from the physical limitation of Cu-based electrical wires, exacerbated by the increase in Cu resistivity, as wire dimensions and grain size become comparable to the bulk mean free path of electrons in Cu (~40nm). Therefore for the interconnect technology, the idea of bringing high speed optical signals directly to CMOS chips offers opportunities for using photons to aid electrical functions in novel ways. Ge’s small direct bandgap of 0.8 eV allows Ge photodetectors, optical modulators and recently light emitters to operate in the low-loss optical fiber range of about 1.3 to 1.55 μm and makes it a strong candidate for optical interconnect applications. However, Si technology enjoys decades of capital investment and offers advanced fabrication ability. Furthermore, Ge substrate is not easy to handle and is not easily available. Therefore to utilize above mentioned advantages of Ge its it is imperative to develop technology for heterogeneous integration of Ge on Si-based platform. It is crucial to be able to grow high quality Ge layers selectively. Ge has large (4.2%) lattice mismatch with Si, which causes strain to Ge layers grown directly on Si which results in high density of dislocations and rough surface. Selective growth of Ge on Si through a thermally grown SiO2 window has been demonstrated by Multiple Hydrogen Annealing for Heteroepitaxy (MHAH) technique. The selective growth mechanism combined with hydrogen annealing steps yields high quality Ge on Si. This technique yields Ge layers with very low dislocation density and surface roughness. In-situ doping allows very abrupt p-n junctions. Fabrication of high performance MOSFETs and optical devices in MHAH Ge on Si has demonstrated future promise of continued scaling.
10:30 AM - I6.6
Analysis of Interface Trap Densities for ZrO2 Gate Dielectrics Grown on In0.53Ga0.47As Channels.
Yoontae Hwang 1 , Roman Engel-Herbert 1 , Jeff Huang 2 , Niti Goel 2 , Susanne Stemmer 1
1 Materials Department, University of California, Santa Barbara, Santa Barbara, California, United States, 2 , Sematech, Austin, Texas, United States
Show AbstractA serious roadblock in utilizing III-V compound semiconductors as channel materials for metal-oxide-semiconductor field effect transistors is finding a high-k dielectric that allows for interfaces with low trap densities, as required for Fermi level unpinning. Although several deposition methods and interface passivation schemes promise high-quality interfaces, only relatively few studies report a quantitative characterization of interface trap densities for III-V/high-k interfaces. In this presentation, we compare the interface trap densities obtained from two different methods, the conductance and the Terman method, for ZrO2/In0.53Ga0.47As interfaces.ZrO2 was deposited in ultra high vacuum on (2×4) reconstructed InGaAs surfaces by molecular beam deposition using a chemical precursor, zirconium tert-butoxide (ZTB) [1]. Capacitance-voltage (CV) and conductance-voltage (GV) curves were measured at frequencies from 100 Hz to 1 MHz and temperatures from 150 to 300 K on both n- and p-type doped In0.53Ga0.47As. The parallel conductance data taken at 300 K reveals a trap level located approximately 0.47 eV above the valence band edge, resulting in an interface trap density larger than 1×1013 cm-2eV-1. The absence of a shift in parallel conductance peak with frequency indicates that this trap level pins the Fermi level near midgap. The trap level position is consistent with a maximum band bending of -0.26 eV as determined from the Terman method. Interface trap densities determined from n-type samples by the Terman method give values ranging from 5×1013 cm-2eV-1 at the conduction band edge to 1×1014 cm-2eV-1 close to the trap level near midgap, overestimating the interface trap density by one order of magnitude compared to the conductance method. Further indication that the Terman method overestimates the interface trap densities comes from low temperature conductance measurements, which indicated trap densities of less than 1×1012 cm-2eV-1 near the conduction band edge. Room temperature conductance measurements on p-type In0.53Ga0.47As showed interface traps located between 0.3 eV and 0.4 eV above the valence band edge with densities ranging between 2×1012 cm-2eV-1 and 3×1013 cm-2eV-1. Furthermore, the large frequency dispersion of CV curves measured on p-type samples at negative gate bias indicates high interface trap densities close to the valence band edge. We will discuss the reasons for the limitations of the Terman method. The results showed that the upturn in capacitance with frequency commonly reported for negative biases for n-type channels is not true inversion but rather due to interface trap response. The results will be discussed in the context of commonly employed qualitative criteria used for the assessment of the quality of these interfaces, such as work function sensitivity of the flat band voltage and CV frequency dispersion. [1] R. Engel-Herbert, Y. Hwang, J. Cagnon, S. Stemmer, Appl. Phys. Lett. 95, 062908 (2009).
10:45 AM - I6.7
Molecular Beam Deposition of a-Al2O3 and a-Si Passivating Layers for In0.17Ga0.83As Field Effect Transistors.
Chiara Marchiori 1 , D. Webb 1 , C. Rossel 1 , C. Gerl 1 , M. Sousa 1 , M. Richter 1 , H. Siegwart 1 , D. Caimi 1 , E. Kiewra 2 , T. Smet 3 , J. Locquet 3
1 , IBM Research-Zurich, Rueschlikon Switzerland, 2 , IBM Watson Research Center - Yorktown, Yorktown Heights, New York, United States, 3 , Katholieke Universiteit Leuven, Leuven Belgium
Show AbstractTo fabricate inversion mode surface channel devices, unpinned, high quality III-V/dielectric interfaces are necessary. This requires (1) the III-V surface to be clean, ordered and highly stoichiometric and (2) any passivating interlayer (IL) to minimize the amount of interface defects while avoiding substrate oxidation. For instance, the Al2O3/InGaAs interface is predicted by molecular dynamics simulations to have a minimum amount of intermix and low interface polarity. In addition, thanks to the “clean up process”, which takes place during atomic layer deposition of a-Al2O3, very clean and abrupt interfaces are obtained. However, from the scalability point of view, higher dielectric constant oxides such as HfO2 may be on the long term more promising. In this contribution we will discuss both approaches. First, we investigate a novel method based on the molecular beam deposition (MBD) of a-Al2O3 from an Al2O3 e-beam source which does not require any additional O supply. In order to address the two requirements listed above, un-doped, strained In0.17Ga0.83As layers are grown on GaAs (001) in a dedicate III-V MBE chamber and passivated with a-Al2O3 after UHV transfer to an oxide MBD chamber. The obtained gate stacks are characterized by in-situ XPS, XRR, and ellipsometry and processed in MOS capacitors and n-FETs. Then, this approach is benchmarked against another promising method which consists of passivating the freshly grown In0.17Ga0.83As surface by mean of a thin, amorphous MBD Si layer. In this case, scalability issues are better addressed by using HfO2 as gate dielectric due to its higher dielectric constant.We will show that even though 2nm Al2O3 are an effective barrier against atomic O diffusion, InGaAs oxidation with the formation of AsOx and InOx species can not be avoided during the deposition of the first Al2O3 nanometers at temperature as low as 250C. In agreement, FETs are characterized by very low drive current and split CVs point to strongly pinned interfaces. On the contrary, a thin a-Si IL acts as effective barrier against In0.17Ga0.83As oxidation during gate stack deposition, enabling the fabrication of working FETs. We will discuss how the presence of this a-Si IL introduces constraints on the gate-first FET processing. For instance, the best activation-anneal thermal budget is the result of a trade off between lowering access resistance (high T) and minimizing Si diffusion (low T) with consequent doping of the III-V channel. Electrical properties of ring FETs with 200nm Pt/7nm HfO2/1.5nm Si-SiO2 gate stack, 5-10-15 μm channel lengths will be presented. Typically, 5 μm ring-FETs are characterized by ID = 2.5 μA/μm at VGS = 2.5 V and VDS = 0.1 V (with RDS correction), Vt = 0.7 V, subthreshold slope 90-107 mV/dec, Ion/Ioff = 106, and gate leakage 10-11 A.Finally, possible methods to improve structural quality and electrical properties of the full gate stack will be discussed.
11:15 AM - I6.8
Effect of Surface Composition on Electrical Performance of InGaAs(100).
Babak Imangholi 1 , Fee Li Lie 1 , Willy Rachmady 2 , Anthony Muscat 1
1 Chemical and Environmental Engineering, University of Arizona, Tucson, Arizona, United States, 2 , Intel Corporation, Hillsboro, Oregon, United States
Show AbstractAtomic layer deposition (ALD) processes have been shown to passivate and auto-clean III-V surfaces, depending on the precursor, deposition conditions, and pre-treatment. In this project, the passivation of InGaAs(100) interfaces by a combination of aqueous HF treatment and ALD Al2O3 was studied. The Al2O3/InGaAs interface composition was obtained by x-ray photoelectron spectroscopy (XPS) and related to the surface recombination velocity (SRV) obtained by C-V curves and large AC signal conductance measurements. The effect of forming gas annealing (FGA) and NH3 annealing on the quality of the interface was also investigated. InGaAs(100) surfaces were prepared initially by solvent cleaning and aqueous HF etching. ALD Al2O3 was conducted at 170°C with trimethylaluminum (TMA) and water precursors. XPS characterization was done in situ after ALD of 1.5 nm of Al2O3 in order to accommodate the shallow depth of XPS analysis. In situ analysis is crucial to prevent uncontrolled oxidation of the InGaAs interface in ambient air. Al2O3/InGaAs prepared by solvent cleaning showed thinning of the native oxide due to TMA reacting with surface moieties. Complete removal of native oxides was not achieved, since interfacial reactions stopped once a critical thickness of Al2O3 formed. Similar characterization performed on Al2O3/InGaAs prepared by liquid phase HF etching showed complete removal of In and Ga oxides, but approximately a monolayer of As oxide remained. The large AC signal characterization on Al2O3/InGaAs containing residual native oxides showed peaks corresponding to both low and high activity defects at the interface. Low activity defects are related to vacancies in the dielectric oxide, while high activity defects are related to semiconductor surface states. Interface defects with residual native oxides yielded a SRV of ~35 cm/s. In contrast, only low activity defects were observed on Al2O3/InGaAs prepared by liquid phase HF, which resulted in a SRV of ~1 cm/s. HF treated samples also showed improved frequency dispersion in C-V curves compared to samples with native oxide. Since defects were only associated with the dielectric oxide, FGA did not affect the height and position of conductance peaks, and consequently SRV, on HF treated samples. However, NH3 annealing drastically reduced and shifted the position of the peak associated with low activity defects in HF-treated samples. Since Al2O3 has primarily ionic character, it was expected that NH3 annealing would passivate the vacancies in the oxide. In addition to the improvement in the low activity defect peak, NH3 annealing on the native oxide samples reduced the peak associated with high activity defects; this could be the result of hydrogen passivation due to H2 produced by NH3 decomposition. These results agree with measurements previously reported on C-V dispersion at low frequencies (<100KHZ) caused by defects in the oxide layer on n-type semiconductors.
11:30 AM - **I6.9
Electrical Properties of InGaAs/High-k Oxide Interfaces: Measurement and Simulation.
Guy Brammertz 1 , Han-Chung Lin 1 , Ali-Reza Alian 1 , Clement Merckling 1 , Marc Chang 1 , Wei-E Wang 1 , Matthias Passlack 2 , Matty Caymax 1 , Marc Meuris 1 , Marc Heyns 1
1 SPDT/EPI, IMEC vzw, Leuven Belgium, 2 Advanced Transistor Research Division - Belgium Branch, TSMC, Leuven Belgium
Show AbstractFor performance scaling beyond the 16 nm node, high mobility materials such as Ge and III-V materials are being investigated as replacement for Si as MOSFET channel material. InGaAs with high In content has emerged as a material that attracts a lot of interest. In this contribution, we investigate the electrical interface properties of In0.53GA0.47As in detail. We present electrical measurements on In0.53Ga0.47As MOS structures with different high-k oxides, surface treatments and post deposition anneals. Both AC conductance measurements and quasi-static CV measurements are performed. The measurement results are compared to calculations of the electrostatic behavior of the system in order to derive the interface state density both inside the bandgap as well as in the lower part of the conduction band. The comparison between model and experiment allows deriving an interface state distribution that has its charge neutrality level at the conduction band edge energy. Inside the bandgap mainly donor-like interface states can be measured, with a relatively low density close to the conduction band edge energy, and a strongly rising density in the lower part of the bandgap. In addition to the donor-like interface states inside the bandgap, also acceptor-like interface states in the lower part of the conduction band can be derived. Due to the low conduction band density of states, these interface states will also be charged, as the Fermi level is allowed to rise rather high into the band upon application of a positive gate voltage. Therefore, the analysis of these interface states is also of high importance for the behavior of InGaAs MOS structures.We will then discuss the consequences of this particular interface state density for MOSFET transistors based on an InGaAs MOS structure. The electrostatic operation of different transistor designs will be discussed, including inversion-mode transistors, as well as alternative designs, such as quantum-well devices with different layouts. Electrical measurements of long-channel In0.53Ga0.47As transistors will be shown to illustrate the findings.
12:00 PM - I6.10
Photoelectron Spectroscopy of the Initial Oxidation Stages of Al-covered GaAs Surfaces Under Atomic Oxygen Exposure Conditions.
Athanasios Dimoulas 1 , Georgia Mavrou 1 , Dimitra Tsoutsou 1 , Yerasimos Panagiotatos 1 , Andreas Sotiropoulos 1 , Sotiria Galata 1 , Evangelos Golias 1 , Clement Merckling 2 , Matty Caymax 2
1 Institute of Materials Science, NCSR Demokritos, Aghia Paraskevi Attikis Greece, 2 , IMEC, Leuven Belgium
Show AbstractAtomic layer deposited (ALD) Al2O3 is one of the most successful gate dielectrics for GaAs and InGaAs nMOSFETs1. Here we present an alternative methodology using molecular and atomic oxygen beams in an UHV-MBE chamber emphasizing on the initial stages of oxidation. We study bare and 1ML Al-covered p-type GaAs surfaces with different surface reconstructions (c(4x4)-As, (2x4)-As and (3x6)/(2x6)-Ga), prepared by in-situ thermal desorption of As-capped samples. The reactions of these surfaces with O2 or plasma generated atomic O at different RF power of 180, 300 and 600 W were studied in-situ by XPS and UPS. Upon exposure to molecular O2 for 5 min at 2.5x10-5 Torr at 250C , both the clean and the Al-covered surfaces show Ga oxidation in the 1+ state (Ga2O) as indicated by both the Ga 3d and Ga 2p XPS peak analysis, but no trace of As oxidation was observed regardless the initial surface reconstruction. When the surfaces are exposed to atomic oxygen, both Ga and As are oxidized. Ga is oxidized in both 1+ (Ga2O) and 3+ (Ga2O3) states, while As only in the 3+ state (As2O3). In the case of bare GaAs surface, a strong Ga2O3 component appears which becomes stronger (thicker) as the RF power increases. In contrast, in the case of Al covered GaAs surface, the Ga2O3 component is weak and remains constant as the RF power increases, while Ga2O increases with RF power. This is an indication that an ultrathin layer of Al is sufficient to suppress (but not completely eliminate) the formation of Ga2O3 component which is correlated with poor electrical characteristics2, in favor of Ga2O formation.Upon deposition of 1 ML of Al on (3x6)-Ga terminated GaAs surface, the Al 2p shows a ~0.9 eV chemical shift to higher BE relative to a thick Al control sample, indicative of the formation of Al-As bonds. The absence of unreacted Al peaks indicates that all Al is consumed to form AlAs. Upon exposure to O2, or atomic oxygen for 5 min at 250 C, the Al2p peak shifts to higher binding energy by 1.6 eV compared to the Al control sample, which indicates a “chemisorbed” Al-O state as previously reported3, while the peak associated to Al-As bonds vanishes. The typically observed shift of 2.6 eV characteristic of an Al2O3 oxide is obtained only after the deposition of a nominal 4 nm-thick oxide by Al and atomic oxygen co-deposition. The chemisorbed state produces a low secondary electron cut-off in UPS of about 4.3 eV which is lower than the 4.6 eV measured on a bare (3x6)-Ga terminated GaAs surface, drastically altering the surface potential (band bending). The factors determining the passivation properties of aluminum oxide are under investigation with special emphasis put on the role of Al or Al-O intermediate “chemisorbed” state in controlling the Ga oxidation state under atomic oxygen exposure conditions. 1.M. Houssa et al., MRS Bulletin 34, 504 (2009)2.C.L. Hinkle et al, Appl. Phys. Lett. 94, 162101 (2009)3.S. A. Flodstrom et al., Phys. Rev. Lett. 37, 1282 (1976).
12:15 PM - I6.11
Origins for Electron Mobility Improvement in InGaAs MISFETs with (NH4)2S Treatment.
Yuji Urabe 1 , Noriyuki Miyata 1 , Tetsuji Yasuda 1 , Hiroyuki Ishii 1 , Taro Itatani 1 , Hisashi Yamada 2 , Noboru Fukuhara 2 , Masahiko Hata 2 , Masafumi Yokoyama 3 , Mitsuru Takenaka 3 , Shinichi Takagi 3
1 , National Institute of Advanced Industrial Sience and Technology, Tsukuba Japan, 2 , Sumitomo Chemical, Tsukuba Japan, 3 , The University of Tokyo, Tokyo Japan
Show AbstractIII-V metal-insulator-semiconductor field-effect transistors (MISFETs) are potential candidates to meet the requirements of performance and power-consumption in the 22 nm technology node and beyond [1]. The effectiveness of the (NH4)2S surface treatment in the MIS interface control has widely been recognized for the InGaAs(100) surfaces. We recently found that this treatment can improve the MISFET performance for the (111) surfaces as well [2]. However, the origins for these improvements are not fully understood. In this paper, electrical and physical characterizations of MIS interfaces fabricated on the (NH4)2S-treated InGaAs surfaces are discussed.
MISFETs and MIS capacitors with Al2O3 gate dielectrics were fabricated on (NH4)2S- and NH4OH-treated In0.53Ga0.47As surfaces. The Al2O3 layers were grown by atomic layer deposition (ALD) at 250oC using Trimethylaluminium and H2O. The samples received the post deposition annealing at 400oC in vacuum. The chemical bonding states of the Al2O3/InGaAs interfaces were investigated by using Auger electron spectroscopy (AES) and X-ray photoelectron spectroscopy (XPS).
The (NH4)2S treatment significantly improved the electron mobility (x1.5~2 times) compared with that with the NH4OH treatment, and this improvement was observed in a wide range of effective electric field (0.1-0.8 MV/cm). The SLMM Auger and S 2p photoelectron spectra indicated that S atoms of about 0.6 monolayer exist at the Al2O3/InGaAs interface. Detailed analyses of the photoelectron spectra suggested that Ga-S and In-S bonds are the major interface species, while As-S bonds are minor. C-V measurements for n-InGaAs(100) MIS capacitors showed that the (NH4)2S -treated sample has approximately the ideal flatband voltage (Vfb). On the other hand, the NH4OH-treated sample shows a positive Vfb shift of about 0.15 V, indicating presence of negative fixed charges or dipoles in the Al2O3/InGaAs(100) structure. The C-V measurements also revealed that the minimum density of the interface states, Dit, is rather unaffected by the choice of the wet treatments (about 1x1012 cm-2eV-1). However, the energy position corresponding to the Dit minimum was found to shift toward the conduction band by the (NH4)2S treatment, which reduces the density of the interface-trapped electrons under the n-channel FET operation conditions. These changes in the densities of the charges should lead to weaker Coulomb scattering and thereby contribute to the mobility improvement in the low-field regime. The changes in the interface/surface morphologies, which would affect the mobility under the high field, could not be identified by the standard characterization techniques such as AFM and cross-section TEM.This was carried out in the Nanoelectronics project supported by NEDO.
[1] S. Takagi et al., IEEE ED 55, 21 (2008).
[2] H. Ishii et al., submitted to Appl. Phys. Exp.
12:30 PM - **I6.12
The Role of Controlling III-V Surface Oxides for High Performance MOSFETs.
Marko Milojevic 1 , Arif Sonnet 1 , Christopher Hinkle 1 , Jiyoung Kim 1 , Eric Vogel 1 , Robert Wallace 1
1 Materials Science and Engineering, University of Texas at Dallas, Richardson, Texas, United States
Show AbstractThe prospect of utilizing III-V materials for high performance surface channel field effect devices has been a topic of research for over 30 years. A key impediment has been the quality of the native surface oxides, which results in relatively poor device performance due to electrically active interface defects. This talk will review our recent in-situ studies on the impact of controlling oxidation states at the high-k dielectric/III-V interface, particularly with atomic layer deposition processes. The correlation of these studies with the electrical behavior of capacitors and transistors will also be discussed.
I7: Novel Devices and III-V MOSFET
Session Chairs
Friday PM, April 09, 2010
Room 2012 (Moscone West)
2:30 PM - **I7.1
Impact of Vertical Devices for Future Nano LSI.
Tetsuo Endoh 1
1 , Tohoku University, Sendai Japan
Show Abstract For the past thirty years, the downscaling of the device size has been the guiding principle in the field of LSI technology. The LSI with the planar MOSFET has supported the expansion of the semiconductor industry; however, recently, the limit of this conventional LSI is becoming apparent [1]. As the feature size of planar MOSFETs approach the nano-scale generation, it is becoming more difficult to improve its performance including low power consumption, high speed operation by conventional technology. Therefore, Logic demands new scheme technology. On the other hands, Memory demands new cell technology for shrinking cell size and realizing high speed programming, low voltage operation and good reliability. Especially, the scaling of NAND Flash memories becomes to be difficult by interference phenomena. Moreover, the process cost of smaller cell fabrication becomes very expensive and the reliability of Flash Memories degraded, as the cell is downscaled. In this paper, the excellent performance of Vertical MOSFETs[2]-[4] is shown in comparison with others structured MOSFETs from viewpoints of high packing density and large driving current and good gate controllability etc. The key points of next generation MOSFET are Multi-Gate-Structure, Floating Body Structure and Vertical Structure. Therefore, proposed Vertical MOSFET is emerging as one of the key candidate devices to replace the conventional planar bulk-MOSFET. Moreover, the impact of the proposed Stacked Vertical Flash Memory [5]-[6] for high density Memory is shown. Stacked Vertical Flash Memory [7]-[9] is constructed by three-dimensional (3D) memory array architecture [5]-[6]. The proposed architecture can use all 3D space sufficiently without scaling technology. All devices for the proposed cell are vertically stacked in one silicon pillar so that no additional areas. Therefore, the Stacked Vertical structured Flash cell can reduce to cell area per bit in proportion to 1/N, as the number (N) of stacked memory cells in one silicon pillar increases. As a result, the Stacked Vertical structured Flash cell can realize a drastically smaller cell area per bit. Recently, BiCS[10] from Toshiba and Vertical Gate NAND[11] from Samsung are based on our Stacked Vertical Structured Flash Cell technology. Therefore, the Stacked Vertical Structured Flash Cell technology becomes the main technology in future Flash Memory.[1] International Technology Roadmap for Semiconductors, 2008 Edition.[2] T.Endoh, et al. IEICE Trans.on Elec., Vol.E80-C, No.7, 1997[3] T.Endoh, et al. IEICE Trans. on Elec., Vol.E81-C, No.9, 1998.[4] T.Endoh, et al. AWAD2009, 2009[5] T.Endoh, et al. IEEE J. SS-C, Vol.34, No.4, 1999[6] T.Endoh, et al. IEEE Trans. ED, Vol.48, No.8, 2001.[7] T.Endoh, et al. IEDM 2001, Washington, 2001[8] T.Endoh, et al. IEEE Trans. ED, Vol.50, No.4, 2003.[9] T.Endoh, et al. 2006 IWDTF, 2006[10] Y.Fukuzumi, et al, IEDM 2007, 2007[11] Wonjoo Kim, et al, VLSI Symp. Tech., 2009
3:00 PM - I7.2
Strain Relaxation Mechanisms in Compressively-strained SiGe-on-insulator (SGOI) Films Grown by Si Selective Oxidation.
Marika Gunji 1 , Ann Marshall 2 , Paul McIntyre 1 2
1 Department of Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Geballe Laboratory for Advanced Materials, Stanford University, Stanford, California, United States
Show AbstractStrain controlled SGOI substrates can be promising substrates for both electronic and optical device applications. For example, thin compressively strained SGOI films can have higher hole mobilities than is possible for bulk Si substrates. To control the strain in SGOI films during device fabrication, strain relaxation mechanisms have been studied in SGOI films (10nm ~ 75nm thickness) with high compressive biaxial strain and high Ge composition (xGe>0.6). These films were prepared by selective oxidation of Si from SiGe layers deposited on Si-on-insulator substrates, sometimes referred to as the “Ge condensation” method. During oxidation at temperatures ranging from 900°C to 1125°C proceeds, compressive biaxial strains that initially exceeded the critical value for dislocation-mediated relaxation grow, but the increasingly Ge-rich SiGe layers remain coherent with respect to the underlying Si substrate. Transmission electron microscopy (TEM) revealed that strain relaxation after longer oxidation times was mediated both by planar defect formation and by SiO2 viscous flow that causes buckling of the SGOI layers. In thin SGOI films, planar defects are identified as intrinsic stacking faults by high resolution TEM imaging, and these are expected to result in strain relaxation. However, the density of these stacking faults was insufficient to relax the strain. Cross sectional TEM imaging suggests that SGOI film buckling further promotes strain relaxation. The relative contributions of these two strain relaxation mechanisms will be assessed quantitatively, and prospects for avoiding them will be discussed.
3:15 PM - I7.3
Study of Germanium Epitaxial Recrystallization on Bulk-Si Substrates.
Byron Ho 1 , Reinaldo Vega 1 , Tsu-Jae King-Liu 1
1 Electrical Engineering and Computer Sciences, UC Berkeley, Berkeley, California, United States
Show AbstractContinued CMOS technology scaling has required the incorporation of advanced processes and device structures to increase performance for ever-shrinking transistor dimensions. In this context, silicon-germanium (Si1-xGex) is now utilized as a source/drain (S/D) stressor to compressively strain the channel, thereby enhancing the hole mobility in p-channel Si MOSFETs. Due to its higher carrier mobilities, Ge is also being considered for use as an alternative channel material in future high-performance applications. To date, Ge MOSFETs have been demonstrated on Si1-xGex virtual substrates and Ge-on-insulator (GOI) substrates. In the future, it is likely that different transistor materials and/or structures will be used together to simultaneously meet the performance requirements for the different portions of an integrated-circuit (IC) chip, e.g. high-speed logic, low-power memory, analog/RF, etc. Since Ge-channel MOSFETs would likely be used only selectively on portions of a Si substrate, methods for forming high-quality Ge on Si should be developed. To date, epitaxial Ge-on-Si growth processes using molecular beam epitaxy or ultra-high-vacuum chemical vapor deposition (UHV-CVD) have been developed, but these are relatively expensive. Recently, it has been shown that molten Ge can recrystallize epitaxially upon solidification on Si; this may provide for a lower cost approach to fabricating Ge MOSFETs on Si. There have been several investigations of this approach for silicon-on-insulator (SOI) substrates. In this work, the formation of epitaxial Ge on Si bulk substrates via melting and recrystallization is studied, to assess the viability of this technique for forming S/D stressors and high-mobility channel regions.Ge was selectively deposited by low-pressure chemical vapor deposition (LPCVD) on bulk-Si (100) substrates and then capped with a layer of low-temperature-deposited SiO2 (LTO) before being melted by a rapid thermal process (RTP) or a furnace anneal (FA). RTP anneals, even at sub-melt temperatures, yielded films with deep pits (as determined by atomic force microscopy) that correspond to Ge spiking into the Si substrate (as determined by cross-sectional scanning electron microscopy). The use of a thin intermediary layer of amorphous Si in conjunction with a FA resulted in dramatically reduced pitting, but the recrystallized Ge layer consists of large grains. Reduced pitting was also achieved by confining the area of Ge epitaxial regrowth, for both RTP and FA. Using published coefficients for Ge diffusion in polycrystalline Si, calculated junction depths are on the same order of magnitude as the observed Ge spiking depth. These results suggest that the Ge spiking is due to defect-assisted diffusion at the Si/Ge interface. Mitigation of this phenomenon should allow for the Ge melt technique to be used as a high-throughput/low-cost alternative to epitaxial growth of Ge on Si for future advanced CMOS technologies.
3:30 PM - **I7.4
Scaling of Sub-100 nm InGaAs FinFETs.
Yanqing Wu 1 , Jiangjiang Gu 1 , Peide (Peter) Ye 1
1 School of ECE, Purdue University, West Lafayette, Indiana, United States
Show AbstractThe well-behaved inversion-mode InGaAs FinFETs with gate length down to sub-100 nm with ALD Al2O3 as gate dielectric have been demonstrated. Using a damage-free sidewall etching method, FinFETs with Lch down to sub-100 nm and WFin down to 40 nm are fabricated and characterized. In contrast to the severe short-channel effect (SCE) of the planar InGaAs MOSFETs at similar gate lengths, FinFETs have much better electro-static control and show improved S.S., DIBL and VT roll-off and less degradation at elevated temperatures. The SCE of III-V MOSFETs is greatly improved by the 3D structure design. The SCE could be further redueced at sub-100 nm gate length by implementing "III-V on nothing" and "all around gate" structures.
4:00 PM - I7.5
Interfacial Properties, Surface Morphology and Thermal Stability of Epitaxial GaAs on Ge Substrates with High-k Dielectric for Advanced CMOS Applications.
Avishek Kumar 1 2 , G. Dalapati 1 , M. Kumar 1 , Kin Shun Wong 2 , C. Chia 1 , H. Gao 1 , B. Wang 1 , A. Wong 1 , D. Chi 1
1 , Institute of Materials Research and Engineering, A*STAR (Agency for Science, Technology and Research) , Singapore Singapore, 2 School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore Singapore
Show AbstractIn order to develop next generation devices for the sub-22nm technology nodes, high mobility semiconductors other than Si have been considered as alternative channel materials. III-V compound semiconductors have numerous applications as integrated devices for the high speed digital, microwave, analogue and optoelectronic areas. The coming convergence of the silicon and compound semiconductor device fields will eventually result in the realization of both high performance, high functionality and low cost manufacturing. The introduction of high permittivity gate dielectrics in advanced complementary metal-oxide-semiconductor (CMOS) technologies has allowed the integration of new channel materials on Si platform. In particular, GaAs on Ge had received much attention because GaAs has six times higher electron mobility than Si. However, the integration of high-k dielectrics with epitaxial GaAs on Ge is very challenging due to polar and non-polar nature, different optimum growth temperatures of GaAs and Ge, outdiffusion of Ga, As and Ge, lack of high quality native oxide and presence of Fermi level pinning. In this paper, we present a study on the interfacial properties of high-k dielectrics and epitaxial GaAs and the effect of thermal treatment. Epitaxial GaAs was grown on (100) Ge substrates by metal-organic chemical vapor deposition. Prior to growth, the Ge substrate was heated at 650°C for 5 min to remove the native oxide layer in H2 ambient. Tertiarybutylarsine and trimethylgallium were then introduced for GaAs growth at 0.32 nm/s. After the GaAs/Ge wafers were cleaned in 1% HF solution for native oxide removal, high-k dielectrics (HfO2 and ZrO2) were deposited by atomic layer deposition and magnetron sputtering onto epitaxial GaAs. Post deposition annealing (PDA) was carried out in N2 ambient at 400C-700C for 1 min. Morphological and interfacial properties of the samples were investigated using conductive atomic force microscopy (C-AFM), secondary ion mass spectrometry (SIMS) and high-resolution transmission electron microscopy (HRTEM). The root mean square surface roughness of intrinsic epi-GaAs was measured by AFM to be ~5 nm and increased slightly with Zn doping. C-AFM observation reveals that the surface current distribution is correlated with topography of epi-GaAs. Both SIMS and HRTEM show out-diffusion of Ga and As at the ZrO2/GaAs interface after PDA. However, the outdiffusion of Ge at the Ge/GaAs interface is only 30 nm which is significantly smaller than previous reports. Capacitance-voltage characteristics at different frequencies and temperature were used to extract the energy distribution of the interface states. The density of interface states, Dit for the ZrO2/GaAs interface is about 8E12/eV/cm2 as calculated by Hill's method for room temprature data. Dit at higher temperature will also be discussed.
4:30 PM - **I7.6
Materials and Technologies for Future Generations of CMOS Devices.
Wilman Tsai 1
1 , Intel, Santa Clara, California, United States
Show Abstract5:00 PM - **I7.7
Scaling FETs to 10 nm: Coulomb Effects, Source Starvation, and Virtual Source.
Massimo Fischetti 1 , Seonghoon Jin 2 , Ting-wei Tang 1 , Yuan Taur 3 , Peter Asbeck 3 , Steve Laux 4 , Nobuyuki Sano 5 , Mark Rodwell 6
1 Electrical and Computer Engineering, University of Massachusetts-Amherst, Amherst, Massachusetts, United States, 2 , Synopsys Inc., Mountain View, California, United States, 3 Department of Electrical and Computer Engineering, University of California, San Diego, Mountain View, California, United States, 4 IBM SRDC, Research Division, IBM, Yorktown Heights, New York, United States, 5 Institute of Applied Physics, University of Tsukuba, Tsukuba, Ibaraki, Japan, 6 Department of Electrical and Computer Engineering, University of California, Santa Barbara, Santa Barbara, California, United States
Show AbstractSummary. In our attempts to scale FETs to the 10 nm length, alternatives to conventional Si CMOS are sought on the grounds that: 1. Si seems to have reached its technological and performance limits and 2. the use of alternative high-mobility channel materials will provide the missing performance. With the help of numerical simulations here we establish the reasons why indeed Si seems to have hit a performance barrier and whether high-mobility semiconductors can indeed grant us our wishes. The role of long- and short-range electron-electron interactions will be revisited together with a recent analysis of the historical performance trends. The density-of-states (DOS) bottleneck and source starvation issues will also be reviewed to see what advantage alternative substrates may bring us. Finally, the well-known `virtual source model' will be analyzed to assess whether it can be used as a quantitative tool to guide us to the 10 nm gate length.
Coulomb Interactions and Historical Trends of Si nMOS Performance. Khakifirooz and Antoniadis have analyzed the historical performance trends of Si MOSFETs and found that their performance (measured by the `injection velocity' at the virtual source) saturates and even decreases for gate lengths smaller than about 30-to-40 nm. We will argue that this trend finds its origin in an intrinsic process: Monte Carlo calculations -- performed accounting for long-range and short-range Coulomb interactions among electrons -- have provided a remarkably similar trend and hint strongly at the intrinsic nature of the problem. The use of metal gates can mitigate the effect to some extent, but the channel-S/D interaction is intrinsic and unavoidable, barring the use of Schottky S/D contacts.
High-mobility Channel Materials. The use of high-mobility semiconductors also presents intrinsic difficulties: The DOS bottleneck -- i.e., the reduced inversion capacitance due to their small effective mass -- overcomes the advantage of the higher velocity. Source starvation -- i.e., the inability of the source region to provide the amount of carriers required to maintain a high current across the channel -- makes it necessary to modify significantly our device design. We shall discuss how our simulated InGaAs-channel devices had to be optimized by using thicker channels, higher-doping and raised S/D regions to counter these effects.
Revisiting the `Virtual Source Model'. Coulomb effects, DOS bottleneck, and source starvation (with the associated off-equilibrium effects near the source) force us to revisit the virtual-source model. It will be argued that while providing a useful qualitative guideline to understand the `essential physics' of MOSFETs, its quantitative predictions cannot be trusted when considering gate length at the sub-50 nm scale.
5:30 PM - I7.8
Interface Study of SiO2/ HfO2/SiO2 Stacks Used as InterPoly Dielectric for Future Generations of Embedded Flash Memories.
Alexandre Guiraud 1 2 , Nicolas Breil 3 , Mickael Gros-Jean 1 , Damien Deleruyelle 2 , Gilles Micolau 2 , Christophe Muller 2 , Pierre Morin 1 , Nathalie Cherault 1
1 , STMicroelectronics, 850 Rue Jean Monnet, 38920 Crolles France, 2 , IM2NP, UMR CNRS 6242, IMT Technopôle de Château-Gombert, 13451 Marseille France, 3 , IBM Microelectronics, 850 Rue Jean Monnet, 38920 Crolles France
Show AbstractThe Oxide-Nitride-Oxide (ONO) stack currently used in Flash memory technology has almost reached its scaling limits. In order to further reduce the Equivalent Oxide Thickness (EOT) replacement of the nitride layer by high-k materials is required, whereas the presence of a SiO2 layer is mandatory in order to keep a high electron barrier for high temperature retention issues. As the dielectrics in embedded Flash memory cells experience high thermal budgets interface reactions can occur between SiO2 and high-k layers. In this paper we present an analysis of the high-k/SiO2 interface using physical and electrical characterisation techniques.The analyzed samples were MIS capacitors composed of a tri-layer SiO2/HfO2/SiO2 stack, on the top of which TiN electrodes were patterned. Prior to the high-k material deposition, a 5nm thick High Temperature Oxyde (HTO) SiO2 layer was deposited at 750°C on p-type silicon wafer. The HfO2 layer was then grown by Plasma Enhanced Atomic Layer Deposition (PEALD) using Tetrakis[EthylMethylAmino]Hafnium (TEMAH) precursors and O2 plasma at 250°C. The HfO2 layer was subsequently capped with a second 5nm thick HTO SiO2 layer. Some samples were annealed at high temperature (15s at 1100°C) after HTO deposition. The TiN material used as top electrode was finally deposited by ALD using TiCl4 and NH3 precursors at 400°C.First, HfO2 layers undergo an amorphous-to-crystalline phase transition between 500 and 600°C depending on their thickness. Moreover, Transmission Electron Microscopy (TEM) observations have shown that no significant layer thickness changes occur within the stack. However, from capacitance-voltage C(V) measurements performed on the same MIS structures, the extracted EOT is higher than expected considering thicknesses deduced from TEM experiments and HfO2 phase dielectric constant. This may suggest either an annealing-induced decrease of HfO2 dielectric constant, or the formation of an interfacial layer with a lower dielectric constant. After current-voltage I(V) measurements, HfO2 appears as a promising candidate for future generations of InterPoly Dielectrics (IPD), both in terms of morphological stability after annealing, as well as to electrical leakage performance.To uncover the origin of this higher EOT, thermodynamics simulations are ongoing in order to determine the free enthalpy of intermixing of the different compounds of the stack, as well as Electron Energy Loss Spectroscopy (EELS) and X-ray Photoelectron Spectroscopy (XPS) depth profiling to physically caracterize the interfacial reactions within stacks annealed over a wide range of temperature. These results will be shown during the presentation.