Shriram Ramanathan Harvard University
Supratik Guha IBM T. J. Watson Research Center
Jochen Mannhart University of Augsburg
J1: Materials and Devices for Beyond CMOS Scaling I
Tuesday PM, April 06, 2010
Room 2012 (Moscone West)
9:30 AM - **J1.1
Material Challenges in Novel Correlated Electron Devices.
George Bourianoff 1 Show Abstract
1 , Intel, Austin, Texas, United States
Intel believes that silicon based CMOS technology will remain the workhorse of information processing technology for the next several decades and beyond that, alternative logic technologies will begin to appear based on alternative methods of storing computational state and processing information. Intel and the rest of the semiconductor industry are undertaking vigorous research activities to identify and understand the specifics of what this “beyond CMOS” technology would look like through research collaborations such as the Nanoelectronic Research Initiative (NRI) in the US. Many of the emerging devices may offer lower power operation than CMOS but be slower and perhaps less dense. However a very few devices are theoretically predicted to offer power delay products lower than CMOS by factors as large as 100. The most promising devices are all based on second order phase transitions involving some order parameter in correlated electron materials. One specific example is the Bilayer Pseudospintronic FET (BISFET) The BISFET is theoretically predicted to operate at room temperature in high quality bilayer graphene. Because the tunneling event is triggered by a second order phase transition, there are no energy barriers to overcome and tunneling event it is inherently fast with very low dissipation. Another example is the spin gain transistor which is based on a paramagnetic to ferromagnetic phase transition in MnGe. This device operates by modulating the charge carrier density and change the phase from paramagnetic to ferromagnetic. In both cases, material properties play a critical role . For the BISFET, dielectric quality, graphene quality and uniformity between the two layers are critical. For the spin gain transistor, high magnetic saturation, high free carrier density and sharp phase transition boundaries are important.
10:00 AM - **J1.2
Innately Three Dimensional Spintronic Memory and Logic Devices: Racetrack Memory and Spin Synapses.
Stuart Parkin 1 Show Abstract
1 , IBM Almaden Research Center, San Jose, California, United States
Recent advances in generating, manipulating and detecting spin-polarized electrons and current in magnetic nano-structures make possible entire new classes of spin based sensor, memory and logic devices- technologies generally referred to as the field of spintronics . The magnetic nano-structures are artificially engineered multilayered stacks formed by combining atomically thin magnetic and non-magnetic layers. Spintronic nano-devices have been used to detect data in high density magnetic recording devices since 1997, and thereby allowed for enormous increases in the storage capacity of disk drives. For about a decade these devices were formed from spin-valves  - a magnetic metallic sandwich - but in the past 2-3 years have been superceded by magnetic tunnel junctions (MTJs). MTJs use exactly the same spin- engineering concepts as spin-valves  but an entirely different spin-dependent transport mechanism . MTJs can also be combined with CMOS circuits to form non-volatile solid state memories and potentially allow for reconfigurable logic functionality. The respective strengths of storage and memory, i.e. the very low cost of disk drives and the high performance and reliability of solid state memories, may be combined in the Racetrack Memory . The Racetrack Memory is a three dimensional technology, which stores information as magnetic domain walls in magnetic nanowires, and manipulates them using spin polarized current pulses. To go beyond current memory and logic technologies based on CMOS, a paradigm shift, from the fundamental two dimensional character of CMOS to devices with innately three dimensional characteristics, such as Racetrack Memory, will be needed. Another important change may be to develop devices which are inherently plastic. We show that MTJs can mimic the synaptic switches in the brain and can exhibit spike timing dependent plasticity, a fundamental characteristic of a biological synapse.  S.S.P. Parkin et al., Proc. IEEE 91, 661-680 (2003).  S.S.P. Parkin et al., Nature Materials 3, 862 (2004).  S.S.P. Parkin et al., Science 320, 190 (2008); Scientific American (June, 2009).
10:30 AM - **J1.3
Characterization and Modeling of Exfoliated and CVD Graphene FETs.
Sanjay Banerjee 1 , Emmanuel Tutuc 1 , Leonard Register 1 , Rodney Ruoff 1 , Seyoung Kim 1 , Dipanjan Basu 1 , Luigi Colombo 2 Show Abstract
1 Microelectronics Research Center, University of Texas-Austin, Austin, Texas, United States, 2 , Texas Instruments, Dallas, Texas, United States
Graphene has attracted attention as a high mobility channel replacement for Si in MOSFETs for high frequency applications, for example, in Low Noise Amplifiers. There must be breakthroughs in large area, high mobility graphene growth for this hope to come to fruition. We will discuss Graphene Field Effect Transistors (GFET) results with exfoliated and chemically vapor deposited (CVD) graphene on various metals such as Cu, Co and Ni. Direct deposition of high-k GFET gate dielectrics such as Al2O3 on graphene has been difficult because of the chemical inertness of graphene’s surface. We have developed a novel H2O-based Atomic Layer Deposition (ALD) technique without substantial mobility degradation, using e-beam evaporated and oxidized Al as a nucleating layer. Variability in the edges of the graphene nanoribbons will also likely have a major impact on transport in nanoribbon GFETs. We have theoretically studied the impact of graphene edge roughness on GFETs using a non-equilibrium Green’s function recursive scattering approach. In order to fabricate a dual-gated GFET, the graphene single layer flakes were exfoliated from natural graphite crystals and transferred onto highly doped Si substrates covered with thermally grown SiO¬2. The thickness of the exfoliated layers was measured by combinations of optical contrast of the graphene samples, thickness measurement by atomic force microscopy and Raman spectroscopy. Using the position of the minimum conductivity points in terms of top and bottom gate bias, and by measuring the channel resistance (Rchannel) and the contact resistance (Rcontact), the charge carrier density at Dirac point (n0 = 2.3×1011 cm-2 ) due to disorder, the carrier mobility (µ=8,600 cm2/Vs) and Rcontact were obtained. This high mobility value was confirmed by Hall measurements of a top-gated graphene Hall bar device. GFETs were also fabricated on graphene grown by CVD on various metals such as Cu, Co and Ni. The tradeoffs of the various metals will be discussed.Since bulk graphene sheets are metallic, graphene will probably be need to be patterned into nanoribbons in order to produce reasonable bandgaps and high ON/OFF ratio. In practice it may be difficult to fabricate samples of graphene with perfect edges, and one can expect the effect of non-idealities on degradation of drain current to increase as the width is scaled down. We have theoretically studied the effect of these edge imperfections in nanoribbon GFETs using full band tight binding ballistic quantum transport simulation. Atomic edge roughness was characterized by correlation number, r, defined as the fraction of times the state of an edge site is identical to the corresponding site in the preceding slice, The edge disorder introduces scattering. As the width is scaled down, the impact of the edge disorder increases and transmission goes down. Transmission falls drastically as the correlation falls below 0.99 and the number of steps along the edge increases.
11:30 AM - **J1.4
Electronics for Intelligent Systems: Concepts and Devices.
Todd Hylton 1 Show Abstract
1 , Defense Advanced Research Projects Agency, Arlington, Virginia, United States
Unlike naturally occurring intelligent systems, computational systems built today lack the capacity to spontaneously evolve structure needed to thrive in a complex environment. Further, we currently lack the foundational concepts to describe intelligence in a concise and practically meaningful way. Thus, it is unsurprising that the goal of building intelligent electronic machines remains elusive. The author will present an overview of his thoughts to address this broad challenge and associated programs at the Defense Advanced Research Projects Agency. In particular, the relationship of intelligence to physical phenomena, to the origin of algorithms, to evolution and to neural systems will be discussed. Finally, thoughts on new classes of electron devices and architectures supporting the creation of intelligent electronic systems will be presented.
12:00 PM - **J1.5
On the Possibility of Negative Capacitance in a Ferroelectric Material.
Sayeef Salahuddin 1 Show Abstract
1 EECS, University of California, Berkeley, Berkeley, California, United States
Landau’s theory predicts that, by the inclusion of an ordinary insulator in series, a ferroelectric material may be stabilized away from its energy minima, thereby making its permittivity negative . A number of intriguing situations may result from this arrangement. For example, in a series combination of a negative and a positive capacitance, the composite capacitance is enhanced such that its amplitude is larger than either of the two. In comparison, a series combination of two ordinary capacitances will always result in a smaller capacitance than its constituents. We shall describe how such enhancement of total capacitance may reduce the dissipation of conventional transistors below its fundamental limit. Theoretical considerations in stabilizing the state of negative permittivity will be discussed. Preliminary experimental results will be presented.S. Salahuddin and S. Datta, Nanoletters, Vol .8, No.2, 2008.
J2: Materials and Devices for Beyond CMOS Scaling II
Tuesday PM, April 06, 2010
Room 2012 (Moscone West)
2:30 PM - **J2.1
Electronic Transport in Graphene Nanostructured Devices.
Pablo Jarillo-Herrero 1 Show Abstract
1 , MIT, Cambridge, Massachusetts, United States
Graphene, a one atom-thick sheet of graphite, has emerged in the past couple of years as a fascinating nanomaterial, both from the fundamental point of view as well as for its potential applications in nanoelectronics. Many of the fascinating effects predicted in graphene rely on a precise control of its electronic structure via atomic control of the edges or via local electric fields. In this talk I will review my group efforts in these directions.
3:00 PM - **J2.2
Reinventing the Transistor: A Grand Challenge for Materials Science.
Thomas Theis 1 Show Abstract
1 , IBM Research, Yorktown Heights, New York, United States
I give a simple argument with the following conclusion: To replace the field-effect transistor in complex digital logic, a viable "post-CMOS" device must either 1) store much less energy to represent a logical state, or 2) be superior for the implementation of energy-conserving (adiabatic) logic. Fortunately, a number of exploratory device concepts already aim to meet one or both of these imperatives. Some of these concepts, such as the band-to-band tunnel-FET, are broadly understood and widely pursued. Still, a viable device demonstration may require further substantial advances in the formation of semiconductor heterojunctions and growth or fabrication of semiconductor nanowires. More exotic device concepts require the development of new materials with properties that, while perhaps feasible, simply do not yet exist. I highlight several examples.
3:30 PM - J2.3
Controllable Molecular Modulation of Conductivity in Silicon-based Devices.
Tao He 1 , James Tour 2 Show Abstract
1 , National Center for Nanoscience and Technology, Beijing China, 2 Department of Chemistry, Rice University, Houston, Texas, United States
Electronic properties of silicon-based complementary metal-oxide-semiconductor (CMOS) devices, such as conductivity, are largely dependent on the density of mobile charge carriers, which can be tuned by impurity doping and gating. When the device size scales down to the nanoscale, however, routine doping becomes problematic due to inhomogeneities. Here we report that a molecular monolayer, covalently grafted atop a silicon channel, can play a role similar to impurity doping and gating. This is demonstrated by the controllable modulation of drain current and threshold voltage in pseudo metal-oxide-semiconductor field-effect transistors (pseudo-MOSFETs) by grafting a monolayer of a structurally varied series of molecules (-C6H4-X, with X = NMe2, NH2, NO2, and Mo6 cluster) atop oxide-free H-terminated silicon surfaces of the channel region. This systematic modulation of the device conductance has been observed in both accumulation- and depletion-mode devices with electron donating and accepting molecules. The molecular effects can even penetrate through a 4.92-μm thick silicon layer. Charge transfer (doping-like effects) occurs between the silicon device layer and the molecules upon grafting, which can influence the surface band bending, and makes the molecules act as donors or acceptors. Moreover, the partly charged end-groups of the grafted molecular layer may act as a top gate (gating-like effects). Hence, our results offer a paradigm for controlling electronic characteristics in nanodevices at the future diminutive technology nodes, i.e., surface grafting can be the way of the future to effectively doped nano-silicon based structures. Furthermore, surface grafting capitalizes on the large surface area to volume ratios in small structures. This should therefore be highly significant as others start to construct devices beyond CMOS scaling.
3:45 PM - J2.4
Tunable Anodized-Titania Memristors: Study on Effects of Annealing and Extent of Anodization.
Sumit Chaudhary 1 , Nathan Neihart 1 , Kyle Miller 1 , Kanwar Nalwa 1 , Amy Bergerud 1 Show Abstract
1 Electrical and Computer Engineering, Iowa State University, Ames, Iowa, United States
We have fabricated and characterized memristive devices based on titanium-dioxide ultra-thin films fabricated by electrochemical anodization. We observe that memristance behavior varies both with anodization time of the original Ti film as well on annealing in oxygen-less atomosphere. Two different mechanisms dependent on the metallic contact types are discussed; based on oxygen vacancies, and metallic filaments. This study is expected to be instrumental towards the design of two terminal memristive devices emerging from the electrochemistry route.
4:30 PM - **J2.5
Graphene for Future Electronics.
Robert Westervelt 1 Show Abstract
1 School of Eng & Appl Sciences, and Dept of Physics, Harvard University, Cambridge, Massachusetts, United States
Graphene is a new material with remarkable properties that are promising for future electronics. We discuss atomic-scale graphene devices that can be fabricated by nanoscupting with a transmission electron microscope beam; predicted magnetic edge states that could be used for spin-based logic; and the imaging of electron motion with a cooled scanning probe microscope.*With David Bell, Jesse Berezvoksky, Mario Borunda, Marija Drndic, Eric Heller, Efthimios Kaxiras, Douglas Mason and Weili Wang. Supported in part by the NSF Nanoscale Science and Engineering Center at Harvard, grant NSF-PHY-06-46094.
5:00 PM - **J2.6
Oxide Nanoelectronics on Demand.
Jeremy Levy 1 Show Abstract
1 Physics and Astronomy, University of Pittsburgh, Pittsburgh, Pennsylvania, United States
Electronic confinement at nanoscale dimensions remains a central means of science and technology. I will describe a method for producing extreme nanoscale electronic confinement at the interface between two normally insulating oxides, LaAlO3 and SrTiO3. Using a conducting atomic-force-microscope probe, we can create nanoscale conducting islands, wires, tunnel junctions, diodes, transistors and photoreceivers with spatial dimensions comparable to the diameter of a single-wall carbon nanotube (~2 nm). These structures are created in ambient conditions at room temperature, and can be erased and rewritten repeatedly. This new, on-demand nanoelectronics platform has the potential for widespread scientific and technological exploitation. This work is supported by a DARPA (W911NF-09-10258), ARO MURI (W911NF-08-1-0317) and NSF (DMR-0704022).
5:30 PM - J2.7
Memristor Synapses in Neuromorphic Systems.
Sung Hyun Jo 1 , Ting Chang 1 , Idongesit Ebong 1 , Bhavi Bhavitavya 1 , Pinaki Mazumder 1 , Wei Lu 1 Show Abstract
1 EECS, University of Michigan, Ann Arbor, Michigan, United States
We demonstrate the experimental implementation of synaptic functions using nanoscale memristors. The sequential computation nature of modern computer systems represented by von Neumann machines inherently imposes complexity to the system architecture and software design especially where real time computation is required such as in sensory systems. Hence the advance in computer systems has ironically resulted in less efficient architectures as the complexity of environments (inputs) increases. Key to the high efficiency of biological systems in dealing with complex tasks is the large connectivity between processing units called synapses. The synaptic weight between two neurons can be altered by the ionic flow through it and the adaptation enables the system to learn and operate. We show here that two-terminal memristors can provide the necessary synaptic functions and the connectivity required for hardware implementation of biologically-inspired neuromorphic circuits. In particular, we verify the hybrid memristor/CMOS neuron circuit can exhibit Spike Timing Dependent Plasticity (STDP), an important synaptic adaption rule in which the change of synaptic weight depends on the timing of the pre/post-neurons’ spikes.The memristor consists of a co-sputtered Ag and Si layer with a properly designed mixture ratio gradient that forms a front between the Ag-rich (high conductivity) and Ag-poor (low conductivity) regions in the active switch layer. Injection and depletion of ions in the memristor moves the front between the ion rich region and ion-poor region and causes a continuous change in conductance. The experimentally obtained data from a hybrid CMOS/memristor circuit can be well fit with STDP rules similar to those of biological systems. These results suggest a promising approach for hardware neuromorphic circuit implementation based on CMOS neurons and nanoscale memristor synapses.
5:45 PM - J2.8
Fabrication and Current-voltage Characteristics of Ni Spin Quantum Cross Devices With P3HT/PCBM Organic Materials.
Hideo Kaiju 1 2 , Nubla Basheer 1 , Kenji Kondo 1 , Nobuyoshi Kawaguchi 1 , Susanne White 1 , Akihiko Hirata 3 , Manabu Ishimaru 3 , Yoshihiko Hirotsu 3 , Akira Ishibashi 1 Show Abstract
1 Research Institute for Electronic Science , Hokkaido University, Sapporo, Hokkaido, Japan, 2 PRESTO, Japan Science and Technology Agency, Kawaguchi, Saitama, Japan, 3 The Institute of Scientific and Industrial Research, Osaka University, Ibaraki, Osaka, Japan
Recently, we have proposed spin quantum cross (SQC) devices, in which organic materials are sandwiched between two edges of thin metal films whose edges are crossing, towards the realization of novel beyond CMOS switching devices. In SQC devices, nanometer-size junctions can be produced since the junction area is determined by the film thickness. According to the recent theoretical calculation, SQC devices with organic materials can work as novel switching devices with high on/off ratios beyond 10000:1 and low energy consumption of less than 10 nW. In this study, as the first attempt towards the creation of such novel beyond CMOS devices, we have fabricated Ni SQC devices with poly-3-hexylthiophene (P3HT)/ 6, 6-phenyl C61-butyric acid methyl ester (PCBM) organic materials and investigated the current-voltage characteristics experimentally and theoretically. First, Ni thin films evaporated on polyethylene naphthalate (PEN) substrates have been sandwiched between two polymethyl methacrylate (PMMA) resins. Then, the edge of PMMA/Ni/PEN/PMMA has been polished by chemical mechanical polishing methods. Finally, P3HT/PCBM organic materials have been sandwiched between two sets of PMMA/Ni/PEN/PMMA whose edges are crossing. The Ni thickness has been measured by optical methods and the microstructures of Ni/PEN have been examined using transmission electron microscopy (TEM) and electron diffraction (ED). The current-voltage characteristics have been measured by four-probe methods at room temperature for Ni SQC devices with P3HT/PCBM organic materials. The resistance of the Ni electrode can be reduced down to ∼100Ω, which is much smaller than the electrode resistance of ∼MΩ produced by conventional lithography. This reduction leads to highly sensitive detection of the junction resistance. The electrode resistance as a function of Ni thickness can also be explained from the Mayadas-Shatzkes model, where we use a grain size of 3 nm which is obtained from TEM observation and ED pattern. This indicates that the junction resistance can be precisely detected even though the size of junctions is less than 20 nm x 20 nm. As a result of utilizing a low-resistance electrode, ohmic current-voltage characteristics are obtained at room temperature for Ni SQC devices with P3HT/PCBM organic materials, where the junction area is as small as 16 nm x 16 nm. The junction resistance is 32 Ω, which shows quantitative agreement with the theoretical calculation results performed within the framework of the Anderson model under the strong coupling limit. This indicates that we can obtain a high on/off ratio beyond 10000:1 and low energy consumption of less than 10 nW in Ni SQC devices with P3HT/PCBM organic materials under the weak coupling condition. These results imply that SQC devices with organic materials can be promising candidates for novel beyond CMOS switching devices.
J3: Poster Session
Tuesday PM, April 06, 2010
Exhibition Hall (Moscone West)
6:00 PM - J3.1
Monolithic Integration of III-V Heterostructures on Silicon Using Crystalline Oxide Buffer.
Jun Cheng 1 , Guillaume Saint-Girons 1 , Philippe Regreny 1 , Ludovic Largeau 2 , Gilles Patriarche 2 , Michel Gendry 1 , Guy Hollinger 1 Show Abstract
1 , Lyon Institute of Nanotechnology (INL), Ecully France, 2 , Laboratory for Photonics and Nanostructures (LPN), Marcoussis France
The monolithic integration of III-V semiconductors on silicon is a key issue for further development of micro and optoelectronic systems. It would allow combining optoelectronic functionalities with standard Si-based CMOS systems, using III-V materials as high mobility channels in CMOS transistors, and would enable the fabrication of large size III-V/Si templates which could lead to a major breakthrough in the field of photovoltaic. The direct growth of high-quality III-V heterostructures on Si is made impossible by a too large lattice mismatch. A variety of solutions have been investigated in the past 20 years(Ref 1,2,3) to overcome this limitation, without coming off the definition of a satisfying process. Recently, significant progress has been recorded concerning the growth of crystalline oxides ((Ba,Sr)TiO3, Gd2O3, Pr2O3) on silicon(Ref4,5).In this context, we have proposed to use oxide/Si crystalline templates as buffers for the monolithic integration of III-V on silicon. In fact, the III-V/oxide heterointerfaces present interesting features: the III-V material takes its bulk lattice parameter as soon as its growth on the oxide surface begins, and the mismatch is fully accommated by an array of dislocations confined at the heterointerface. As a result, the III-V material does not contain any threading defect related to any plastic relaxation mechanism, contrasting with standard mismatched epitaxial systems. This opens important perspectives for the monolithic integration of III-V heterostructures on silicon. In this contribution, we will focus on two III-V/oxide/Si systems, namely InP(001)/SrTiO3(001)/Si(001) and InP(111)/Gd2O3(111)/Si(111). The growth mechanisms, particularly the very early stages of the growth and the peculiarities of the lattice mismatch accommodation, will be analyzed in details. We will show how the InP growth conditions can be optimized to improve its structural quality. Room-temperature photoluminescence has been obtained from InAsP/InP quantum wells monolithically integrated on SrTiO3 substrates and on Gd2O3/Si(111) templates. These results will be presented, furthemore, the opportunity of using crystalline oxide/Si templates for the monolithic integration of III-V on silicon will be discussed.Reference:1) J. Bai, J.-S. Park, Z. Cheng, M. Curtin, B. Adekore, M. Carroll, A. Lochtefeld and M. Dudley, Appl. Phys. Lett. 90, 101902 (2007).2)Y. Chriqui, G. Saint-Girons, S. Bouchoule, G. Isella, H. Von Kaenel and. I. Sagnes Electron. Lett. 39, 1658, (2003).3)M.E. Groenert, C.W. Leitz, A.J. Pitera, V.Y. Harry Lee, R.J. Ram, and E.A. Fitzgerald, J. Appl. Phys. 93, 362, (2003).4)Y. Wang, C. Ganpule, B. T. Liu, H. Li, K. Mori, B. Hill, M. Wuttig, R. Ramesh, J. Finder, Z. Yu, R. Droopad, and K. Eisenbeiser, Appl. Phys. Lett. 80, 97, (2002)5)G. Delhaye, C. Merckling, M. El-Kazzi, G. Saint-Girons , J. Appl. Phys. 100, 124109 (2006).
6:00 PM - J3.3
Potential Mapping of UHV Cleaved Functional III-V MOSCAPs with Kelvin Probe Force Microscopy.
Wilhelm Melitz 1 , Jian Shen 1 , Sangyeob Lee 1 , Steven Bentley 2 , Douglas Macintyre 2 , Martin Holland 2 , Iain Thayne 2 , Andrew Kummel 1 Show Abstract
1 , UC San Diego, La Jolla, California, United States, 2 , University of Glasgow, Glasgow, Scotland, United Kingdom
Cross-sectional scanning probe microscopy (SPM) is an imaging technique which can map potential of an operational MOSCAP or MOSFET device. Kelvin probe force microscopy (KPFM) measures the contact potential difference (CPD) of a conductive cantilever and a sample surface with a precision of better than 10 meV. In cross sectional KPFM, (X-KPFM) a fully functional MOSFET or MOSCAP is cleaved in UHV and the potential inside the working device can be measured in two-dimension; UHV cleaving is critical to preserve an oxide-free surface so the unperturbed potential can be measured, Cross-sectional KPFM can determine the effect of surface passivation of gate oxide in operational devices, structural features and their effects on the potential distribution, and even work function offsets of gate and semiconductor. The biggest challenges in imaging cleaved devices is obtaining good cleaves and finding the structure of interest while maintaining good tip conditions for high resolution. By using a comb structure for the electrodes to increase the density of the devices on the cleave face, the fraction of cleaving yielding working devices has improved. The cleave edge of the sample drastically effects the stability of the cantilever. In order to increase the stability, we embed the devices in a >300nm insulator, therefore the device of interest in not located directly on the edge face. Using this capping technique, it has been demonstrated that the gate follows an applied bias in a UHV cleaved GaAs MOSCAP device. For -1 Volt gate bias the CPD of the gate is reduced 796 meV, where at +1 Volt the gate increases 694 meV. The gate oxide is 30nm of GGO and most of the potential drop observed from the gate to the semiconductor occurs of a range of 30-60nm. Current efforts focus on the improvement of cleaves to achieve higher lateral resolution and potential changes in the devices from different gate biases.
6:00 PM - J3.4
Control of Effective Work Function for p-Metal Gate Metal-oxide-semiconductor Field Effect Transistor by Insertion of PE-ALD TiO2 Layer.
Woo-Hee Kim 1 , Wan-Joo Maeng 1 , Hyungjun Kim 2 Show Abstract
1 Department of Materials Science and Engineering, POSTECH (Pohang University of Science and Technology), Pohang Korea (the Republic of), 2 School of Electrical and Electronic Engineering, Yonsei University, Seoul Korea (the Republic of)
We investigated the flat band voltage (VFB) modulation by inserting titanium oxide (TiO2) capping layer into hafnium oxide (HfO2) gate dielectric through plasma enhanced atomic layer deposition (PE-ALD) for p-metal gate metal-oxide-semiconductor field effect transistors (MOSFET). To confirm VFB modulation effects of TiO2 capping layer, Aluminum oxide (Al2O3), as a previously studied capping material for p-FET, was also investigated for comparative studies. Both the capping layers effectively suppressed Fermi level pinning (FLP) effect. However, of the two, TiO2 layer showed lower value of capacitance equivalent oxide thickness (CET) and interface state density (Dit) than those of Al2O3 layer, thereby being of benefit to equivalent oxide thickness (EOT) scaling. For the mechanism of VFB modulation by capping layer, the recent explanation is attributed to dipole layer formation at the interface of HfO2/Si substrate. However, the location of the dipole layer is still controversial either high k/gate or high k/Si interface. Thus, to understand effects of insertion layer according to their position, TiO2 layer was inserted at the top or the bottom of the HfO2 gate dielectric. A superior feature was shown when TiO2 was used as a bottom-inserted layer, where much larger VFB shift(≈ 250 mV) was achieved, indicating the significant reduction in FLP effect. Hence, it can be convinced that the interface which plays a dominant role in the tuning of VFB is the high-k/Si interfacial layer.
6:00 PM - J3.5
A Source/Drain Overlap Design for 16 nm High-k/Metal Gate CMOSFETs.
Towoo Lim 1 , Junyong Jang 2 , Youngmin Kim 1 Show Abstract
1 School of Electrical Engineering, Hongik University, Seoul Korea (the Republic of), 2 LED devision, LGinnotek , Gwangju Korea (the Republic of)
We present simulation based analysis of a Source/Drain (S/D) design for a 16 nm MOSFET. Various gate integration schemes for a high-k gate dielectric and metal gate implementation are considered. A two-dimensional mixed-mode simulation was used to extract switching delays and a trade-off study between series resistance and overlap capacitance has been performed. We have found an optimum S/D overlap to the gate would depend on the gate structure, i.e., 0~1 nm overlap for conventional gate structure and 1~2 nm underlap for high-k surrounding gate one. Based on the calculated delay models, we suggest an optimized gate structure and S/D design for improved performance of nano MOSFETs.
6:00 PM - J3.7
Towards the Spin Wave-based Majority Logic Gate.
Mingqiang Bao 1 , Alexander Khitun 1 , Kin Wong 1 , Kang Wang 1 Show Abstract
1 Electrical Engineering, University of California Los Angeles, Los Angeles, California, United States
We present experimental data illustrating the performance of a four-terminal micrometer scale spin wave-based logic device for potential application as a Majority logic gate. The device fabricated onto a silicon platform comprises a 20nm thick NiFe film, which serves as a spin wave bus. The set of conducting wires on the top of the structure are used to excite spin waves in the spin wave bus and to detect the inductive voltage produced as a result of the spin wave interference. The experimental data show variation of the output inductive voltage as a function of the relative phases of three input signals. The signal of the output voltage is shown to always correspond to the logic majority of the input signals. The device operates in the GHz frequency range and at room temperature. Potentially, the demonstrated prototype device can be used as a basis for spin wave Majority logic gate. The utilization of spin wave devices provides a route to scalable and low-power consuming logic devices compatible with conventional silicon circuitry. We also present numerical estimates on the circuit throughput and compare it with projected scaled CMOS-based circuits.