PeideD. Ye Purdue University
RobertM. Wallace University of Texas-Dallas
John Robertson Cambridge University
Shinichi Takagi The University of Tokyo
Kurt J. Lesker Company
Omicron NanoTechnology USA
P3: Poster Session
Tuesday PM, April 26, 2011
Exhibition Hall (Moscone West)
1:00 AM -
P3.1 Transferred to P7.6
P1: High-k on III-V
Tuesday AM, April 26, 2011
Room 3003 (Moscone West)
9:30 AM - **P1.1
III-V CMOS: The Key to Sub-10 nm Electronics?
Jesus del Alamo 1 Show Abstract
1 , MIT, Cambridge, Massachusetts, United States
CMOS (Complementary Metal-Oxide Semiconductor) scaling is at the heart of the microelectronics revolution. The ability of Si CMOS to continue to scale down transistor size while delivering enhanced performance is becoming increasingly difficult with every generation of technology. For Moore’s law to reach beyond the limits of Si, a new channel material with a high carrier velocity is required. A promising family of materials for this is III-V compound semiconductors. III-Vs are well known for their unique suitability for high frequency electronics. III-V-based integrated circuits are currently in use in a variety of communications and defense applications: some are mission critical, such as space systems where exceedingly high reliability is essential; others are mass-market and very cost-sensitive applications such as power amplifiers for smart phones. The prospect of III-Vs entering the logic roadmap is tantalizing. The requirements are daunting, yet the payoff is huge. This work reviews some of the critical issues.The barrier for insertion of a new channel material into the CMOS roadmap is simply huge. Any new technology has to beat scaled Si designs in performance at device footprints that allow the integration of billions of transistors on the same chip. In addition, cost-effective manufacturing must be realized. The technology has to deliver reliability levels that match that of some of the most complex systems ever made. To make all this work, a III-V CMOS technology has to solve a number of very interesting and challenging technical problems. The development of a gate stack that includes a high-K dielectric and yields a high-quality semiconductor interface with a III-V compound semiconductor is up there as one of the greatest and most fascinating problems in modern semiconductor technology. Recent research suggests that this is an eminently attainable goal. Transistor size scalability is also a major worry. Will it be possible to scale future III-V transistors to the required dimensions while preventing excessive short-channel effects and attaining the demanding parasitic resistance objective? This is a topic that will call for extensive experimental and simulation research. Fortunately, calibrated simulators today reproduce quite well the characteristics of 30 nm gate length III-V FETs and should be valuable in projecting to devices in the 10 nm range. If planar device designs are unsuitable, 3D designs might offer a viable path. Recent 3D device demonstrations with impressive characteristics give hope that this is a promising strategy. A future III-V CMOS technology will also have to “look and feel” as much as Si as possible. This calls for the formation of thin high-quality III-V layers on top of large Si wafers. In fact, depending on what emerges as the best option for the p-channel device, a major challenge in itself, two dissimilar materials might need to be integrated side by side in very close proximity on top of a Si wafer. These are all great problems that will require the coordinated attention of scientists and technologists with expertise in many different domains.This talk will review the prospects and challenges for a III-V CMOS logic technology with gate lengths in the 10 nm range.
10:00 AM - **P1.2
High κ’s/high Carrier Mobility Semiconductors for Post Si CMOS Nano-electronics.
Pen Chang 1 , Tsung-Da Lin 1 , Lung-Kun Chu 1 , Han-Chin Chiu 1 , Yu-Hsing Chang 1 , Mao-Lin Huang 2 , Tun-Wen Pi 3 , Minghwei Hong 1 , Jueinai Kwo 2 4 Show Abstract
1 Department of Materials Science and Engineering, National Tsinghua University, Hsinchu Taiwan, 2 Department of Physics, National Tsinghua University, Hsinchu Taiwan, 3 , National Synchrotron Radiation Research Center, Hsinchu Taiwan, 4 Center for Condensed Matter Sciences, National Taiwan University, Taipei Taiwan
High κ’s on high carrier mobility channels of InGaAs and Ge are now strong candidates for technologies beyond the 15 nm node ICs. Five key material/electrical/processing issues need to be solved for realizing the new devices are equivalent oxide thickness (EOT) < 1 nm, interfacial density of state (Dit) ≤ 1011 eV-1cm-2, self-aligned process, low parasitic resistance, and integration with Si. This talk will cover the tremendous progress on the first three area made by this research group and many others with molecular beam epitaxy (MBE) and atomic layer deposition (ALD) high κ’s of Ga2O3(Gd2O3), Al2O3, and HfO2; namely attainment of an EOT of 0.5 nm, Dit of low 1011 eV-1cm-2 (with a flat distribution versus energy within the semiconductor bandgap), and high-temperature stability of the MOS structures. Particular attention will be paid to the high κ’s/InGaAs and /Ge interfaces. High-performance self-aligned inversion-channel high κ’s/InGaAs and /Ge MOSFET’s will also be discussed.
10:30 AM - P1.3
On the Surface Passivation of GaAs and In0.53Ga0.47As with Amorphous Silicon Interlayer.
Jean Fompeyrine 1 , Mario El-Kazzi 1 , Chiara Marchiori 1 , Dave Webb 1 , Christian Gerl 1 , Lukas Czornomaz 1 , Christophe Rossel 1 , Mirja Richter 1 , Maryline Sousa 1 , Daniele Caimi 1 , Heinz Siegwart 1 , Tomas Smets 2 1 Show Abstract
1 Zurich Laboratory, IBM ResearchGmbH, Rueschlikon Switzerland, 2 Departement of Physics and Astronomy, Solid State Physics and Magnetism, Leuven Belgium
III-V based metal-oxide-semiconductor field effect transistors (MOSFET) are considered as promising candidates for replacing Si-based devices beyond the 15nm CMOS technology node. Nevertheless, competitive n-channel FETs have not yet been demonstrated. Numerous challenges have to be tackled, among them the passivation of electrical defects at the interface between the semiconducting channel and the high-k dielectric, and the fabrication of self-aligned source and drain contacts with low resistivity.The passivation of GaAs surfaces using MBE-grown hydrogenated amorphous silicon (a-Si) as interface layer (IL) and in combination with HfO2 as a high-k dielectric were already reported earlier. The interface state density (Dit) distribution can be mapped over the whole GaAs band gap by conductance measurements at different temperatures. Minimum values down to Dit = 7.10^11 cm-2 are obtained close to the conduction band edge. We report here on the use of this IL scheme to the passivation of InGaAs surfaces with an In content up to 53%. For the largest In content, the Dit distribution within the band gap is extracted. In the vicinity of the conduction band, Dit values close to 10^12 cm-2 are measured. In order to reach sub-nm equivalent oxide thicknesses (EOT), the different thicknesses must be aggressively scaled, and interdiffusion between a-Si and HfO2 must indeed be avoided. The thermal stability of the gate stack will therefore be discussed, and alternative approaches to minimize the interdiffusion at the different interfaces are investigated. For the gate deposition. different metallization processes will finally also be compared, either using evaporated aluminum or sputtered tungsten gate. We show that the interface quality clearly depends on the deposition method. In particular, capacitors fabricated on n-GaAs exhibit lower Dit with Al gates than with W gates, whereas the opposite observation is done on capacitors fabricated on p-GaAs.Finally, the impact of our results on the fabrication of quantum-well, InGaAs based transistors will be considered, and we will discuss whether the use of a-Si IL is a viable approach. C. Marchiori et al, J. Appl. Phys. 106 p114112 (2009)
10:45 AM - P1.4
Low Temperature Characterization of HfO2 InAs MOS Diodes.
Erik Lind 1 , Lars-Erik Wernersson 2 1 Show Abstract
1 Solid State Physics, Lund University, Lund Sweden, 2 Electrical and Information Technology, Lund University, Lund Sweden
InAs is an interesting alternative as a channel material for future III-V MOSFETs, due to a high electron mobility and injection velocity. Pseudomorphic HEMTs based on InAs channels have shown excellent performance, with transconductances over 2 mS/µm  for gate length of 40 nm. Further scaling of the gate length can be achieved by introducing a high-k oxide as an gate insulator. We have investigated the properties of n-type InAs/HfO2 diodes with high-k oxides grown by ALD. The epi-ready oxide on a (100) InAs wafer was removed in an H2 anneal prior to loading the wafer into an ex-situ ALD system. 80 cycles of HfO2 was deposited at 250C using TDMAHf and H2O as precursors, resulting in an oxide thickness of approximately 6 nm. MOS diodes with sputtered W/Au metal contacts of an area of 27000 µm2 were formed using optical lithography and wet/dry etching.In order to characterize the oxide/semiconductor interface, we performed G-V and C-V measurements at temperatures between 4.2 K to 300 K and frequencies between 1 kHz-100 kHz. From the low temperature range (10〈 T〈 100 K) conductance measurements, a low Dit of 5x1011 eV-1cm-2 was observed at the conduction band edge, increasing towards 10x1012 eV-1cm-2 towards the valence band, possibly overestimated through a weak/strong inversion response . These numbers are promising, considering the simple ex-situ process used prior to the ALD process, indicating that InAs could be a good candidate for III-V MOSFETs. The low temperature, high-frequency, C-V curves can further be well fitted to simulated curves by taking the strong nonparabolicity of the InAs band structure into account . In accumulation, a logarithmic frequency dispersion is observed, most likely related to charge traps inside the oxide. For a small accumulation voltage of Vg=0.1 V at T>100 K, the dispersion is less than 1%. This increases almost linearly with temperatures above 100 K to 4.4% at T=300 K, indicative of a weakly temperature activated process. The effect of post deposition anneals will also be presented.K. Dae-Hyun and J. A. del Alamo, "Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications," Electron Devices, IEEE Transactions on, vol. 57, pp. 1504-1511, 2010. K. Martens, et al., "On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates," Electron Devices, IEEE Transactions on, vol. 55, pp. 547-556, 2008. E. Lind, et al., "Accumulation capacitance of narrow band gap metal-oxide-semiconductor capacitors," Applied Physics Letters, vol. 96, Jun 2010.
11:30 AM - **P1.5
III-V MOSFETs for Sub-15 nm Technology Generation CMOS Applications.
Iain Thayne 1 Show Abstract
1 School of Engineering, University of Glasgow, Glasgow United Kingdom
To address issues associated with continual scaling of the International Technology Roadmap for Semiconductors (ITRS) beyond the 15 nm technology generation, MOSFETs with high mobility channel materials are now being seriously considered. As a result, there has been a significant expansion in research into III-V MOSFETs as a potential n-channel device solution.Whilst a high mobility channel device solution may offer enhancements in drive current and switching speed, an equally important driver will be transistor density scaling which will continue unabated, and therefore the geometric half-pitch metrics of the ITRS will have to be met, irrespective of the technology solution being employed. This density scaling will put severe contraints on both static and dynamic power consumption and it could be the case that high mobility channel solutions will enable a significant reduction in rail voltages and therefore power consumption. It should also be borne in mind that mainstream semiconductor manufacture is, and probably always will remain, silicon-based. As a consequence, any alternate high mobility channel material based device solution must be manufacturable using contemporary silicon processing methodologies. For the case of compound semiconductor based devices, this means replacing traditional III-V approaches of gold-based contact metallization and lift-off techniques with blanket refractory metal deposition and subtractive dry etching. These latter routes have the potential to introduce significant mobility degrading damage into the underlying semiconductor materials which clearly has to be mitigated against in any process module development.This presentation will review issues in realising aggressively III-V MOSFETs for beyond 15 nm CMOS, including the challenges to be addressed in demonstrating manufacturable process modules to define the gate stack, source-drain contacts, and access regions. A common theme is the development of silicon compatible process modules and integrated flows which do not compromise the high mobility channel properties due to process induced damage. An intimate linkage between device architecture, scalability and manufacturability will be demonstrated, and will be explained with reference to various aggressively scaled III-V MOSFET process modules recently developed in Glasgow and elsewhere.
12:00 PM - P1.6
Interface Modification in the High-k/n-In0.53Ga0.47As System.
Paul Hurley 1 , Eamon OConnor 1 , Terrance ORegan 1 , Scott Monaghan 1 , Vladimir Djara 1 , Negara Adi 1 , Aileen OMahony 1 , Ian Povey 1 , Alan Blake 1 , Dan OConnell 1 , Martyn Pemble 1 , Karim Cherkaoui 1 Show Abstract
1 Tyndall, University College Cork, Cork Ireland
The use of high mobility channel materials such as InxGa1-xAs and Ge in future integrated circuits introduces the possibility of improved performance to power ratio for devices with minimum feature sizes ≤16nm. One of the main challenges associated with the successful integration of high indium concentration InGaAs n-channel MOSFETs into CMOS processes is the intrinsic elimination and/or passivation of electrically active bulk and interface defects which are present in the high-k/InGaAs system. Interface state densities are typically reported to be in the range mid-1012 to 1013cm-2 eV-1[1-3], which remains too high for practical device applications. While reduced interface state densities are obtained using a quantum well structure with a top III-V barrier layer , this layer does add to the overall gate capacitance, so research interest remains in high-k layers directly on high indium concentration InxGa1-xAs channels. This paper will describe our recent experiments aimed at surface preparation of In0.53Ga0.47As prior to high-k deposition to reduce interface state concentrations and the use of multi layer high-k gate stacks on In0.53Ga0.47As surfaces. The surface preparation is based on the use of a remote plasma source in the atomic layer deposition system, to expose the In0.53Ga0.47As surface to a hydrogen plasma prior to the ALD high-k deposition. Based on capacitance-voltage (CV) and conductance-voltage (GV) analysis of the resulting high-k/In0.53Ga0.47As/InP MOS structures, the remote plasma process does result in improved interface state density values. The paper will also report a second approach of oxide based interface control layers. It has recently been reported  that the use of bi-layer oxide gate stacks, such as HfO2/Al2O3/In0.53Ga0.47As/InP, incorporating Al2O3 (~1nm) as a wide band gap interface control layer, improves the electrical properties of the high-k/n-In0.53Ga0.47As MOS system. We will report on the use of Al2O3 (0.5nm to 1 nm) at the both the In0.53Ga0.47As and metal interfaces in a Pd/Al2O3/HfO2/Al2O3/In0.53Ga0.47As/InP structure, which results in further improvements in electrical properties of the gate stack on In0.53Ga0.47As. É. O'Connor, et al Appl. Phys. Lett. 94, 102902 (2009) G. Brammertz, et al J. Electrochem. Soc. 155, H945 (2008) Yoontae Hwang, et al Appl. Phys. Lett. 96, 102910 (2010) M. Radosavljevic, et al Proc of IEDM (2009) A. O’Mahony et al, Appl. Phys. Lett., 97, 052904 (2010)
12:15 PM - P1.7
TiO2/Al2O3 Bilayer Dielectrics as Gate Oxide for In0.53Ga0.47As Metal Oxide Semiconductor Devices.
Jaesoo Ahn 1 , Marika Gunji 1 , Irina Geppert 2 , Yu Yuan 3 , Yuan Taur 3 , Moshe Eizenberg 2 , Paul McIntyre 1 Show Abstract
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Materials Engineering, Technion - Israel Institute of Technology, Haifa Israel, 3 Electrical and Computer Engineering, University of California, San Diego, San Diego, California, United States
We report electrical properties of Atomic-Layer-Deposited (ALD) TiO2 and Al2O3 bilayer gate dielectrics and comparison with single ALD-Al2O3 dielectrics on n-InGaAs substrates that were originally As2-capped to prevent uncontrolled oxidation prior to gate oxide deposition. Capacitance-Voltage (CV) analysis in the frequency range of 1k to 800kHz shows that forming gas anneal (FGA) reduces the CV stretch-out and frequency dispersion for both monolayer and bilayer dielectrics. Comparison of the measured CV curve to an ideal, calculated curve including the simulated capacitive response of the substrate, suggests a total interface trapped charge density (Dit) in high-10^12 cm^-2eV^-1 range for energies in the top half of the InGaAs band gap. The maximum accumulation capacitance (Cmax) of the bilayer gate oxide increases by more than 60% after FGA at 400°C for 30 min, whereas Cmax of the monolayer Al2O3 capacitor remains the same. Crystallization of the TiO2 film, which is responsible for the Cmax increase, is observed after FGA at 350°C in plan-view Transmission Electron Microscopy (TEM) and confirmed by a Selected Area Electron Diffraction (SAED), with a mixture of anatase and rutile phase diffraction rings. The resulting gate stacks can achieve sub-nm capacitance-derived equivalent oxide thickness after accounting for the InGaAs substrate capacitance. The conduction band offsets of Al2O3 and TiO2 to In0.53Ga0.47As measured by X-ray Photoelectron Spectroscopy (XPS) are 2.4eV and 0.6eV, respectively, indicating the ability of this stacked dielectric to suppress gate leakage conduction.
12:30 PM - **P1.8
High Performance InGaAs Quantum Well FETs with High-k Dielectrics.
Marko Radosavljevic 1 Show Abstract
1 , Intel Corporation, Hillsboro, Oregon, United States
In this talk, we will review and present the recent development at Intel on high performance InGaAs quantum well FETs with high-k dielectrics.
P3: Poster Session
Tuesday PM, April 26, 2011
Exhibition Hall (Moscone West)
6:00 PM - P3.2
Density-Functional Theory Molecular Dynamics Simulations of a-Al2O3/InGaAs, a-HfO2/InGaAs, and a-ZrO2/InGaAs Interfaces.
Evgueni Chagarov 1 , Andrew Kummel 1 Show Abstract
1 , UCSD, La Jolla, California, United States
Density Functional Theory Molecular Dynamics (DFT MD) simulations were applied to simulate bonding and electronic structure of a-Al2O3/InGaAs, a-HfO2/InGaAs, and a-ZrO2/InGaAs interfaces. Highly realistic samples of amorphous a-Al2O3, a-HfO2, and a-ZrO2 were generated by hybrid classical-DFT MD simulations and were verified comparing simulated coordination distributions, average coordination numbers, radial- and angular distribution functions to experimentally measured properties. The high-K oxide/InGaAs interfaces were DFT MD annealed, cooled and relaxed to simulate the most realistic interface bonding avoiding formation of predetermined interface structure. For each oxide/InGaAs interface two separate systems were simulated using different initial oxide terminations in interface region to improve general statistics. All 6 obtained high-K oxide/InGaAs interfaces revealed unpinned interface; however some interfaces demonstrated bandgap-edge states localized at under-coordinated interfacial atoms. In addition the interfacial coordination distribution, charge transfer through interface, and InGaAs layer-by-layer deformation were investigated.
6:00 PM - P3.3
La2O3-Al2O3-TiO2 Multilayer Gate Dielectrics for Ge MOS Devices Prepared by Atomic Layer Deposition.
Chih Chiao Chen 1 , Jyun Kai Lan 1 , Jyun Yi Wu 1 , Ming Ho Lin 1 , Tai Bor Wu 1 , Su Jien Lin 1 Show Abstract
1 Material Science and Engineering, National Tsing Hua University, Hsinchu Taiwan
Germanium (Ge) is a promising candidate for channel material in high-performance metal-oxide-semiconductor (MOS) devices since it possesses higher intrinsic carrier mobility and narrower band gap than those of Si. However, it is difficult to achieve a high-quality oxide/Ge interface comparable to SiO2/Si due to unfavorable surface properties and unstable native oxides of Ge. Therefore, one of the critical issues is finding adequate high-κ gate oxide materials to reduce interface defect density and to form thermodynamic favorable interlayer with Ge. La2O3, Al2O3 and TiO2 have been applied as such high-κ gate oxide materials. There are several dramatic advantages we concerned, like stable interlayer lanthanum germanate (LaGeOx) between Ge and La2O3, excellent thermal stability and large band gap (~8.8 eV) of Al2O3, and high dielectric constant (60-80) of TiO2. Moreover, it has been known that La2O3 and Al2O3 are the compatible oxides owing to the stable compound LAO forming. In this study, the high-κ stacks in the MOS structures consistent with La2O3, Al2O3 and TiO2 multilayer alternatively were deposited by remote-plasma atomic layer deposition (RPALD) system. We will change their relative position to investigate the interaction between different oxides and Ge even between different oxides separately. After the MOS capacitor preparation, Capacitance-voltage (C-V) and current-voltage (I-V) measurement were done to discuss the electrical characteristics, such as equivalent oxide thickness (EOT), flatband voltage (VFB), hysteresis window, and leakage current density (Jg@VFB-1V). Cross-sectional high resolution transmission electron microscopy (HRTEM) images were obtained to examine the morphology and microstructure of the high-κ films. The chemical composition and binding structure of the sample were analyzed by x-ray photoelectron spectroscopy (XPS).
6:00 PM - P3.4
Effect of Different La2O3 Locations on Electrical Properties and Crystal Structure in HfO2/La2O3/HfO2 Gate Stack.
Jyun-Yi Wu 1 , Ming-Ho Lin 1 , Su-Jien Lin 1 , Tai-Bor Wu 1 Show Abstract
1 Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan
Recently, lanthanum (La) incorporation into HfO2 has attracted much attention because of its several beneficial effects, such as higher permittivity (~30) and large conduction band offset (2.3 eV) of the La2O3 film. Besides, it is also reported that HfO2 with La incorporation can suppress the oxygen vacancy formation.In this work, we fabricated 5 nm thick HfO2/La2O3/HfO2 stack structure with different La2O3 positions to investigate the La2O3 location effect in HfO2 gate oxide. The vertical location of La2O3 layer was accurately controlled by atomic layer deposition (ALD). After the MOS capacitor preparation, capacitance-voltage (C-V) and current-voltage (I-V) relations were measured to study the electrical properties. In addition, chemical composition and depth profile were examined by Secondary Ion Mass Spectrometer (SIMS). From the results, we found that the La2O3 position affects the flatband voltage (VFB) and thermal stability. Besides, from the In-plane X-ray diffraction (IPXRD) results, we found that a specific La2O¬3 position can make the crystal structure of HfO2 transfer to a cubic phase which shows higher permittivity (~40) than that of monoclinic phase (~19).
6:00 PM - P3.5
CVD Growth of Graphene with Micro-engineered Metal Catalyst.
Bin Yu 1 , Bhaskar Nagabhirava 1 , Eisenbraun Eric 1 Show Abstract
1 CNSE, SUNY-Albany, Albany, New York, United States
We report a technique to grow graphene layers using micro-engineered metal catalyst film. The new method provides ultra-thin, highly uniform, low defect, and conformal metal films as compared with the conventional beam-evaporated films. Different from evaporated metal films or foils that are commonly used in the research community, we use micro-engineered metal catalyst (Cu/Ni) for graphene CVD growth. In this poster we will report the experimental results of graphene growth based on such thin films. The micro-engineered Cu/Ni layers enhance the expected lateral growth of graphene layers due to the absence of inter-granular defects which leads to the disruption of growth process. Using thin catalyst films and high cooling rates enable the good control of graphene layers. A range of thin-film physical thickness is investigated and graphene is grown using CVD at raised temperature with methane as the precursor. Basic characterization on critical graphene morphology and material properties will be reported.
6:00 PM - P3.7
DC/AC Performance Analysis of Indium Antimonide Nanowires.
Ali Guvenc 1 , Miroslav Penchev 1 , Jiebin Zhong 2 , Cengiz Ozkan 2 3 , Mihrimah Ozkan 1 Show Abstract
1 Electrical Engineering, University of California, Riverside, Riverside, California, United States, 2 Mechanical Engineering, University of California, Riverside, Riverside, California, United States, 3 Materials Science and Engineering Program, University of California, Riverside, Riverside, California, United States
We investigated the electrical properties and transmission line performance of indium antimonide nanowires. The results indicate that the of nanowires suffer from low mobility values on the order of 10-15 cm2V-1s-1 because of the contact resistances, scattering due to their small diameters, crystal defects and oxidation occurs during growth and cooling. nanowires show extremely inductive behavior during the AC measurements and due to these parasitic parameters, they can sustain transmission for the signals having frequencies up to 20 MHz. The bandwidth of the nanowires is directly proportional to the diameter of the nanowires. Improving the mobility to higher values and introducing de-embedding and impedance matching to the measurements and analysis could easily carry the bandwidth beyond GHz levels..
6:00 PM - P3.8
Deposition of Lanthanum Hafnium Titanium Oxide High-κfilms on Ge Substrate by Atomic Layer Deposition.
Jyun-Kai Lan 1 , Chih-Chiao Chen 1 , Ming-Ho Lin 1 , Jyun-Yi Wu 1 , Tai-Bor Wu 1 , Su-Jien Lin 1 Show Abstract
1 , National Tsing Hua University, Hsinchu Taiwan
As alternative to Si in high-speed logic devices, Ge is widely considered due to its higher carrier mobility. Coupling Ge channel with high dielectric constant material is a promising strategy for ultrascaled logic devices. However, Ge surface passivation is a big challenge especially. GeO2 becomes unstable when it is deposited on Ge , because it reacts with Ge forming substoiciometric oxide or GeO. GeO is volatile and sublimes leaving behind a defective interface. Rare earth oxides are considered to be class of materials which offer good passivation of Ge , as it has recently been suggested. This is because rare earth oxides react strongly with the substrate resulting in catalytic oxidation of Ge and in the spontaneous formation of stable interfacial layers. Lanthanum oxide is one rare earth oxide which has been studied mainly for Si-based devices, while there is considerably less work related to the properties of La2O3 deposited on Ge substrates . But La(OH)3 formation due to OH− groups absorption when La2O3 is exposed to air significantly degrades its k value In this study , we use atomic layer deposition process to prepare a thin La2O3 passivating layer and a HfO2 or Tio2 cap layer to take advantage of the higher κ and the good insulating properties of the latter material.Finally , LHTO films are characterized by a combination of (i)grazing incidence x-ray diffraction (GIXRD), (ii) high resolution transmission electron microscopy (HRTEM) and (iii) X-ray photoelectron spectrometer (XPS), (iv) capacitance-voltage (C-V), and current density-voltage (J-V) measurements.
6:00 PM - P3.9
Atomistic Study of Passivation of Ge(100) Surface via Nitridation and Oxidation.
Joon Sung Lee 1 2 , Sarah Bishop 2 , Tobin Kaufman-Osborn 1 2 , Andrew Kummel 2 Show Abstract
1 Materials Science and Engineering, University of California, San Diego, La Jolla, California, United States, 2 Chemistry and Biochemistry, University of California, San Diego, La Jolla, California, United States
Germanium is a promising channel material for next generation MOSFET devices since it has superior electronic properties when compared to silicon. However, high interface trap density between a Ge surface and a Ge native oxide has been a challenging issue when fabricating practical devices, which demands a proper passivation of the Ge surface. Among various passivation methods, nitridation and oxidation have shown the most promising results. Nevertheless, for a highly-scaled MOSFET device with a high-k dielectric layer, the thickness of these passivation layers should be minimized down to one or two monolayers. In this study, the monolayer passivation of the Ge(100) surface via formation of Ge-N and Ge-O surface species was investigated using scanning tunneling microscopy (STM) and density functional theory (DFT).Direct nitridation was performed on a Ge(100) surface using an electron cyclotron resonance (ECR) plasma source with pure N2 gas, and a submonolayer Ge-N ordered structure was formed at 500°C. This is consistent with the thermal stability of Ge nitride at this temperature. However, scanning tunneling spectroscopy (STS) showed that the Fermi level of the n-type Ge(100) surface was pinned near the valence band edge after the nitridation process. Theoretical modeling using DFT calculations showed that the bandgap states are produced from the ordered nitride structure, which is consistent with the Fermi level pinning of the surface. It is predicted that a further passivation process such as forming gas annealing (FGA) is needed to unpin the Fermi level by reducing the dangling bonds and bond strain of the ordered structure.The best method to passivate a Ge(100) surface is to form a layer of GeO2 free of Ge suboxides. However, the thermodynamic behavior of GeO2 (GeO2 + Ge → 2GeO) makes it difficult to keep stoichiometric GeO2 monolayer at an elevated temperature. H2O is a promising oxidant for Ge because its reaction temperature in the ALD process is normally lower than 300°C. Using a differentially-pumped H2O dosing system, a monolayer of H2O chemisorption sites on a Ge(100) surface was obtained with a low density of unreacted dangling bonds at room temperature. The H2O chemisorption sites appear dark in the filled state STM image due to the termination of the surface dangling bonds by –OH and –H. By annealing up to 250°C, the coverage of H2O sites decreased significantly. This is consistent with desorption of H2 or H2O, and the multiple prepulsing of H2O at 250°C previously reported by other groups. The H2O chemisorbed Ge surface is ideal monolayer passivation of Ge which can serve as a great template for the ALD process, since it contains a half monolayer of –OH which induces the formation of Al-O bonds with the introduction of tri-methyl aluminum (TMA). High resolution XPS experiments indicated that thermally unstable Ge-OH bonds were converted to thermally stable Al-O bonds.
PeideD. Ye Purdue University
RobertM. Wallace University of Texas-Dallas
John Robertson Cambridge University
Shinichi Takagi The University of Tokyo
Kurt J. Lesker Company
Omicron NanoTechnology USA
P4: High-k on Ge and III-V
Wednesday AM, April 27, 2011
Room 3003 (Moscone West)
9:00 AM - **P4.1
High Mobility Strained Ge Channels and Gate Dielectrics for Planar and Non-Planar p-MOSFETs.
Judy Hoyt 1 , Pouya Hashemi 1 , Hyung-Seok Lee 1 , Maruf Bhuiyan 1 , Dimitri Antoniadis 1 Show Abstract
1 , MIT, Cambridge, Massachusetts, United States
Strained Ge epitaxial layers with thickness < 10 nm grown pseudomorphic to relaxed SiGe have been demonstrated in the past to achieve record hole mobilities (e.g. a factor of 10 enhancement relative to unstrained Si p-MOSFETs). Such structures have included a thin strained Si cap layer which improves the mobility but increases the capacitance equivalent thickness of the device, which is a problem for ultimate device scalability. For nanoscale devices, a suitable gate dielectric that maintains high mobility without the use of a Si cap layer is desired. This presentation will begin with a review of high mobility Ge channel structures for planar and non-planar (e.g. tri-gate type) Ge p-MOSFETs. Preliminary results on measured channel mobilities for planar strained Ge p-MOSFETs with and without a Si capping layer, utilizing high-k/metal gate stacks, will be discussed.
9:30 AM - **P4.2
Fundamental Aspects and Interface Engineering of Ge-MOS Devices.
Heiji Watanabe 1 , Katsuhiro Kutsuki 1 , Lori Hideshima 1 , Gaku Okamoto 1 , Shoichiro Saito 1 , Tomoya Ono 1 , Takuji Hosoi 1 , Takayoshi Shimura 1 Show Abstract
1 Department of Material and Life Science, Osaka University, Suita, Osaka, Japan
As Si-based MOS devices are now facing physical limitations in attempts to enhance transistor performance, Ge has attracted attention as an advanced channel material due to its higher hole and electron mobility. Among various gate dielectric candidates for Ge-MOS devices, GeO2 is known as a fundamental material for gate dielectrics. Although previous reports have pointed out the poor thermal stability and electrical degradation of GeO2, recent experimental and theoretical studies have indicated its promising features. We have explored the fundamental aspects of GeO2/Ge interface based on first-principles calculations and presented distinct evidence of superior electrical properties of Ge-MOS devices . Moreover, in order to overcome electrical degradation caused by instability of GeO2 in ambient environment, we proposed in situ low temperature vacuum annealing of the oxides prior to gate electrode formation . Improvement in electrical properties of the Ge-MOS devices, such as significantly reduced flatband voltage shift, small hysteresis, and minimized minority carrier response in C-V characteristics, has been demonstrated. In addition, high quality and thermally stable Ge oxynitride (GeON) were fabricated by nitridation of GeO2 surface . Plasma nitridation was found to be a very effective method to form a stable nitride capping layer on the oxide and improve the stability of gate dielectric. Consequently, degraded insulating feature of ultrathin GeO2 caused by air exposure was recovered, and we were able to achieve excellent interface quality with GeON scaled down to 1.7 nm. Furthermore, it was found that the nitride capping layer, which suppresses volatilization of GeO molecules and resultant electrical degradation, improves thermal stability of the gate dielectrics. We also concluded that thermal annealing just below the decomposition temperature is beneficial in terms of EOT shrinkage and defect passivation both within the bulk and at the GeON/Ge interface .  S. Saito, T. Hosoi, H. Watanabe, and T. Ono, Appl. Phys. Lett. 95, 011908 (2009).  T. Hosoi, K. Kutsuki, G. Okamoto, M. Saito, T. Shimura, and H. Watanabe, Appl. Phys. Lett. 94, 202112 (2009).  K. Kutsuki, G. Okamoto, T. Hosoi, T. Shimura, and H. Watanabe, Appl. Phys. Lett. 95, 022102 (2009).  K. Kutsuki, I. Hideshima, G. Okamoto, T. Hosoi, T. Shimura, and H. Watanabe, Jpn. J. Appl. Phys. (in press).
10:00 AM - P4.3
Impact of Post Deposition Annealing Treatment on the Interface and Oxide Defects in LaGeOx Grown on Ge Substrates by Molecular Beam Deposition.
Alessandro Molle 1 , Silvia Baldovino 1 2 , Marco Fanciulli 1 2 , Dimitra Tsoutsou 3 , Evangelos Golias 3 , Athanasios Dimoulas 3 Show Abstract
1 Laboratorio MDM, CNR-IMM, Agrate Brianza (MB) Italy, 2 Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano Italy, 3 , NCSR-Demokritos, Athens Greece
Despite a general consensus on GeO2 as passivation layer for Ge channel substrate in advanced logic applications, the dielectric performance of GeO2 are poor so that consideration must be extended to other passivating materials which allow for a more aggressive scaling of the final metal-oxide-semiconductor (MOS) based devices.To this purpose, La-assisted oxidation of Ge was recently shown to generate a stable LaGeOx layer with higher dielectric constant than GeO2 and similarly good electrical response . The LaGeOx/Ge interface then appears as an attractive configuration to investigate in its fundamental electrical properties in order to optimize the LaGeOx layer passivation performance. In this regard, the electrical activity of paramagnetic traps at the LaGeOx/Ge interface has been scrutinized by electrically detected magnetic resonance. Consistently with the atomic oxygen grown GeO2 , both Ge dangling bond and oxygen related defects can be observed and the latter one strikingly disappear after annealing at 300°C in 700 Torr O2 pressure for 20 min. This behavior is put in correlation with the admittance spectroscopy study of the interface trap distribution in either p- and n-type MOS capacitors separately incorporating as grown and annealed LaGeOx stacks. References: A. Dimoulas, et al, Appl. Phys. Lett. 96, 012902 (2010) S. Baldovino, et al, Appl. Phys. Lett. 96, 222110 (2010)
10:15 AM - P4.4
LaLuO3 as Gate Dielectric for Ge MOSFETs towards 1nm EOT.
Min Xu 1 , Yiqun Liu 2 , Chen Wang 1 , Roy Gordon 2 , Peide Ye 1 Show Abstract
1 ECE, Purdue, West Lafayette, Indiana, United States, 2 Chemistry and Chemical Biology, Harvard, Cambridge, Massachusetts, United States
LaLuO3 has a very high k value of 26~30. In this work, LaLuO3 films were grown on Ge(100) and Ge(111) substrates by atomic layer deposition (ALD) at 300 to 350 oC. Interestingly, the film was epitaxially grown on Ge(111) while it was amorphous on Ge(100) from the high-resolution cross-section TEM images. Systematically studies of C-V and G-V were done based on LaLuO3/Ge MIS structures at different temperatures, which indicated epitaxial LaLuO3 on Ge(111) had better interface property toward EC while not degrading the interface toward EV, compared to amorphous LaLuO3 on Ge(100). Therefore, it is a very promising high-k gate dielectric for future Ge CMOS application. We will also report on C-V and Ge MOSFETs results on EOT<1nm by utilizing in-situ WN gate electrode deposition.
10:30 AM - P4.5
Reduction in Interface State Density for High-k/III-V MOS Capacitors by Incorporation of InP Capping Layers Grown In-situ by MOVPE on In0.53Ga0.47As.
Eamon O'Connor 1 , Roger Nagle 1 , Kevin Thomas 1 , Emanuele Pelucchi 1 , Aileen O'Mahony 1 , Alan Blake 1 , Karim Cherkaoui 1 , Scott Monaghan 1 , Ian Povey 1 , Martyn Pemble 1 , Paul Hurley 1 Show Abstract
1 , Tyndall National Institute, Cork Ireland
The detrimental effect of high interface state density, Dit, on high-k/III-V device characteristics has motivated extensive research on passivation of the high-k/III-V interface in an attempt to reduce Dit. The interface chemistry for high-k materials on III-V substrates is more problematic than that for the traditional SiO2/Si system, with the possibility for more than one substrate element, and its native oxides, to contribute to interfacial defects. Any strategies to prevent or minimize uncontrolled oxidation of the III-V surface due to ambient exposure would be critical in realizing viable high-k/III-V metal-oxide-semiconductor field effect transistors (MOSFETs) for future CMOS applications. Recently, InP barrier layers have been observed to be beneficial as determined by improvements in MOSFET device performance [1-3]. The objective of this work is to build upon these publications to perform a detailed study of how the presence of the undoped InP capping layer affects the density of electrically active interface defects. The study involved Pd gate MOS capacitors with 8nm Al2O3 comprising both un-capped In0.53Ga0.47As and devices where nominally undoped InP capping layers of different thickness (0.6 nm, 2 nm) were grown in-situ on In0.53Ga0.47As by metal oxide vapour phase epitaxy (MOVPE). Multi-frequency capacitance voltage analysis, in conjunction with conductance analysis, indicate significant a reduction in interface state density for the samples capped with InP. In addition, the thicker 2 nm InP cap was more effective in reduction of Dit than the thinner 0.6nm InP cap. Detailed characterization of the interface state density and energy profile will be presented using both the Conductance Method and a temperature modified High-Low frequency capacitance method. [4, 5]. The effect of forming gas annealing treatment on the devices will also be presented, in addition to TEM micrographs of the Pd / 9nm Al2O3/ InP/ In0.53Ga0.47As structures.  Zhao et al. Appl. Phys. Lett. 94 193502 (2009) Zhao et al. Appl. Phys. Lett. 96 102101 (2010) M. Radosavljevic et al, presented at IEDM (2009) E. H. Nicollian and J. R. Brews, MOS Physics and Technology, New York, Wiley, (1982). E. O’Connor et al., J. of Appl. Phys., in press (2010).
10:45 AM - P4.6
Interface Properties of GeNx/Ge Fabricated by Electron-cyclotron-resonance Plasma Nitridation.
Yohei Otani 1 , Yukio Fukuda 1 , Tetsuya Sato 2 , Hiroshi Toyota 3 , Hiroshi Okamoto 3 , Toshiro Ono 3 Show Abstract
1 , Tokyo University of Science, Suwa, Chino, Nagano, Japan, 2 , University of Yamanashi, Kofu, Yamanashi, Japan, 3 , Hirosaki University, Hirosaki, Aomori, Japan
In this paper, we report on the interface properties of GeNx/Ge fabricated by the plasma nitridation of Ge surface using Electron-Cyclotron-Resonance (ECR) plasma technique with some process conditions. Al/Si3N4/GeNx/Ge gate stacks were fabricated by applying ECR plasma techniques. P-type Ge substrates were degreased with ethyl alcohol and etched in a dilute HF solution to remove residual surface native oxide before series of gate stack formation. Some Ge surfaces were oxidized by ECR oxygen plasma irradiation prior to the formation of dielectric layers. GeNx and Si3N4 layers were successively formed on Ge substrates by ECR nitrogen plasma irradiation and ECR sputtering, respectively, at temperatures from room temperature to 400oC. Following this, Al gate electrodes with an area of 5.4 × 10-4 cm2 were formed through a stencil mask by vacuum evaporation without substrate heating and followed by the forming gas annealing (FGA) at temperatures from 200oC to 500oC for 30 min in 10% H2+N2 ambient at 1 atm. The periods of ECR oxygen plasma irradiation prior to the gate dielectric stack formation, the temperatures of ECR nitrigen plasma irradiation and the temperatures of FGA affected the properties of the nitrided Ge surface, such as, interface state density (Dit), the flat-band voltage shift (ΔVFB) and the capacitance equivalent thickness (CET). The Dit values at the midgap of the Al/Si3N4/GeNx/Ge stacks fabricated without substrate heating decreased with an increase in the ECR plasma oxidation period (0, 30, 60 and 120 s) and showed the lowest with an oxidation time of 60 s. This fact shows that ECR oxygen irradiation onto the surface of Ge for an appropriate duration improves the GeNx/Ge interfaces. The Dit values of the Al/Si3N4/GeNx/Ge stacks fabricated without substrate heating decreased with an increase in the FGA temperature up to 400oC, although FGA at 500oC damaged gate electrodes and Dit could not be measured. From this result, we recognized the temperature of 400oC in the FGA process as a key temperature. We checked the gate stack formation temperature dependence of Dit concerning the samples irradiated by ECR oxygen plasma for 120 s prior to the gate dielectric formation and applied FGA at 400oC for 30 min. We confirmed that no substrate heating during formation of gate stacks is necessary for improving the interface properties of GeNx/Ge. Through above mentioned approach, we have succeeded in lowering Dit of GeNx/Ge interface to ~1 × 1011 cm-2eV-1. In summary, we reported on the interface properties of GeNx/Ge fabricated by the plasma nitridation of Ge surface using ECR plasma technique with some process conditions. We showed that the periods of ECR oxygen plasma irradiation prior to the gate dielectric stack formation, the temperatures of ECR plasma nitridation and the temperatures of FGA affected the properties of the GeNx/Ge interface.
11:30 AM - **P4.7
Integration of High-k Dielectrics on Germanium for High-performance MOS: The EOT vs. Mobility Challenge.
Matty Caymax 1 , Florence Bellenger 1 2 , Guy Brammertz 1 , Dennis Lin 1 , Laura Nyns 1 , Sonja Sioncke 1 , Kristin De Meyer 1 2 , Marc Heyns 1 3 Show Abstract
1 FPS, imec, Leuven Belgium, 2 Department of Electrical Engineering, KULeuven, Leuven Belgium, 3 Department of Metallurgy and Materials Engineering, KULeuven, Leuven Belgium
Germanium is the first candidate high-mobility channel material to replace silicon in high-performance MOS applications. Although many researchers in the field dislike(d) GeO2 for passivation of the germanium-dielectric interface for its thermal instability and water solubility, it has been shown that Ge/GeO2 interfaces can be of very high electrical quality. The major drawback is that its carrier mobility dwindles as EOT approaches 1 nm or less. Recent work on S passivation might point the way towards high mobility at low EOT. The major mechanism responsible for low mobility is Coulomb scattering on charges trapped at defects at or near the interface (apart from possible defects higher up in the oxide layer, which are ignored here for simplicity). We have found that Ge/GeO2/high-k interfaces are characterized by two different types of defects, located either at the very Ge surface (so-called interfacial states the density of which is expressed by Dit, with energy levels inside the germanium bandgap) and defects inside the dielectric but very close to the interface (within 0.7 to roughly 5 nm), so-called border traps. Most reports on germanium passivation in literature discuss only Dit (and Dit spectra vs. energy), but ignore the presence of border traps. These two types of defects can be observed in low frequency measurements (100 Hz) as an increased depletion capacitance (high mid-gap Dit) or stretch-out (high border trap density). Typically, extremely thin interfaces (basically, high-k dielectrics deposited straight on germanium in non-oxidizing conditions) show high mid-gap Dit and very few border traps, whereas minor oxidation of germanium, resulting in germanium oxide or oxy-sulfide, tends to decrease strongly Dit at the expense of high amounts of border traps. This behavior can be strongly modulated by the specific processing conditions, as will be discussed at the conference.Many of the features discussed in this report look similar to the very well-known Si/SiO2 MOS structure, where the behavior of defects upon specific processing steps is well understood and schematically depicted in the so-called Deal Triangle. The major differences between the silicon and germanium system are the lower Ge-O binding energy, the high vapor pressure of GeO, and the peculiar characteristics of hydrogen in germanium that make H-passivation not work, in contrast to silicon. A model will be presented that explains the behavior of most of the Ge/GeO2 and Ge/high-k interfaces, including aspects such as sulfur passivation, thick and thin germanium oxide layers, varying oxidation temperature, with or without anneal.
12:00 PM - **P4.8
Materials Issues in III-V P-Channel MOSFETs.
Serge Oktyabrsky 1 , Padmaja Nagaiah 1 , Michael Yakimov 1 , Hassa Bakhru 1 , Richard Moore 1 , Vadim Tokranov 1 Show Abstract
1 CNSE, University at Albany, Albany, New York, United States
Development of p-type MOSFETs using new materials is an important goal to provide a further scaling of CMOS circuits. Although bulk transport properties of Ge make it the main candidate for p-channel, strained III-As and, in particular, III-Sb are good competitors in particular for deeply scaled devices due to lower hole effective mass in strained III-V heterostructures, simplicity of band engineering with variety of material choices to create high barriers, reduce leakage, improve ohmic contacts, etc. The materials parameters affecting MOSFET’s figures-of-merit are reviewed with the emphasis on strain in quantum wells (QWs), effective mass, density of states and mobility. Interface properties of high-k oxides with low-In and high-In content InGaAs and InGaSb are reviewed. High-In InGaAs/InP are shown to have typically high interface state density close to the valence band. This along with the position of the charge neutrality level close to the conduction band makes the fabrication of p-MOSFETs an extremely challenging task. On the contrary, high performance (i) low-In InGaAs/GaAs and (ii) III-Sb channels are more realistic. CV, IV, Hall and transistor characteristics of MOS structures with these channel materials are demonstrated and correlated to XPS, SIMS and TEM results. (i) Interface passivation using thin (~0.5nm) in-situ Al layer for low-In InGaAs is proved to be as effective for p-type III-V similar to a-Si passivation for n-type. Al layer is oxidized to AlOx when HfO2 is deposited on top, and results in significant reduction of interface state density. (ii) Progress in development of materials for III-Sb channels is reported: optimization of strain in QWs using metamorphic superlattice buffers on GaAs and InP substrates, doping of source-drain regions by C- and Mg- implantation and Zn-diffusion from spin-on-glass, oxidation chemistry on n- and p-III-Sb surfaces and associated differences in CV’s, and resulting test transistor characteristics.
12:30 PM - P4.9
Interface Characterization of High-k Dielectric/Narrow Bandgap Semiconductor: ALD Al2O3 on InAs and InSb.
Chen Wang 1 , Kun Xu 1 , Min Xu 1 , Nathan Conrad 1 , Peide Ye 1 Show Abstract
1 , Purdue, West Lafayette, Indiana, United States
The bandgap of InAs and InSb is 0.35eV and 0.17eV, respectively. Due to their narrow bandgaps, the effect of minority carriers in these materials cannot be ignored at room temperature. This makes conventional room temperature CV measurement inappropriate for characterizing their interfaces. In this work, we use low temperatures (down to 10 K) to suppress the minority carrier response during interface characterization of ALD Al2O3/InAs and Al2O3/InSb. Clear accumulation, depletion and inversion features were observed at temperatures of up to 77 K. By combining with conductance measurement, interface trap densities of 1.4~4.0x1012/cm2-eV were characterized at Al2O3/InAs and Al2O3/InSb interfaces.
12:45 PM - P4.10
Origin of Schottky Barrier Height Shifts on Ge and GaAs by Inserting Thin Insulator Layers.
Liang Lin 1 , Stewart Clark 2 , John Robertson 1 Show Abstract
1 Engineering Dept,, Cambridge University, Cambridge United Kingdom, 2 Physics Dept, Durham University, Durham United Kingdom
The Schottky barrier heights (SBHs) of metals on high mobility semiconductors such as Ge or InGaAs are sometimes too high to allow low resistivity contacts. Most metals on Ge have a low p-type barrier height, whereas metals on some InGaAs alloys have a low n-type barrier. Experimentally, the insertion of ultra-thin (1 nm) layers of insulators such as SiNx or HfO2 can cause a large shift of SBHs on Ge from small p-type to small n-type [1-3]. The effect has been attributed to the ‘de-pinning’ of metal induced gap states (MIGS) by the insulator . We show by ab-initio calculations on supercells of a metal, oxide and Si, that the main effect is the introduction of an interface dipole at one interface and this shifts the overall SBH. The depinning effect does occur, but is of less importance. The calculations require the use of hybrid density functional methods, to give good semiconductor band gaps.1.T Nishimura, K Kita, A Toriumi, App Phys Express 1 051406 (2008)2 M Kobayashi, et al, J App Phys 105 023702 (2009)3.J Hu, K C Saraswat, H S P Wong, J App Phys 107 063712 (2010)
PeideD. Ye Purdue University
RobertM. Wallace University of Texas-Dallas
John Robertson Cambridge University
Shinichi Takagi The University of Tokyo
Kurt J. Lesker Company
Omicron NanoTechnology USA
P7: High K on III-V Semiconductors
Thursday PM, April 28, 2011
Room 3003 (Moscone West)
2:30 PM - **P7.1
Scaling of InGaAs MOSFETs into Deep Submicron Regime.
Yanqing Wu 1 , Jiangjiang Gu 2 , Peide Ye 2 Show Abstract
1 , IBM T.J. Watson Research Center, Yorktown Heights, New York, United States, 2 Electrical and Computer Engineering and Birck Nanotechnology Center, Purdue Univ., West lafayette, Indiana, United States
Research on III-V transistors for future high-speed and logic applications has attracted many efforts recently because of the high carrier mobility. Research work has been focused mainly on two categories: surface channel MOSFET and buried channel HEMT. Using similar operation principles as Si MOSFET, the first approach faces less scaling challenge and is our research focus of this abstract. However, many high mobility III-V materials such as InGaAs and InSb are narrow bandgap semiconductors. The short channel effects of deeply-scaled devices based on these channel materials are usually more severe. New process steps such as halo ion implantation and EOT scaling are implemented to improve the off-state performance of short channel devices. Also, for the first time, tri-gate structures using top-down approaches are implemented on III-V MOSFETs. The short channel effect of the inversion-mode deep submicron InGaAs MOSFETs can be greatly improved by using these approaches.
3:00 PM - P7.2
AlGaAs/GaAs Nanowire HEMT: Planar GaAs NW and AlGaAs Shell Interface Study.
Xin Miao 1 , Xiuling Li 1 Show Abstract
1 , University of Illinois, Urbana, Illinois, United States
Semiconductor nanowire has been studied extensively for next generation electronic devices because of the better gate control inherent to the three-dimensional geometry. Doping in nanowires however, has been challenging in terms of uniformity and controllability. We report the first bottom-up grown planar GaAs nanowire high electron mobility transistor (NW-HEMT) that consists of an undoped GaAs planar nanowire and a Si-doped AlGaAs shell. The GaAs nanowire was grown at 480°C using MOCVD via Au-catalyzed vapor-liquid-solid (VLS) mechanism, which was followed by the growth of a thin AlGaAs shell at >600 °C to suppress the VLS growth mode and promote 2-dimensional epitaxial overgrowth. Specifically, a 45nm Si-doped AlGaAs (x=0.35) was grown and capped by a 5 nm highly doped GaAs layer. The doping level of the AlGaAs was calibrated separately using a planar Hall sample to be 2 e17 cm-3. Gate recess was formed by selectively etching away GaAs vs AlGaAs using Citric: H2O2 (5:1) acid. Then gate metal was evaporated directly on AlGaAs. The separation between source and drain is 9 μm and gate length is 3 μm. The device works in enhancement mode with a threshold voltage of 0.65V. Excellent DC output and transfer characteristics have been measured, with transconductance gm of 80 mS/mm at Vds of 0.1 V, Ion/Ioff ratio of 1e7, and subthreshold slope of 79 mV/dec. The growth conditions of the AlGaAs shell have been varied to optimize the interface between the GaAs nanowire with a trapezoidal cross-section and the AlGaAs shell. Electrical characterization of HEMT devices with different interfaces will be discussed.
3:15 PM - P7.3
Influence of Trimethylaluminium (TMA) Exposure on the Growth and Electrical Characteristics of Gate Stacks.
Yoontae Hwang 1 , Roman Engel-Herbert 2 , Susanne Stemmer 1 Show Abstract
1 Materials Department, University of California, Santa Barbara, Santa Barbara, California, United States, 2 Department of Materials Science and Engineering, Pennsylvania State University, University Park, Pennsylvania, United States
Achieving low interface trap densities and low equivalent oxide thicknesses are still considered major challenges in the development of III-V MOSFETs. Numerous studies have investigated the influence of surface treatment prior to high-k deposition on these parameters. Here we investigate the influence of exposing In0.53Ga0.47As surfaces exhibiting different surface reconstructions with trimethylaluminum (TMA) prior to HfO2 gate dielectric deposition using chemical beam epitaxy. Interface trap densities and Fermi level efficiency of the gate stacks were analyzed using the conductance and Terman methods. Surfaces of As-decapped In0.53Ga0.47As layers on (001) InP were exposed to TMA for short times at substrate temperatures between 200 and 300 °C. The growth surfaces were monitored using reflection high-energy electron diffraction (RHEED). It is shown that the TMA dose, exposure time and substrate temperature critically influence the electrical properties of the gate stack, despite that fact that the TMA exposure was sufficiently short to have no apparent influence on the surface reconstructions seen in RHEED. For (2x4) reconstructed In0.53Ga0.47As surfaces TMA acted as surfactant, allowing for the growth of thin, coalesced HfO2 films using hafnium tert-butoxide as the source. These stacks could be scaled to equivalent oxide thicknesses of less than 1 nm. Without prior TMA exposure the HfO2 films grew columnar and were not coalesced up to 30 nm in thickness. For low TMA doses and in combination with post-deposition anneals in forming gas, interfaces with an unpinned Fermi level were obtained, showing a band bending corresponding to more than half of the band gap of In0.53Ga0.47As . For higher substrate temperatures and longer TMA exposure times, a much more pronounced midgap interface trap response was observed. For these stacks, the Fermi level was pinned near midgap even after forming gas anneals. For the group-III-rich, (4x2) reconstructed In0.53Ga0.47As surfaces, TMA had no effect on the growth of HfO2 films and did not act as a surfactant. We will discuss the mechanisms by which TMA and forming gas control the interface trap densities and Fermi level (un)pinning.  Y. Hwang, R. Engel-Herbert, N. G. Rudawski, S. Stemmer, Effect of post-deposition anneals on the Fermi level response of HfO2/In0.53Ga0.47As gate stacks, J. Appl. Phys. 108, 034111 (2010).
3:30 PM - P7.4
Optimizing Initial Cycles of Al2O3 ALD on InGaAs: Impact of Al(CH3)3 Dosage and In-line Monitoring by Auger Electron Spectroscopy.
Wipakorn Jevasuwan 1 , Yuji Urabe 1 , Tatsuro Maeda 1 , Noriyuki Miyata 1 , Tetsuji Yasuda 1 , Hisashi Yamada 2 , Masahiko Hata 2 , Noriyuki Taoka 3 , Mitsuru Takenaka 3 , Shinichi Takagi 3 Show Abstract
1 , National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki, Japan, 2 , Sumitomo Chemical Co. Ltd., Tsukuba, Ibaraki, Japan, 3 , The University of Tokyo, Bunkyo-ku, Tokyo, Japan
For the III-V channels to be successfully implemented in future devices, improvement of their MIS interfaces is one of the central issues. ALD of Al2O3 has the so-called self-cleaning effect which removes the native oxides on III-V’s . This effect suggests that the MIS interface properties may be improved by optimizing the initial ALD conditions independently from those for the bulk Al2O3 growth. However, there have been few studies addressing optimization of the initial cycles of ALD. In this paper, we report that a high Al(CH3)3 dosage (more than x100 w.r.t. the bulk ALD condition) in the first and second cycles of ALD effectively improves the MIS characteristics of Al2O3/InGaAs. In-line Auger analysis during the ALD processing showed that there is no oxygen uptake from the vapor phase in the first and second cycles, endorsing our approach of separating the interface-formation and bulk-growth stages in optimizing the ALD conditions. Experiments were carried out using the ALD system that is high-vacuum compatible and is equipped with an analysis chamber for AES . Al2O3 film growth was carried out using Al(CH3)3 (TMA) and H2O at 250 °C. The standard TMA dosage for the bulk-film growth was ~0.005 Pa.s, while high dosage (~0.5 Pa.s) was used in the initial cycles. The growth rate was 0.10 nm/cycle regardless of the TMA dosage. MIS capacitors were prepared with high TMA dosage in the initial cycles and standard dosage for the following cycles, keeping the total cycle number at 60. C-V measurements showed that the frequency dispersion (i.e., shift of the C-V curve as frequency was changed from 100 to 1 MHz) was reduced to ~70 mV by using the high dosage in the initial cycles, whereas the dispersion was as large as 190 mV when the initial cycles were performed with the standard dosage. The smaller frequency dispersion indicates the smaller interface traps densities. It was also observed that the high TMA dosage caused positive shifts in the flat band voltage by 0.1-0.2 V which were due to the interface dipoles of the interfacial Al-As bonds or negative fixed charges. Reduction of the frequency dispersion was most remarkable when the high TMA dosage was employed in the first and second cycles. The in-line AES analysis showed that the Al LMM signal was increased in proportion to the cycle number, whereas the O KLL signal was unchanged in the first and second cycles. These behaviors were observed for both NH4OH- and (NH4)2S-treated surfaces. These results indicate that TMA reacts with the InGaAs surface oxide to form the interface and oxygen uptake from the H2O vapor does not take place in these initial cycles. These C-V and AES results imply that the excessive TMA dosage in this interface-formation process is the key to form high-quality Al2O3/InGaAs MIS interfaces. This study was supported by NEDO.  C. L. Hinkle et al., Appl. Phys. Lett. 92, 071901 (2008);  T. Yasuda et al., Mater. Res. Soc. Symp. Proc. 1194E, A08-07-01~12 (2010).
3:45 PM - P7.5
Interface Composition of HfO2 and Al2O3 Thin Films on InAs Substrates and InAs Nanowires Studied by X-ray Photoemission Spectroscopy.
Rainer Timm 1 , Martin Hjort 1 , Alexander Fian 1 , Erik Lind 1 , Claes Thelander 1 , Jesper Andersen 1 , Lars-Erik Wernersson 1 , Anders Mikkelsen 1 Show Abstract
1 The Nanometer Structure Consortium, Department of Physics, Lund University, Lund Sweden
Thin high-κ oxide films on InAs, formed by atomic layer deposition (ALD), are the key to achieve high-speed metal-oxide-semiconductor devices. Thereby the quality of the interface between the semiconductor and the high-κ material is crucial for the device performance for bulk InAs substrates  as well as for InAs nanowires . X-ray photoemission spectroscopy (XPS) is a well-suited tool to investigate the chemical composition of the interface between III-V semiconductors and high-κ thin films, as has been shown in many cases for GaAs and InGaAs . However, although InAs has an even higher electron mobility and is an important binary reference material, only a few XPS studies on high-κ thin films on InAs(100) substrates have been reported yet . Here, we present a detailed XPS investigation on the interface between InAs and 2-nm-thick Al2O3 or HfO2 layers, deposited by ALD at different temperatures, for InAs substrates with different surface orientations as well as for InAs nanowires with different crystal structure. From XPS core-level spectra, obtained at the MAX-lab synchrotron facility, we can reveal the composition of the native oxide and obtain how the high-κ layer deposition reduces the different oxide components.By systematically comparing As 3d, In 3d, and In 4d spectra of an InAs reference sample with InAs/Al2O3 and InAs/HfO2 samples, a strong oxide reduction upon high-κ deposition is obtained. Two arsenic oxidation states (As+3 and As+5) can be distinguished, and their peaks in both high-κ samples have typically less than 10% the size of the corresponding peak in the reference sample. The reduction of the In-oxide component typically only reaches about 50%, except for an InAs/Al2O3 sample with low-temperature ALD, leading to strong In-oxide reduction . In this case, however, a thin AlAs film is observed at the interface. The oxide reduction is generally strongest on (100) substrates, while the interface stoichiometry on (111)A or (111)B substrates reflects the original surface termination.With the high X-ray intensity of a synchrotron, we were also able to study the interface of HfO2 and Al2O3 layers on InAs nanowires. The nanowires were grown by metalorganic vapour phase epitaxy using Au seed particles and then deposited on Si substrates for XPS. All nanowire samples exhibit larger oxide peaks than the corresponding bulk (100) samples, which is partly due to the different geometry of planar surfaces and nanowires in the XPS experiment. Nanowires in the Wurtzite crystal structure contain less oxide than Zinkblende nanowires. Importantly, also for the InAs nanowires, a significant reduction of the native oxide upon deposition of HfO2 and especially Al2O3 is obtained. E. Lind et al., Appl. Phys. Lett. 96, 233507 (2010).  S. Roddaro et al., Appl. Phys. Lett. 92, 253509 (2008). R. M. Wallace et al., MRS Bulletin 34, 493 (2009). R. Timm et al., Appl. Phys. Lett. 97, 132904 (2010).
4:30 PM - P7.6
Probing the Metal Gate High K Interactions by Backside XPS and C-AFM.
Wilfried Vandervorst 1 2 , Umberto Celano 1 , Thierry Conard 1 , Thomas Hantschel 1 Show Abstract
1 mca, imec, leuven Belgium, 2 IKS, KULeuven, leuven Belgium
The metal gate high k interaction is one of the dominant processes influencing the electrical performance (Vt, charge accumulation,..) of advanced gate stacks. These interactions are influenced by the entire thermal budget and the presence of reactive elements (on top/ within the material gate) such that relevant measurements can only be performed after a full processing cycle and on a compete gate stack. In such cases the relevant metal gate high k interface is a buried interface buried located below the metal gate (+ Si cap) and is not accessible for standard characterization methods like XPS due the limited escape depth of the photoelectrons. Moreover the presence of conductive metal gate prevents the application of techniques such as C-AFM, to probe the local distribution of the defects, trapping sites and local degradation upon stressing. XPS in combination with layer removal steps like ion beam sputtering will destroy the bonding information and is thus not applicable. Chemical etching of the metal gate stack prior to the XPS measurements requires an extremely precious control of the etching in order to stop 1-2 nm before the high k metal interface. As an alternative we have developed a backside removal approach whereby the underlying Si substrate is removed through a combination of polishing and final etching. The latter is selective and stops at the SiO2 interface. This is a severe refinement of the backside SIMS approach where normally still 100-200 nm of Si substrate are left. In our approach all the (non-oxidized Si) is removed whereby the surface roughness of the etched samples is less than 1 nm rms. The limited dielectricum thickness (2-3 nm) brings now the high k metal interface within the sampling volume of XPS . An analysis of a TiN-HfSiO2 gate stack demonstrates now the expected oxidation bonds but also highlights the presence of additional Hf-N bonds resulting from an interaction of the TiN with the high k material. Most likely the latter is the result of the energetic interaction during the PVD TiN deposition process as studied by a comparison to a stack produced with an ALD TiN-process.The complete removal of the Si from the substrate makes the samples also usable for (backside) C-AFM measurements and enables the probing of the nanoscopic distribution of electronic defects and charge trapping sites. The latter becomes extremely interesting as the inverted stack allows to tunnel through the high k layer (+ interface) into the metal gate thereby probing the electronic properties of the metal high k interface and the presence of defects within the entire high k film. Having established the procedures on Si -based metal gate stacks, we will demonstrate its applicability to SiGe-based gate stacks as well.
4:45 PM - P7.7
Interfacial Reaction Induced GeO Desorption, GeO2 Crystallization and Non-uniform Void Formation in GeO2/Ge Stack.
Shengkai Wang 1 , Koji Kita 1 2 , Tomonori Nishimura 1 2 , Kosuke Nagashio 1 2 , Akira Toriumi 1 2 Show Abstract
1 Department of Materials Engineering, The University of Tokyo, Tokyo Japan, 2 , JST-CREST, Tokyo Japan
Germanium attracts much attention because of its high mobility than silicon for the sub-22nm node. However, interfacial reaction between GeO2 and Ge hampers the development of Ge-MOSFETs because it severely degrades the quality of GeO2 films and GeO2/Ge interface. Although various methods have been applied on the quality control of dielectric and interface, how the interfacial reaction affects on the GeO2 and GeO2/Ge interface is still unclear. For further quality enhancement and from the viewpoint of materials science study of GeO2/Ge system, it is necessary to reveal the interfacial reaction mechanism and the kinetic effects induced by the interfacial reaction.In this paper, we investigate the interfacial reaction between GeO2 and Ge. Through comparing the reaction kinetics between GeO desorption and Ge oxidation on differently oriented substrates, the interfacial reaction has been revealed to be a redox reaction with oxygen vacancy generation. Moreover, three aspects that induced from the interfacial reaction are discussed, (i) GeO desorption; (ii) structural transition of GeO2 (iii) void formation in GeO2. First of all, by the 18O and 73Ge isotope tracing technique, together with the thermal desorption spectroscopy analysis, the kinetic model of GeO desorption from GeO2/Ge stack is proposed. In our model, oxygen vacancy diffusion from GeO2/Ge interface to the GeO2 surface is considered. And GeO desorption is attributed to the reduction of GeO2 by oxygen vacancy at the GeO2 surface region. Moreover, amorphous to α-quartz like phase transition, assisted by interfacial reaction, has been observed by x-ray diffraction in GeO2/Ge after receiving vacuum annealing whereas no crystallization of GeO2 could be observed on SiO2 under the same condition. This implies the crystallization barrier is reduced under the help of interface reaction and the structural variation is also responsible for quality degradation in GeO2/Ge stack. In addition, non-uniform void formation in GeO2 has been studied by taking account of both GeO desorption kinetic model and the interface assisted GeO2 crystallization. We infer that the void formation is ascribed to the faster diffusion of oxygen vacancy in the destructive grain boundary area. Although no diffraction peak has ever been observed for thin GeO2 on Ge, we think the disorder-order transition still happens intrinsically but not dominantly. At this time, observable crystalline GeO2 is hard to form because GeO desorption consumes the GeO2 dominantly. These understandings in GeO2/Ge strongly indicate that Ge MOSFET performance can be pushed ahead with suppressing the oxygen vacancy concentration in GeO2.
5:00 PM - P7.8
Direct Measurement of Inversion Charge Density in Enhancement-mode GaAs and InP Field-effect Transistors with Al2O3 Gate Dielectric Using Gated-hall-Bar Structures.
Davood Shahrjerdi 1 , Bahman Hekmatshoar 2 , Junghyo Nah 1 , Emanuel Tutuc 1 , Sanjay Banerjee 1 Show Abstract
1 Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, United States, 2 Electrical Engineering, Princeton University , Princeton, New Jersey, United States
III-V materials are being extensively explored as alternative channel materials for post-Si CMOS applications due to their high intrinsic electron mobility. Proper surface passivation of III-V materials has long been a key challenge for realization of high-performance III-V MOSFETs. However, the presence of significant charge traps at the interface can result in erroneous calculation of effective channel mobility using conventional split C-V method. Therefore, to determine the carrier mobility in III-V MOSFETs with high-k gate dielectrics, a direct measurement of inversion charge density (Qinv) is necessary. In this work, for the first time, we have used gated Hall bars (GHB) to directly measure Qinv and mobility in GaAs- and InP-channel FETs. The GHB devices were fabricated on (001) SI-GaAs and InP substrates with 8nm of ALD-Al2O3 gate dielectric. The electrical characteristics of the devices were carefully examined. The split C-V data indicates the presence of fast interface traps, evident from the frequency dispersion of the C-V curves. The presence of slow ‘border’ traps was examined using pulsed I-V and stress measurements. We will show that border traps can further complicate the Hall measurements. Therefore, we have developed a special procedure to alleviate the effect of slow traps during the Hall and four-point measurements. The Hall resistance (RH) was measured at different gate voltages, sweeping the magnetic field (B). The Qinv was extracted from the slope of the RH-B curves at different gate voltages, indicating a relatively low Qinv by comparison to the expected values from split C-V data, indicating significant charge trapping in our high-k/III-V FETs.Another advantage of the GHB structure is the elimination of the parasitic effect of the source/drain series resistance on the extracted mobility through four-point measurements. The mobility was evaluated using the measured mobile charges in the channel in combination with the corresponding intrinsic channel resistance (Rint=[qnμH]-1). The peak Hall channel mobility of GaAs and InP transistors was measured to be ~2140 and ~1925 cm2/V.s, respectively. It is notable that the field-effect mobility for our devices (extracted from the slope of their corresponding Id-Vg curves assuming ideal MOS equations) is much lower (~100 and ~300 cm2/V.s for GaAs and InP, respectively). These data indicate that substantial charge trapping can be the major cause for the significant degradation of the DC characteristics of our III-V FETs, as well as in many other reports in the literature. In summary, we have directly measured the inversion charge density and the corresponding intrinsic channel mobility for self-aligned E-mode high-k GaAs and InP FETs using gated Hall bars.
5:15 PM - P7.9
Ultra-thin III-V on Insulator (XOI) Layers for High-performance and Low-power Transistors.
Rehan Kapadia 1 , Kuniharu Takei 1 , Hyunhyub Ko 1 , Steven Chuang 1 , Hui Fang 1 , Paul Leu 1 , Kartik Ganapathi 1 , Elena Plis 2 , Ha Sul Kim 1 , Szu-Ying Chen 3 , Morten Madsen 1 , Alexandra Ford 1 , Yu-Lun Chueh 3 , Sayeef Salahuddin 1 , Sanjay Krishna 2 , Ali Javey 1 Show Abstract
1 Electrical Engineering, University of California Berkeley, Berkeley, California, United States, 2 Center for High Technology Materials, University of New Mexico, Albuquerque, New Mexico, United States, 3 Material Science and Engineering, National Tsing Hua University, Hsinchu Taiwan
Due to scaling limitation of Si based devices, high mobility compound semiconductors are heavily studied for channel materials. It is particularly desirable to integrate compound semiconductors on Si, as this takes advantage of the established Si processing infrastructure and combines it with the high mobility of III-V semiconductors. However, the conventional approach of heteroepitaxial growth presents significant fabrication challenges as well as issues in terms of junction leakage and defect densities. To overcome these limitations, we have developed an epitaxial layer transfer technique to assemble ultra-thin,single crystalline InAs films onto Si/SiO2 substrates. As a parallel to silicon-on-insulator (SOI) technology, we use the abbreviation “XOI” to represent our compound semiconductor-on-insulator platform. The electron transport properties of InAs XOI devices, including the dominant role of quantum confinement, are characterized through experiments and simulations. Importantly, the growth of a thermal InAsOx layer is shown to significantly improve the InAs/dielectric interface, allowing for a low interface trap density of ~10^11 states/eV-cm^2. The fabricated XOI MOSFETs demonstrate excellent performance, with a peak transconductance of ~1.6 mS/µm, a subthreshold swing of 107 mV/decade, field effect mobilities up to 5500 cm^2/V-s, and on off ratios of 10^4 at a channel length of ~0.5 µm.The novel technology platform demonstrated here enables the direct integration of III-V transistors on Si with excellent materials and device properties. In the future, by the integration of both p- and n- type materials, high performance III-V circuits on Si would be enabled.References: H. Ko, K. Takei, R. Kapadia, et. al. Nature, in press, 2010.
5:30 PM - P7.10
Wafer Bonded Ge-Si Heterostructure for Avalanche Photodiode Application.
Ki Yeol Byun 1 , John Hayes 1 , Farzan Gity 1 , Brian Corbett 1 , Cindy Colinge 1 Show Abstract
1 , Tyndall National Institute, Cork, na, Ireland
Avalanche photodiodes (APDs) have been used widely in optical communication systems to detect and amplify weak optical signals using the internal gain provided by the impact ionization process. These components have been available for several years from the III/V semiconductor technology on InP and GaAs wafers. Nevertheless, the integration of these devices on large wafers within the mainstream silicon technology requires either high-cost hybrid integration approach or back-end technology. The integration of germanium into silicon increases absorption, leading to possible photodetection at telecommunication wavelengths (from 1.31um to 1.55um). Recently, it has been demonstrated that pure germanium can be a promising candidate as a broadband photodetector [1,2]. Furthermore, germanium has a direct energy bandgap of 0.8 eV and is compatible with the CMOS technology. However, conventional epitaxial Ge growth requires careful processing and device design to minimize the impact of the dislocations because it is well known that defects and dislocations are generation centers that contribute to the leakage current in minority carrier devices. In this work, we propose an alternative method for producing the Ge-Si APDs which has, potentially, less defective interfaces and employs a low thermal budget. Chemical and electrical investigations show that successful low temperature Ge to Si wafer bonding can be achieved for avalanche photodiode integration. The effects of the germanium surface passivation are determined using angle-resolved x-ray photoelectron spectroscopy. Based on the surface chemistry of the germanium surface, we investigate the properties of the buried interface as a function of passivation techniques. Characterization of the Ge-Si hetero-junction is achieved by measuring the forward and reverse currents and comparing the results with TCAD simulation. We show the performance can be further enhanced by reducing the interface oxide.Reference: S. Assefa, F. Xia, and Y. Vlasov, Nature 464, 80 (2010). Y. Kang, H. Liu, M. Morse, M. Paniccia, M. Zadka, S. Litski, G. Sarid, A. Pauchard, Y. Kuo, H. Chen, W. Zaoui, J. Bowers, A. Beling, D. McIntosh, X. Zheng and J. Campbell, Nature Photon..3, 59 (2008). L. Colace, G. Masini A. Altieri, and G. Assanto, IEEE Photon. Technol. Lett. 18, 1094 (2006).
5:45 PM - P7.11
Effect of Interface Defects and Record High Peak Tunnel Current Density in Si-based Tunnel Diodes Grown by RTCVD.
Jiun-Yun Li 1 2 , James Sturm 1 2 , Isaac Lauer 3 , Steve Koester 3 4 Show Abstract
1 Electrical Engineering, Princeton University, Princeton, New Jersey, United States, 2 Princenton Institute for the Science and Technology of Materials, Princeton University, Princeton, New Jersey, United States, 3 T.J. Watson Research Center, IBM, Yorktown Heights, New York, United States, 4 Electrical and Computer Engineering, University of Minnesota, Minneapolis, Minnesota, United States
There has been a great interest in SiGe/Si tunneling FETs (TFETs) for sharp subthreshold slopes (< 60 mV/decade) [1,2]. A key issue underlying this novel FET design is the fundamental quantitative understanding of band-to-band tunneling (BTBT) in SiGe/Si heterojunctions. This is necessary to predict possible maximum drive current and to calibrate numerical device simulations. Because it is difficult in practice to separate BTBT and defect-assisted tunneling (DAT) currents in reverse bias of tunnel diodes (where the TFETs operate), in this study we focus on the negative differential resistance (NDR) region in forward bias where the peak current is due to BTBT. Two major results are presented: (i) the annealing effect to reduce junction defects and thus the DAT current, which is monotonic in I-V and masks the NDR, and (ii) the highest peak current density (PCD) of 8 kA/cm2 in the NDR region among Si-based tunnel diodes grown by CVD to date, 40 times higher than in previous record .In first experiment, p+Si0.7Ge0.3 (boron level ~ 1 x 1020cm-3) epitaxial layers were grown by RTCVD at 625oC on phosphorus-implanted (2 x 1020 cm-3) n-Si wafers. Before growth, a 5 min in-situ H2 annealing step was performed in the CVD reactor at various temperatures to remove implant damage and to clean the surface. Diodes were made by mesa etching with Ti/Al contacts. NDR was observed for annealing temperatures of 800 to 950oC, with a maximum peak/valley current ratio (PVCR) ~ 2 and PCD ~ 0.3 kA/cm2 at 900oC. For anneal below 900oC, the DAT current dominates due to an incomplete removal of junction defects. Above 900oC, both the PVCR and PCD drop due to a lower surface phosphorus concentration by diffusion and evaporation. Less surface doping, which defines the n-side of tunnel junction, leads to a lower junction field and a higher tunnel barrier and thus less BTBT. Similar samples implanted through a screen oxide had a high level of background oxygen after annealing due to the knock-on effect (6 x 1020 cm-3). These diodes and those without screen oxide have similar NDR properties, implying the residual oxygen does not contribute the DAT current.To avoid high temperature annealing, which leads to a higher tunnel barrier, we then continuously grew strained p+Si0.7Ge0.3/n+Si0.7Ge0.3 epitaxial layers on Si substrates at 625oC in CVD reactor without implantation. NDR was observed without any annealing to remove junction defects. For the same doping levels as our earlier experiments, the PCD rose to 1.8 kA/cm2 with the PVCR of 2.8. As the p-type doping was increased by three times, the PCD was 8 kA/cm2 with its PVCR of 3.5, a current density 40 times higher than in previous Si-based tunnel diodes, where at least one side of the junction was grown by CVD . Choi et al, IEEE Electron Device Letters, v. 28, p. 743, 2007 Bhuwalka et al., Japanese Journal Applied Physics, v. 43, p. 4073, 2004 Li et al., 67th Annual Device Research Conference, p. 99, 2009