Orlando Auciello Argonne National Laboratory
Panagiotis Dimitrakis Institute of Microelectronics
Yoshihisa Fujisaki Hitachi Ltd.
Eisuke Tokumitsu Tokyo Institute of Technology
Dirk Wouters IMEC
Applied Materials Inc
M. Watanabe &
Park Systems Corporation
Universal Systems Co., Ltd
Q1: Advanced Flash and Nano-Floating Gate Memories
Tuesday AM, April 26, 2011
Room 3002 (Moscone West)
9:30 AM - **Q1.1
Scaling Challenges for NAND and Replacement Memory Technology.
Kirk Prall 1 Show Abstract
1 , Micron Technology, Boise, Idaho, United States
As the industry scales NAND memory technology below 20nm feature sizes many fundamental scaling challenges occur. A NAND cell is typically the smallest MOSFET transistor in production. The architecture of the NAND array allow direct measurement of each transistor in a 32 Gigabit array. The NAND cell is a very useful device for examining nano-scale behavior. A few of the fundamental scaling challenges caused by nano-scale behaviour facing NAND memory technology will be reviewed. The first topic presented will be the reduction in the number of electrons required for cell operation due to scaling. The number of electrons required is proportional to the cell capacitance which is proportional to the area of the cell. At a 20nm feature size the number of electrons per state in the cell is approximately 30. The lack of electrons in the cell causes numerous noise related problems. Parasitic electron trapping dominates cell operation over electrons trapped on the floating gate and requires careful optimization of the dielectrics to improve trapping. The second topic reviewed will cover dopant fluctuations and related giant random telegraph signal (RTS) noise. At a feature size of 20nm the number of boron dopant atoms in a cell is about 70 atoms per cell. The statistics of ion implantation cause a large variation of approximately 35% in the number of dopant atoms per cell. This problem causes large variation in cell performance. The giant RTS problem is caused by the unlucky occurrence of an electron trap over a conducting filament relatively free of boron atoms. The third topic covered will be the program noise problem caused by random tunneling events on the floating gate which also add additional variation to the cell. During each program or erase tunneling event a different number of electrons tunnel through the tunnel oxide resulting in random threshold voltage shifts. The second half of the presentation will cover key issues related to potential NAND replacement technologies. The cross-point memory is the favored candidate for NAND replacement. The major challenges related to cross-point memories will be discussed. The economic challenges for a cross-point memory consist of several issues: increased process cost due to the need to stack multiple memory layers, the costly and uncertain lithography roadmap, etc.. The memory element requirements include a large dynamic resistance, the need for deterministic behavior, ability to function as a multilevel cell, energy limitations (current, voltage, and power), cycling capability, and data retention. The diode requirements for a cross point memory include: low voltage operation, high current carrying capacity, stability and low temperature formation. The materials challenges for a successful RRAM element will be presented including filamentary and uniform systems.
10:00 AM - Q1.2
Effect of Hydrogen on Charge Trapping Behavior of Metal-oxide-nitride-oxide-silicon Nonvolatile Memory Devices.
Nam Nguyen 1 , Gang He 1 , Markus Wilde 2 , Ziyuan Liu 3 , Toyohiro Chikyow 1 Show Abstract
1 , National Institute for Materials Science, Tsukuba, Ibaraki, Japan, 2 Institute of Industrial Science, University of Tokyo, Tokyo Japan, 3 , NEC Electronics Corporation, Kawasaki, Kanagawa, Japan
Metal-Oxide-Nitride-Oxide-Silicon (MONOS) charge-trapping nonvolatile memory devices have emerged as a potential for charge-storage media due to their simple cell structure, compatibility with the conventional CMOS technology and their potential for large scalability. These devices, however, still suffer from reliability problems, such as a short data retention time and gate leakage current. In addition, electrical performance of these devices has been shown to be greatly affected by the depth distribution of hydrogen (H) atoms at the oxide/nitride interfacial layers. The observed H accumulation at the interfaces implies the need for a better fundamental understanding on the role of hydrogen in these devices. In this work, the effect of hydrogen on MONOS-based memory devices was investigated. We focused on the H-retaining property of Al2O3/Si3N4/SiO2/Si and Al2O3/SiAlON/Si3N4/SiO2/Si stacks grown by combinatorial pulsed laser deposition technique. The interfacial structure along with the chemical composition, thickness of MONOS stacks were analyzed using X-ray photoelectron spectroscopy (XPS), Transmission Electron Microscopy (TEM), and the H distribution in the stacks were analyzed using nuclear reaction analysis (NRA). The results demonstrated that an interfacial layer with chemical formula of SiAlON that was purposely introduced between Al2O3 and Si3N4 can effective block H species from diffusing to bottom oxide and thus leads to improve electrical performance of MONOS memory devices.
10:15 AM - Q1.3
Investigation of SiO2/HfO2 Stacks for Flash Memory Applications.
Bhaswar Chakrabarti 1 , Heesoo Kang 3 , Adam Pirkle 1 , Barry Brennan 1 , Stephen Mcdonnell 1 , Nhan Nguyen 4 , Robert Wallace 1 2 , Eric Vogel 1 2 Show Abstract
1 Materials Science and Engineering, University of Texas at Dallas, Richardson, Texas, United States, 3 Flash Core Technology Lab, Samsung Electronics Co. Ltd., Hwasung City, Gyonggi-Do, Korea (the Republic of), 4 , National Institute of Standards and Technology, Gaithersburg, Maryland, United States, 2 Electrical Engineering, University of Texas at Dallas, Richardson, Texas, United States
Tunnel-barrier engineered (TBE) structures have been proposed to enable continued scaling of the flash memory tunnel dielectric. Despite theoretical prediction of significant retention and programming improvement with these structures, experimental observations have produced mixed results. While some show performance improvement, several other reports indicate poor performance in such stacks due to presence of charge traps in the high-K layer. To optimize performance it is necessary to understand the role of parameters such as high-K layer thickness, annealing temperature, annealing gas etc on the electrical characteristics of these structures. In this work we have studied the effect of these parameters on the performance of SiO2/HfO2 gate stacks by electrical and physical characterization techniques. Results show increasing trap assisted tunneling in these structures with increasing thickness of the HfO2 layer. Our calculations also indicate that it is necessary to reduce the EOT in order to achieve better program current compared to single layer SiO2. Effects of annealing conditions were studied using spectroscopic ellipsometry, x-ray diffraction analysis and x-ray photoelectron spectroscopy. This work was supported by the Korea Electronics Technology Institute FUSION program.REFERENCES: K.K. Likharev, Layered tunnel barriers for nonvolatile memory devices. Applied Physics Letters, 1998. 73: p. 2137-2139. K.K. Likharev, Riding the crest of a new wave memory[NOVORAM]. IEEE Circuits and Devices, 2000. 16(4): p. 16-21. E.M. Vogel et. al., Modeled Tunnel Currents for High Dielectric Constant Dielectrics. IEEE Transactions on Electron Devices, 1998. 45(6): p. 1350-1355. J. Buckley et. al., Investigation of SiO2/HfO2 gate stacks for application to non-volatile memory devices. Solid-State Electronics, 2005. 49(11): p. 1833-1840. F. Irrera, Engineered Barriers with Hafnium Oxide for Nonvolatile application. IEEE Transactions on Electron Devices, 2006. 53(9): p. 2418-2422.
11:00 AM - Q1.4
Growth and In-line Characterization of Silicon Nanodots Integrated in Discrete Charge Trapping Non-volatiles Memories.
Julien Amouroux 1 2 3 , Vincenzo Della Marca 1 2 3 , Philippe Boivin 1 , Philippe Maillot 1 , Christophe Muller 2 , Damien Deleruyelle 2 , Eric Jalaguier 3 , Jean-Philippe Colonna 3 Show Abstract
1 R&D, STMicroelectronics, Rousset CEDEX France, 2 , Institut Matériaux Microélectronique Nanosciences de Provence, UMR CNRS 6242, Marseille France, 3 , CEA / LETI MINATEC, Grenoble France
Non-Volatiles Memories (NVM) integrating Silicon Dots (SDs) are considered as an emerging solution on Flash memories fabrication process. SDs are used as discrete traps for injected charges in replacement of the conventional polysilicon floating gate. Silicon NanoDots integration enables reliability performances improvement in terms of endurance and retention. Furthermore, since Si nanodots are isolated, the robustness to parasitic cross-talk is increased and the sensitivity to defects within tunnel oxide is lowered. Si-dots integration is fully compatible with CMOS processes and tools. Since SDs with diameter around 10 nm cover a drastically smaller area than a continuous polysilicon gate in Flash memories, node downscaling is thus possible. Moreover, the decrease in the number of needed photolithography masks brings a reduction in wafer cost.Si-dots were grown by Low Pressure Chemical Vapor Deposition (LPCVD) on top of the tunnel oxide. Depending on the pre-growth surface treatment, tunnel oxide surface may present either siloxane or silanol groups. A chemical reaction on SiO2 during tunnel oxide cleaning increases the number of silanol groups which are used as nucleation sites. SDs deposition relies on a 2–steps process: nucleation by SiH4 and selective growth with SiH2Cl2.In a context of technology industrialization, it is of primary importance to develop in-line metrology tools dedicated to Si dots growth process control. Hence, Si dots were observed in top view by using an in-line Critical Dimension Scanning Electron Microscopy CDSEM and their average size and density were extracted using image processing. This technique showed satisfactory results for small SDs (<5nm) at high density (1012 dots/cm2). In addition, Haze measurement, generally used for bare silicon surface characterization, was customized to quantify Si-dots deposition uniformity over the wafer. A correlation between Haze value and nanodots density and size determined by CDSEM was made possible. Finally, spectroscopic ellipsometry was used to measure an average equivalent Silicon Dots layer thickness which could be linked to dots size and density. To complement physical characterization, memory cells with SDs charge trapping were electrically characterized with a peculiar attention paid toward the cycling endurance by combining fast program/erase operations.Considering these encouraging results, optimization of Si dots size and density is in progress to improve the electrical performances and other process integration trials (tunnel oxide, SDs passivation…) are developed to enhance the electrical robustness.
11:15 AM - Q1.5
Immersion-plated Gold Nanocrystal Embedded in LaxO1-x for Nonvolatile Memory.
Che-Wei Chen 1 , Chun-Hu Cheng 1 , Hung-Chung Yu 1 , Gia-Yeh Huang 2 , Nian-Huei Chen 1 , Albert Chin 3 , Fon-Shan Huang 1 Show Abstract
1 Institute of Electronics Engineering, National Tsing Hua University, Hsinchu Taiwan, 2 Department of Power Mechanical Engineering, National Tsing Hua University, Hsinchu Taiwan, 3 Department of Electronics Engineering, National Chiao Tung University, Hsinchu Taiwan
A simple, low cost and high throughput immersion plating for the fabrication of gold nanocrystal (Au NCs) and Al/LaxO1-x/Au NCs/SiO2/p-Si MOS capacitor structure for nonvolatile memory (NVM) are reported. Au metal has high work function of 5.1 eV which can make deep level traps and can enhance the data retention of NVM device performance. Furthermore, it is also known that the smaller sizes and higher density of Au NCs can achieve large memory window. Immersion plating method has an advantage to control the size and density of Au NCs by adjusting the concentration of plating solution and plating time. The interfaces between tunnel dielectric and plated Au NCs can be better than that of Au fabricated by sputter-deposition method. Meanwhile, the integration of high-k blocking dielectric of LaxO1-x can enhance the voltage drop across the tunnel dielectric, consequently, results in high injection current and fast program/erase (P/E) speed. The tunnel dielectric, SiO2, was thermally grown on RCA cleaned n-type, (100)-oriented Si wafer with thickness of 5 nm. The 2 nm amorphous silicon (a-Si) was then deposited by LPCVD. A large number of kinks on the surface of a-Si provide suitable sites for Au NCs nucleation during immersion plating. The plating solution was mixture of 0.48 mM HAuCl4/1.5 mM Hf and immersed into solution for 1~3 s. Further, we investigate the influence of Au NCs annealing step on electric property of NVM MOS capacitor. After Au NCs formation (sample A1), the annealing process of 200 oC for 30 min in N2 ambient was performed (sample A2). For control dielectric layer, the thickness of 30 nm LaxO1-x was deposited by e-gun deposition. The samples were annealed at 400 oC for 10 min after LaxO1-x deposition. After Al electrodes deposited by evaporator with 300 nm thickness, the Al/LaxO1-x(30 nm)/AuNCs/SiO2(5 nm)/p-Si capacitor was finished. From SEM inspection, the size of Au NCs were 5-10 nm with density about 9×1010~1×1011. Further, the HR-TEM image shows the cross-section view of Al/LaxO1-x(30 nm)/Au NCs/SiO2(5 nm)/p-Si capacitor. The Au NCs were embedded in LaxO1-x and located above the tunnel SiO2. For P/E speed measurement, sample A1 and A2 were programmed at equal Vg of 10 V for 10 and 5 ms and resulted in memory windows of 0.9 and 1.4 V. Afterwards, A1 and A2 were erased at identical Vg of -12 V for 1 s and 250 ms to return initial state of NVM device. The Au NCs annealed sample shows higher P/E speed than unannealed device. This might be explained by tunnel mechanism of samples. We find that F-N tunneling of A2 can start at lower Vg than that of A1. It might be due to the grain size of A2 (after annealing) is larger than that in A1. The effective dielectric thickness of A2 is smaller than that in A1. So, the electric field in SiO2 (tunnel oxide) of A2 is higher than that in A1, enhances the F-N current and increases the P/E speed. Further study is still under investigated.
11:30 AM - Q1.6
MOCVD Al0.39O0.6 N0.01/Al-rich Al0.4O0.45N0.15/Al0.4O0.4N0.2 with High Density Aluminum Nanocrystal for Nonvolatile Memory.
Nian-Huei Chen 1 , Hung-Chung Yu 1 , Gia-Yeh Huang 2 , Fon-Shan Huang 1 Show Abstract
1 Institute of Electronics Engineering, National Tsing Hua University, Hsinchu Taiwan, 2 Department of Power Mechanical Engineering, National Tsing Hua University, Hsinchu Taiwan
Due to the good interface between aluminum (Al) and Al-based dielectrics, the low cost Al NCs embedded in high-k dielectrics such as AlN and Al2O3 is promising for nonvolatile memory. Compared with Al2O3, AlN has lower barrier height of 2.2eV for hole injection from Si substrate and results in fast program/erase (P/E) speed. For long retention time, there is higher barrier height of 5.5eV for hole at Al NCs and Al2O3 interface. In this work, a simple RTA-MOCVD system is utilized to deposit high density Al NCs in Al0.39O0.6N0.01/Al-rich Al0.4O0.45N0.15/Al0.4O0.4N0.2 layered structure on SiO2/n-Si wafer without breaking vacuum for nonvolatile memory. The Al-rich AlON contains excess Al NCs is utilized for charge storage layer. In order to achieve fast P/E speed and long retention time, a barrier-engineering technique by modulating NH3 ratio during AlN deposition to form tunnel and control dielectric tended to be rich in AlN and in Al2O3 is also reported. The crystalline properties and film composition of memory layered structure were analyzed from GIXRD and Auger. The grain size of Al NCs and thickness of each layer in capacitor were measured by TEM. The high frequency (1MHz) capacitance-voltage (C–V) tests were utilized to determine the memory window, retention and endurance characteristics of memory capacitor.The SiO2 was thermally grown on RCA cleaned n-type, (100)-oriented Si wafer with thickness of 4 nm. Then AlOxNy /Al-rich AlOaNb / AlOmNn layered structure was deposited on SiO2/n-Si substrate using RTA-MOCVD system. Precursor TMAl which is carried by Ar mixed with NH3 with ratio of 1:5~1:20 was operated at pressure of 0.1-5torr and temperature of 600-900oC for deposition. The Al electrodes were formed by evaporator-deposition with 200nm thickness and lift-off process. The element ratio of sample was conducted by Auger depth profiling. It is found that there are Al, O, N element with 40%,40%,20% and 39%,60%,1% existing in tunnel and control dielectric. From GIXRD analysis, the tunnel dielectric shows amorphous layer, however, there are Al2O3 (217)(214) peaks in control dielectric. For Al-rich layer, it indicates Al (200)(220) orientation which is consistent with selected area diffraction pattern in TEM. The plan-view TEM images show Al NCs with size of 2-13nm and density of 1.13×1013/cm2 in Al-rich films. Though larger Al NCs size of 8-13nm can be observed, there is mixing with a great number of 2-3nm Al NCs. Further, from cross-section view TEM image, the sample has the structure of Al0.39O0.6N0.01 (18nm) / Al-rich Al0.4O0.45N0.15 (31nm) / Al0.4O0.4N0.2 (3nm) / SiO2 (4nm) / n-Si. For memory measurement, there are 1.1 and 1.45V flat-band shift after program with -15V for 100ms and erase with 15V for 10ms. After 105s data retention, the charge loss are about 7.2% and 12.4%. In order to evaluate the reliability, the memory device was performed with a high number of P/E cycle. After 50000 P/E cycles, only 8% window narrowing can be observed.
11:45 AM - Q1.7
Matrix Density Effect on Morphology of Germanium Nanocrystals Embedded In Silicon Dioxide Thin Films.
Arif Alagoz 1 2 , Mustafa Genisel 3 4 , Sean Foss 5 , Terje Finstad 5 , Rasit Turan 2 Show Abstract
1 Applied Science, University of Arkansas at Little Rock, Little Rock, Arkansas, United States, 2 Physics, Middle East Technical University, Ankara Turkey, 3 Chemistry, Middle East Technical University, Ankara Turkey, 4 Chemistry, Bilkent University, Ankara Turkey, 5 Physics, University of Oslo, Oslo Norway
Flash type electronic memories are the preferred format in code storage at complex programs running on fast processors and larger media files in portable electronics due to fast write/read operations, long rewrite life, high density and low cost of fabrication. Scaling limitations of top-down fabrication approaches can be overcome in next generation flash memories by replacing continuous floating gate with array of nanocrystals. Germanium (Ge) is a good candidate for nanocrystal based flash memories due its small band gap. In this work, we present effect of silicon dioxide (SiO2) host matrix density on Ge nanocrystals morphology. Low density Ge+SiO2 layers are deposited between high density SiO2 layers by using off-angle magnetron sputter deposition. After high temperature post-annealing, faceted and elongated Ge nanocrystals formation is observed in low density layers. Effects of Ge concentration and annealing temperature on nanocrystal morphology and mean size were investigated by using transmission electron microscopy. Positive correlation between stress development and nanocrystal size is observed at Raman spectroscopy measurements. We concluded that non-uniform stress distribution on nanocrystals during growth is responsible from faceted and elongated nanocrystal morphology.
12:00 PM - Q1.8
Temperature Effect on Charge Transportation Mechanism of Nanocrystals Embedded High-k Nonvolatile Memory Devices.
Chia-Han Yang 1 2 , Yue Kuo 1 , Chen-Han Lin 1 , Way Kuo 3 Show Abstract
1 Thin Film Nano & Microelectronics Research Lab, Texas A&M University, College Station , Texas, United States, 2 Department of Industrial and Information Engineering, University of Tennessee, Knoxville, Tennessee, United States, 3 , City University of Hong Kong, Hong Kong Hong Kong
The nanocrystalline Indium Tin Oxide (ITO) embedded in Zr-doped HfO2 (ZrHfO) high-k dielectric can trap a large number of charges with a long retention time . Reliability issues related its breakdown mechanism and the relaxation current decay with time have been studied [2,3]. In this paper, authors investigated the thermal effect on its performance and reliability. The result showed under the high temperature condition, the magnitude of the memory window increased while the charge decay rate also increased. Additionally, the loss of the trapped charges increased with the increase of temperature, i.e., 34.8%, 64% and 92% at 25°C, 75°C and 125°C, respectively after a long stand-by period, e.g., 10 hours. The temperature influenced the retention of both the deeply- and loosely-trapped charges. The time required for the total loss of the trapped charges decreased from over 10 years at 25°C to 270 days at 75°C and 1.67 days at 125°C. The thermal effect of the charge transportation mechanism in the nc-ITO embedded sample was analyzed using the ln(J/E) vs. E1/2 curve (Poole-Frenkel relation). The result showed that the onset of the Poole-Frenkel (P-F) tunneling was greatly dependent on the temperature. For example, it started at Vg = 1V, 2.3V, and 2.4V under 25°C, 75°C and 125°C, respectively. Hence, the P-F tunneling does not dominate the charge transportation mechanism at the high temperature. Other mechanisms such as direct tunneling or Schottky emission are not negligible. Authors acknowledge the support of NSF CMMI-0926379 project.  A. Birge and Y. Kuo, J. Electrochem. Soc., 154, H887 (2007).  C.-H. Yang, Y. Kuo, R. Wan, C.-H. Lin, and W. Kuo, IEEE 46th Intl. Rel. Phys. Symp., 46 (2008).  C.-H. Yang, et al., MRS Proc., 1071, F02-09 (2008).
12:15 PM - Q1.9
Ordered Arrays of Silicon Nanocrystals by Block Copolymer Lithography.
Michele Perego 1 , Gabriele Seguini 1 , Andrea Andreozzi 1 , Emanuele Poliani 1 , Gerard BenAssayag 2 , Sylvie Schamm-Chardon 2 , Paolo Pellegrino 3 Show Abstract
1 , Laboratorio MDM, IMM-CNR, Agrate Brianza Italy, 2 , CEMES-CNRS and Univ. de Toulouse, nMat grou, Toulouse France, 3 , University of Barcelona, Barcelona Spain
Silicon nanocrystals attracted a lot of attention for their potential use as charge trapping elements in non volatile memory devices. Despite the wide interest of the scientific community, all the effort to implement Si nanocrystals in mass storage memory devices have been frustrated by the difficulties related to the control of the lateral dispersion of the nanocrystals; random distributions can induce fluctuation in device performances due to variations in the number of Si nanocrystals and consequently of trapping elements for each memory cell. Moreover, due to the irregular distribution of Si nanoparticles, non uniform channel inversion can be induced with the formation of conductive paths between source and drain that inhibit device functionality. Despite these limitations Si nanocrystals (diameter ≤15 nm) based memories have already been introduced for embedded memory applications. In order to increase the scaling capabilities of these devices and to explore the possibility to introduce them in mass storage architectures, more accurate control on Si nanocrystal size and positioning is required. In this work block copolymer lithography is used to fabricate 2 dimensional ordered arrays of Si nanocrystals. Under suitable processing conditions asymmetric polystyrene-b-poly(methylmethacrylate) (PS-b-PMMA) copolymer thin films naturally self organize forming a PS matrix with hexagonally close-packed PMMA cylinder patterns, perpendicularly oriented with respect to the substrate. After selective removal of PMMA component a nano-porous PS soft mask is formed. The diameter of the pores is about 17 nm and the pitch around 33 nm. The polymeric soft mask is used as template for the deposition of Si or SiO dots with dimensions, density and lateral distribution that closely resembles the original nano-porous template. Subsequent thermal treatment at high temperatures (1050°C, 30 min, N2) induces crystallization of Si dots or nucleation and growth of Si nanocrystals within the SiO dots. Detailed analysis of the characteristics (size, density and in plane distribution) of the silicon nanocrystals population is performed combining different characterization techniques (SEM, AFM, ToF-SIMS, TEM). Informations about their functional properties are provided as well. This research activity was funded by the ERANET PLUS “NanoSci-E+” consortium through the NANO-BLOCK project.References S. Tiwari et al., Appl. Phys. Lett. 68, 1377 (1996) C.M. Compagnoni et al. J. Nanosci and Nanotech 7, 193 (2007)
12:30 PM - Q1.10
Permittivity and Band Gap Enhancement by Doping Optimization for Charge Trap Memory Blocking Oxides.
Junko Nakatsuru 1 , Naomu Kitano 1 , Takashi Nakagawa 1 , Toru Tatsumi 1 , Jimmy Price 2 , David Glimer 2 Show Abstract
1 , Canon ANELVA, Kawasaki Japan, 2 , SEMATECH, Austin, Texas, United States
MANOS (Metal/Al2O3/Si3N4/SiO2/p-Si) structure for charge trap memory is one of the promising types of nonvolatile semiconductor memory. For faster readout and higher reliability in memory devices, equivalent oxide thickness (EOT) scaling and good retention at high temperatures are greatly desired. The development of metal oxides with high permittivity and wide band gap is key to realizing such requirements. Permittivities depend on the crystalline phase which closely relates with doping materials and concentration  .In this study, we evaluated Al2O3, AlSiOx, and HfAlON films using DC reactive co-sputtering with Ar, O2 and N2 as process gasses. The effect of doping materials and concentration on permittivity and the band gap were investigated. As for permittivity, we evaluated the effect of Al and N doping concentration on HfOx. On the other hand, we optimized Si doping for band gap enhancement of Al2O3. Al and Si concentrations were controlled by the sputtering power of Al or Si targets. X-ray photoelectron spectroscopy (XPS) and X-ray diffractometry (XRD) were used to characterize the dielectric films. Metal/dielectric films/SiO2 stacks were prepared for capacitance-voltage (C-V) characterization.The atomic concentration of Al in HfAlON was controlled from 0 to 14 at.% by Al sputtering power. HfAlON films with 2 to 6 at.% Al were crystallized by annealing at 1000 degrees C. The films exhibited a cubic phase as compared to HfOx which shows a monoclinic phase for the same annealing temperature. With optimum Al and N concentrations, a very high permittivity near k ~ 50 was obtained. Sputtered Al2O3 was amorphous and crystallized to γ- Al2O3 after 1000 degree C annealing as confirmed by XRD. The crystallized film showed the same permittivity and band gap as ALCVD Al2O3 . AlSiOx (0-30 at.% Si) films were also crystallized after 1000 degree C annealing. The phase of Si-doped Al2O3 changed from γ- Al2O3 to aluminum silicate-based crystals above 10 at.% Si doping. The band gap of AlSiOx was increased by 0.07eV by 0-10 at.% Si doping while maintaining a high permittivity. Moreover, the leakage current decreased with increasing doped Si concentration for the same EOT. In addition, EOT-Jg improved. However, further increasing the Si contents led to degradation in band gap energy and permittivity. In conclusion, we have evaluated the dependence of permittivity and band gap with doping material and concentration. We have demonstrated significantly increased permittivity with HfAlON and band gap enhancement with AlSiOx at optimum doping concentrations. More details of these materials will be discussed in the presentation. A. Toriumi et al, IEDM 2007, pp.53 T.S. Bösche at al, IEEE 2006  Jang-Sik Lee at al, JJAP Vol.45, No.4B, 2006, pp.3213
12:45 PM - Q1.11
Simulation and Experiment of Core Shell Nanocrystal Nonvolatile Memory.
Huimei Zhou 1 , Jianlin Liu 1 Show Abstract
1 Dept of Electrical Engineering, UC Riverside, Riverside, California, United States
Nanocrystal (NC) floating gate memory devices have attracted considerable attention due to excellent memory performance and high scalability 1-2. Double Si NCs, Ge NCs, metal NCs, silicide NCs, and dielectric NCs, have been proposed to achieve memory devices with longer retention3-5. Here we demonstrated metal/high-K core shell NC memory device. The representative metal and high-K materials are cobalt and Al2O3, respectively. At the same time, Schrodinger’s and Poisson-Boltzmann’s equations are combined to calculate the energy band distribution in writing and erasing processes by self-consistent calculation in 1-Dimension. The results show that core shell structure improves the device performance compared with NCs without shell. The electrical potential Φ(with respective to the substrate potential) satisfies the Poisson-Boltzmann’s equation: ▽●(ε▽Φ)=q(p-n+D) . The electron density in the NC is determined by the Schrodinger’s equation: -h2(d2u/dx2)/2m+V(X)u(x)=Eu(x). The device parameters for the simulation are the same as those in fabricated devices with 6nm NC size, 3nm tunnel oxide, 15nm control oxide and the calculation stops as maximum difference between successive potential distributions is 1mV.The fabricated memories were characterized by Agilent 4284A LCR meter and pulse generator at room temperature. Transient characteristics of the core-shell NC memoires show fast writing/erasing speeds and long retention performance. The calculated conduction band edges for the memory devices with the embedded core shell NCs indicate voltage distribution in the writing and erasing biases, respectively. As a high-k material, the shell does not bear much electric field and most of the voltage is still dropped on the SiO2 layer. Compared with experiment result, theoretical analysis clarifies the physical mechanism in the writing and erasing processes of core shell NC memory devices. The result indicates that the core shell NCs improve the retention performance of the device.REFERENCE:1T. Mikolajick and C. Pinnow, Materials for Information Technology, Engineering Materials and Processes, Part II, 111, (2005).2 Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, Jpn. J. Appl. Phys., 38, 2453 (1999).3 Singh P K, Bisht G, Hofmann R, Singh K, Krishna N, Mahapatra S, Electron Device Letters, IEEE , 29 , 1389, (2008).4 F.M. Yang, T.C. Chang, Po-Tsun Liu, Y.H Yeh, Y.C. Yu, J.Y. Ling, S.M. Sze and J.C. Lou, Thin Solid Films 516, 360, (2007).5P. K. Singh, G. Bisht, R. Hofmann, K. Singh, N. Krishna, S. Mahapatra, Electron Device Letters, IEEE , 29, 1389, (2008).
Q2: Ferroelectric Memories
Tuesday PM, April 26, 2011
Room 3002 (Moscone West)
2:30 PM - **Q2.1
Embedded Ferroelectric Random-Access Memory – Technology and Applications.
Ted Moise 1 Show Abstract
1 Analog Technology Development, Texas Instruments, Dallas, Texas, United States
Since 2007, Texas Instruments has manufactured and sold millions of chips that include high-density, embedded ferroelectric random-access memory (eFRAM). This cost-effective, non-volatile memory technology complements conventional CMOS logic by adding distinct capabilities including high-endurance data storage, fast-write data protection, secure data protection, and low-power operation. eFRAM operates at low voltage (1.5V) and, unlike floating-gate devices, does not require power-consuming charge pumps. The memory is fabricated within a low-leakage 130nm 5LM Cu interconnect CMOS logic process. In this presentation, the process steps and integration approach required to create eFRAM will be shown. The electrical and reliability properties of the memory will also be reviewed. The combination of fast-write capabilities, low-power operation, and nearly-infinite write endurance enable eFRAM to be used in wide variety of applications. The application space and advantages of this technology relative to conventional non-volatile memories will also be presented.
3:00 PM - **Q2.2
Recent Progress in Downsizing FeFETs for Fe-NAND Application.
Shigeki Sakai 1 , Mitsue Takahashi 1 , Van Hai Le 1 Show Abstract
1 , National Institute of Advanced Industrial Science and Technology, Tsukuba Japan
NAND flash memories are popular high-density nonvolatile memories used in mobile digital equipments and solid state drives (SSDs). However conventional floating-gate (FG) type NAND is insufficient for high-spec SSDs because the FG-NAND has poor program-and-erase (P/E) endurance of 1E+04 times and large program voltage of 20V. In 2008 we introduced a novel NAND flash memory named Fe-NAND which uses ferroelectric-gate field effect transistors (FeFETs) as memory cells [1,2]. The Fe-NAND has potential advantages over the conventional FG-NAND, which are higher endurance than 1E+08 times and lower operation voltages than 6V. The Fe-NAND is scalable by 4F2 rule as well as the FG-NAND because a memory unit of the Fe-NAND is one FeFET. Capacitance-coupling noise problem for the Fe-NAND will be less serious than for the FG-NAND even when they are downsized in the future because permittivity of gate oxides in an Fe-NAND cell is much higher than a permittivity of an inter-cell insulator between neighbor Fe-NAND cells. Experimentally we confirmed good electrical properties of Pt/SrBi2Ta2O9(SBT)/Hf-Al-O/Si FeFETs as Fe-NAND memory cells: high P/E endurance over 1E+08 times at 6V-and-10µs bipolar-pulsed program/erase voltage, long retentions measured over 1 month, small distribution of threshold voltages (Vths), long retentions at 85°C and 120°C, and good Vth controllability by ion implantation into channel regions. Very recently we succeeded in fabricating 0.56 µm-gate-length FeFETs with good retention characteristics. This was the world’s smallest FeFET with good retention. The gate lengths were evaluated by scanning electron microscopic views of the FeFET gate cross sections. Inclination angles of the etched SBT sidewall were 76°. The FeFETs with 0.56 µm gate length showed steep drain current vs. gate voltage (Id-Vg) hysteresis curves with subthreshold swing values of S = 115 mV/decade and a memory window of 0.93 V at Vg = 1±5 V. Good endurance performance was demonstrated by applying 1E+08 cycles of +6 V and -4 V bipolar pulses with 20 µs period on the FeFET gates. The endurance test indicated program/erase cycles of the FeNAND will be 1E+04 times as large as that of conventional NAND flash memory. The FeFETs also showed good Id retention with 1E+04 on/off- Id ratio for 1E+05 s. Not only single memory cell but also integrated circuits of the Fe-NAND are now being investigated. We fabricated Fe-NAND memory arrays and experimentally demonstrated the block erase, page program and nondestructive read a of a miniature 4 × 2 Fe-NAND cell array. Bit-line read-out-current distribution for programmed patterns of the 4 × 2 Fe-NAND cell array successfully showed two distinguishable “0” and “1” states.  S. Sakai, et al. 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings 2008, 103-105.  AIST press release, http://www.aist.go.jp/aist_e/latest_research/2008/20080624/20080624.html
3:30 PM - **Q2.3
Passive Matrix Non-volatile Ferroelectric Polymer Memory: The Keys to Making it Work.
Nicklas Johansson 1 , Christer Karlsson 1 , Per Bröms 1 , OlleJonny Hagel 1 , Anders Hägerström 1 , Grzegorz Greczynski 2 Show Abstract
1 , Thin Film Electronics, Linköping Sweden, 2 Department of Physics, Linköping University, Linköping Sweden
With increasing demand for low-cost memory and the emergence of roll-to-roll printing as a commercial fabrication method, there is renewed interest in ferroelectric passive matrices as a memory architecture. The lack of active circuitry within the memory gives superior packaging density as well as a simple architecture. Logic and memory may be printed in separate optimized processes, easing integration into complete electronic devices. The main challenge with a passive matrix memory architecture is that all cells are connected in series and parallel. This causes disturb fields on non-addressed cells during reading and writing. These disturbs may result in the loss of data content. By choosing the proper ferroelectric material, optimal processing conditions, and suitable electrodes, it is possible to create cells defined by the crossing of metal lines sandwiching the memory film. One such class of ferroelectric materials are the P(VDF-TrFE) copolymers which naturally crystallize in a ferroelectric state. Using this polymer, it is possible to adjust the drive protocol to keep the disturb voltage on non-addressed cells below a critical threshold. Under these conditions, and with proper initialization (or polling) it is possible to achieve vast memory array size, memory bit access times of less than 50 μs, more than 1e9 read/write cycles and seemingly unlimited retention. To guarantee low-cost printing, the most prominent parameters are the simplicity of the memory cell and array architecture, the stability of the P(VDF-TrFE) copolymers, and PET-compatible low-temperature processing.
4:30 PM - **Q2.4
Nanoscale Studies of Ferroelectric Domains for Future Non-volatile Memories.
Seungbum Hong 1 , Orlando Auciello 1 2 , Leo Ocola 2 , Ramesh Nath 1 3 , Moonkyu Park 1 4 , Jeffrey Klug 1 , Mengchun Pan 1 5 , Martin Holt 2 , Alexandra Joshi-Imre 2 , Kwangsoo No 4 , Ram Katiyar 3 , Amanda Petford-Long 2 Show Abstract
1 Materials Science Division, Argonne National Laboratory, Lemont, Illinois, United States, 2 Center for Nanoscale Materials, Argonne National Laboratory, Lemont, Illinois, United States, 3 Institute of Functional Materials, University of Puerto Rico , San Juan , Puerto Rico, United States, 4 Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejon Korea (the Republic of), 5 Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois, United States
Multiferroic nanostructures have received great attention due to their complex and emergent properties that could potentially lead to disruptive leap in the memory density. Here we present our current understanding of structure-property relationship with special emphasis on ferroic domain structures and dynamics at both micron and nanometer scales in multiferroic nanostructures or heterostructures such as BiFeO3/SrRuO3/SrTiO3 and PbTiO3/CoFe2O4/SrRuO3/SrTiO3 systems. Various characterization techniques including piezoresponse force microscopy (PFM), transmission electron microscopy (TEM) and x-ray nanoprobe have been used to give fuller picture behind emergent properties and phenomena observed in the model systems. Possible device structures based on the multiferroic materials will also be discussed.
5:00 PM - Q2.5
Lanthanum Oxide Capping Layer for Solution-processed Ferroelectric-gate Thin-film Transistors.
Phan Trong Tue 1 , Trinh Bui Nguyen 2 , Takaaki Miyasako 2 , Thanh Pham 1 , Eisuke Tokumitsu 3 2 , Tatsuya Shimoda 1 2 Show Abstract
1 School of Materials Science, Japan Advanced Institute of Science and Technology, Nomi, Ishikawa, Japan, 2 ERATO, Shimoda Nano-Liquid Process Project, Japan Science and Technology Agency, Nomi, Ishikawa, Japan, 3 Precision and Intelligence Laboratory, Tokyo Institute of Technology, Tokyo Japan
Recently, the use of indium-tin-oxide (ITO) as a channel layer and ferroelectric (Bi,La)4Ti3O12 (BLT) or Pb(Zr,Ti)O3 (PZT) film as a gate insulator has been shown as promising candidates for the ferroelectric-gate thin-film transistors (FGTs). In general, the use of PZT is preferred to BLT because of its advantages, such as higher remanent polarization, lower crystallization temperature and more flat surface. However, interdiffusion or reaction between solution-processed ITO and PZT layers is easy to occur even at low process-temperature of 450oC. This results in a degradation of ITO quality and poor ITO/PZT interface property. Thus, preventing the interdiffusion and reaction is critical to realize the good interface property which is inevitable for obtaining good retention characteristics.It is well established that lanthanum oxide (LO) is a high-κ insulator (ε ~ 27) with lattice constant (3.937-4.05 Å) similar to that of PZT (4.03 Å). It is also thermodynamically stable without forming an interface layer when placed in contact with PZT. Another key criterion for the selection of LO is the high band offset barrier which reduces the conduction current of electrons and holes. Based on these considerations, in this study we propose the use of a LO as a capping layer between ITO and PZT to prevent the reaction and interdiffusion between these layers, as well as to improve the retention properties. The cross-section TEM image of the ITO/LO/PZT structure revealed an atomically flat interface with no defective layer. In addition, high uniformity of PZT layer and negligible interdiffusion between ITO and PZT layers were confirmed by the high angle annular dark field scanning TEM image and energy dispersive X-ray spectroscopy. In contrast, in the conventional ITO/PZT structure there existed an interlayer of about 7-10 nm at the ITO/PZT interface. And also it was found that in 20-nm-PZT surface layer, Pb and Ti atoms diffused out (10-20 at % loss), and further 10 at % of Pb entered the ITO layer. Such diffusion seriously degraded ITO properties as well as FGT performance in the conventional structure, but was completely prevented in the case of ITO/LO/PZT structure. These results suggest that the LO layer acting as a good barrier not only prevents the reaction between ITO and PZT layers but also stabilize the PZT structure against the out-diffusion of Pb, Zr and Ti. Interestingly, an amount of La (3-5 at %) was observed to diffuse into the PZT layer, which is believed to be another reason of improved stability of PZT structure. As a result, the fabricated ITO/LO/PZT FGT devices exhibit excellent performance with high “ON/OFF” current ratio and large memory window in range of 1E6-1E8 and 2-4 V, respectively. Furthermore, an improved data retention time is also experimentally demonstrated due to the good interface properties between the ITO and PZT layers. This type of FGT can be a good candidate for next-generation ferroelectric random access memory.
5:15 PM - Q2.6
Nanoscale Resolved Growth Dynamics During Switching in Memory Materials.
Nicholoas Polomoff 1 , Atif Rakin 1 , Sungjun Lee 2 , Joseph Desmarais 1 , Catherine Czaja 1 , Bryan Huey 1 Show Abstract
1 Institute of Materials Science, University of Connecticut, Storrs, Connecticut, United States, 2 Division of Physical Metallurgy, Korea Research Institute of Standards and Science, Daejeon Korea (the Republic of)
The activation energy landscape for switching between states in data storage materials dictates the ultimate switching speed. Nucleation energies for switching are easily determined by mapping hysteresis energies between states, but resolving local growth velocities and directions for this process is a challenge due to experimental limitations for coupled high spatial and temporal resolution measurements. A recently developed high speed variation of Atomic Force Microscopy enables such investigations, applied here to map the evolution of switching for ensembles of domains in ferroelectrics. Strategies for enhancing switching speeds with an overall decrease in energy consumption result.
5:30 PM - Q2.7
3-D BaTiO3-MWNT Nanoscale Capacitors by a Novel Deposition Technique.
Sai Shivareddy 1 , Youngjin Choi 1 , Gehan Amaratunga 1 Show Abstract
1 Engineering , University of Cambridge, Cambridge United Kingdom
The integration of high dielectric constant perovskite and ferroelectric materials onto three dimensional metallic nanostructures is investigated in the context of next generation ferroelectric memories and DRAMs. Multiwalled carbon nanotubes (MWNTs) are attractive electrode materials in the development of three dimensional architectures. The high aspect ratio of nanotubes results in a large surface area that is exploited only when there is a conformal deposition of the insulator material in the Metal-Insulator-Metal structure. Here, we report a simple low cost solution process to conformaly coat MWCNTs with Barium titanate thin films. MWNTs are grown in a highly oriented manner on e-beam patterned catalyst dots on P-Si by a DC PECVD technique. The MWNT array on P-Si dictates the geometry of the bottom electrode. A thin insulator film of BaTiO3 is deposited on the nanotube array by a combination of elect rophoresis and sol-gel techniques. Due to the metallic nature of MWNTs, the nanotube array forms one of the electrode in the electrophoresis setup with stainless steel being the opposite electrode. BaTiO3 nanoparticles (Aldrich, ~60nm) are suspended in a solution of 2-Methoxyethanol and acetylacetone by ultrasonication. Electrophoresis is done under a DC bias across the electrodes to obtain a conformal layer of BaTiO3 nanoparticles on the nanotube array. The film deposition rate can be controlled by the concentration of the suspension and field strength. To make the BaTiO3 film dense, a thin sol-gel film, from a diluted stock solution of BatiO3 sol is spun on the BaTiO3 nanoparticle layer, and annealed at 700 deg C to obtain the desired properties of the insulator film. Top electrode is deposited by evaporating aluminium. The physical and electrical properties of the device are also presented.
5:45 PM - Q2.8
Flexible Ferroelectric(PZT) Thin Film Capacitor on Plastic Substrate.
Jonghyun Rho 1 , Sang Jin Kim 3 , Wook Heo 1 , Nae-Eung Lee 1 , Hwan-Soo Lee 3 , Jong-Hyun Ahn 1 2 Show Abstract
1 Advanced Materials Science and Engineering,Center for Human Interface Nanotechnology, Sungkyunkwan Univ., Suwon, Gyeonggi, Korea (the Republic of), 3 Advanced Materials Laboratory, Samsung Electro-Mechanics, Suwon, Gyeonggy, Korea (the Republic of), 2 SKKU Advanced Institute of Nanotechnology, Sungkyunkwan Univ., Suwon, Gyeonggy, Korea (the Republic of)
We investigated the fabrication of high performance flexible ferroelectric(PZT) capacitor on plastic substrate. The ferroelectric active layer was formed between Pt electrodes by Sol-Gel method on sacrificial(a-Si) and buffer(SiO2) layer. These ferroelectric capacitors were patterned by general photolithography and dry etching process with optimized layouts. After etching and sacrificial layer removing process, these capacitors were transferred on plastic substrate using dry transfer method. The electrical properties of transferred ferroelectric capacitors were similar to that of general ferroelectric devices on rigid substrate. These properties suggest promising applications in flexible electronic systems.
Orlando Auciello Argonne National Laboratory
Panagiotis Dimitrakis Institute of Microelectronics
Yoshihisa Fujisaki Hitachi Ltd.
Eisuke Tokumitsu Tokyo Institute of Technology
Dirk Wouters IMEC
Applied Materials Inc
M. Watanabe &
Park Systems Corporation
Universal Systems Co., Ltd
Q6: Poster Session: Emerging Non-Volatile Memories
Wednesday PM, April 27, 2011
Salons 7-9 (Marriott)
1:00 AM -
Q6.5 transferred to Q2.8
9:00 PM - Q6.1
Charge-trapping Memory Devices with Oxide Nanocrystals Precipitated from High-k Dielectric Films.
Jiang Yin 1 Show Abstract
1 Dept. of Phys./National Laboratory of Solid State Microstructures, Nanjing University, Nanjing, Jiangsu, China
Non-volatile flash memory devices with discrete charge-trapping layers are currently attracting significant attention due to the widespread practical use and the compatibility with the traditional complementary metal-oxide-semiconductor(CMOS) technology. The investigation of embedding semiconducting or metallic nanoclusters in a SiO2 amorphous matrix as charge storage has been widely completed. The main problem for these charge trapping memory devices is the limited retention time basically due to charge loss by leakage current through the ultra-thin SiO2 tunneling layer although the replacement of the continuous polysilicon layer of a conventional flash memory device by a 2-dimentional nanoparticle array exhibits several advantages. One of the possible solutions to this problem is to increase the thickness of the tunneling oxide layer, which results in the higher operating voltages and the reduced write and erase speed. Several high-k materials have been employed as the tunneling oxide layer to realize the low-voltage charge trapping memory devices. Besides the tunneling layer, the parameters of the charge trapping layers, such as the size, structural stability and distribution of the nano-crystals of metal or semiconductors also play a critical role in the performance of the charge trapping memory devices. To improve the parameters of the charge trapping layers and increase the amount of the memory capacity controllably, we report novel charge-trapping memory devices with hetero-structures Pt/ZrSiOx/Si0.2Zr0.8Ox/ZrSiOx/p-Si(100) and Pt/Al2O3/Ti0.25Al0.75Ox/Al2O3//p-Si(100). The Si0.2Zr0.8Ox and Ti0.25Al0.75Ox films suffer chemical phase separation to precipitated SiO2 and TiAl2O5 nanocrystals after annealed at high temperature. SiO2 and TiAl2O5 nanocrystals were employed as the charge trapping sites in each device. In the charge storage layers, ZrO2 and TiAl2O5 nano-crystals as identified by using high resolution transmission microscopy(HRTEM) were well encapsulated by the amorphous matrix. A memory window of about 3 V with a stored electron density of about 1×1013 cm-2 was obtained for ZrO2 nano-crystal device, and a 2.3V memory with a stored electron density of about 1×1013 cm-2 was obtained for TiAl2O5 nanocrystal device. The retention properties of the devices as characterized at different temperatures reach 10 years with a tolerable degradation. Our approach provides significant advantage in fabricating non-volatile charge-trapping memory devices with a simple structure and a precisely controllable technique.
9:00 PM - Q6.10
A Study on the Growth and Annealing Characterization of Mutiferroic ZnO : Ti Films.
Youngmin Lee 1 , Han Tae Ryu 1 , Sejoon Lee 2 , Jin Young Lee 1 , Deuk Young Kim 1 Show Abstract
1 Semiconductor Science, Dongguk university, Seoul Korea (the Republic of), 2 Quantum-functional Semiconductor Research Center, Dongguk University, Seoul Korea (the Republic of)
Ti doped ZnO films were prepared on Pt(111)/Ti/SiO2/Si(001) substrates by simultaneous RF magnetron sputtering of ZnO and DC magnetron sputtering of Ti and which were annealed at 600 to 900°C increased of 50°C step during 3min.Effect of post-annealing on the structural, magnetic and electric properties of Ti doped ZnO films were investigated.X-ray diffraction results indicated that there are not any secondary phases and Ti2+ substituted for Zn2+ of ZnO host under annealed at 700°C but Ti-Oxided phases were detected at above 700°C. at 650°C samples have most strong c-axis preference and crystallinity. Magnetic hysteresis loops were observed in as-grown sample and annealed samples(600, 650, 700°C). Magnetic properties was increased with in the annealing temperature until 650°C. The increase in magnetic properties can be explained as a result of the enhanced crystal magnetic anisotropy. For I-V measurement results electric hysteresis loops were observed. As grown sample have 0.63V memory window as annealing temperature increases, electric hysteresis loops and memory window was decreased. And electric hysteresis loops was disappeared above at 700°C. As the thermal temperature increase, the decrease of lattice distortion and the formation of Ti-Oxide start to occur, resulting in going down the number of electrical dipoles.
9:00 PM - Q6.11
Transition Metal-Doped Transparent Conducting Oxides as Promising Building Blocks for Spintronic Materials.
Shokouh Sadat Farvid 1 , Pavle Radovanovic 1 Show Abstract
1 Department of Chemistry, University of Waterloo, Waterloo, Ontario, Canada
In recent years, nanostructured transition metal-doped semiconductors, known as diluted magnetic semiconductors (DMSs), have been extensively studied as a promising class of multifunctional materials for spintronic devices . For practical applications, DMSs with ferromagnetic phase transition temperatures (Tc) at or above room temperature are required. Transparent conducting oxides (TCOs) have attracted much attention as host lattices for DMSs due to their stability, optical transparency and electrical conductivity . Among TCOs, indium oxide is one of the most widely applied because of its transparency, electrical conductivity, and high charge carrier mobility . In our study, room temperature ferromagnetism was observed in nanocrystalline films fabricated from colloidal chromium and manganese doped indium oxide nanocrystals. Possible explanations for the origin of ferromagnetic ordering in DMSs include charge carrier mediated ordering of dopant centers and the formation of secondary phases involving dopant ions [4,5]. These samples were synthesized and prepared under mild conditions to ensure that the secondary ferromagnetic phases were not present. Furthermore, XRD, TEM, or spectroscopic data indicate no presence of secondary phases. Our results from X-ray absorption spectroscopy measurements have shown substitution of dopant ions for In sites which supports the hypothesis that the origin of ferromagnetic ordering in these fabricated films is related to substitutional dopant ions. The observed ferromagnetism has been associated with the grain-boundary defects, formed at the interfaces of NC building blocks which mediate the dopant magnetic moment ordering, perhaps through formation of charge carriers . These results also suggest that colloidal chromium and manganese doped indium oxide nanocrystals may potentially be used as building blocks for spintronic materials.  Wolf, S. A. et al., Science 294, 1488 (2001). Liu, Y. et al., Chem. Mater. 17, 3997 (2005). Farvid, S. S. et al., Chem. Mater. 22, 9 (2010). Coey, J. M. D. et al., Nat. Mater. 4, 173 (2005). Zhou, S. et al., Vacuum 83, S13 (2009). Farvid, S. S. et al., J. Phys. Chem. C 112, 17755 (2008).
9:00 PM - Q6.12
Electro-forming and Resistance Switching of Vacancy-doped Metal-SrTiO3-metal Structures.
Florian Hanzig 1 , Juliane Seibt 1 , Hartmut Stoecker 1 , Barbara Abendroth 1 , Dirk Meyer 1 Show Abstract
1 Institute of Experimental Physics, TU Bergakademie Freiberg, Freiberg Germany
Resistance switching in metal-insulator-metal (MIM) structures is a promising concept for upcoming non-volatile memories. Transition metal oxides are favourite materials for the insulating layer, because their electronic properties can be tailored in a wide range by doping and external fields.Due to its cubic structure and large band gap, SrTiO3 is a valuable model system to study the relevant electronic parameters. Alternatively to Nb or Fe doping, the conductivity of the SrTiO3 was established by high vacuum annealing introducing charged oxygen vacancies acting as donor centers. To achieve diode characteristics of the MIM stack, a combination of Au and Ti as front and back contacts was evaporated, respectively. Forming in an external electric field is often required to initialize the resistance memory effect in as-prepared structures.Since we investigated single crystals as the insulator, where the annealing procedure leads to strong reduction of the near surface dislocation density, conductive filaments along dislocations play a less important role than in other works reported on this subject. Therefore, we were able to study the contribution of bulk oxygen vacancy migration and localized and delocalized electrons on the electro-forming and field induced resistance change.Switching between two distinct resistance states is demonstrated by applying a typical cycle of write, read and erase voltages. Time dependent experiments show a minimum resistivity after a characteristic forming time depending on crystal thickness and electric field. For continued formation, the resistivity increases up to failure of the system where no current can be measured anymore and switching becomes impossible.For the formation and switching, an electronic band structure model is proposed accounting for trap states near the contact interface and a vacancy concentration gradient, i.e. a p-n junction formation within the SrTiO3 volume.
9:00 PM - Q6.13
Electroforming Process in Metal-oxide-polymer Resistive Switching Memories.
Qian Chen 1 , Henrique Gomes 1 , Dago Leeuw 2 , Stefan Meskers 3 Show Abstract
1 Electronics and Telecommunication, CEOT, University of Algarve, Faro Portugal, 2 Philips Research Labs, High Tech. Campus, Eindhoven Netherlands, 3 Molecular Materials and Nanosystems, Eindhoven University of Technology, Eindhoven Netherlands
Electroforming is a process by which after application of a high bias to a device we can induce permanent and non-volatile memory characteristics. In this contribution, we studied the electroforming process for an Al/Al2O3/polymer/Al resistive switching structure. A series of experiments were designed to understand the trapping mechanisms which will lead to a soft-breakdown of the aluminum oxide layer and ultimately to non-volatile memory characteristics. The electrical properties where studied before the memory is fully formed. It was found that in the early stages of electroforming, there is significant carrier trapping process. The study of the kinetics of the trapping mechanism reveals that is a single activated process with a time constant of 1 hour at room temperature. Thermal detrapping experiments show that the trap density is around 5x10Λ17/cmΛ3 with a trap depth of 0.65 eV.In order to understand the role of the polymer in the soft-breakdown mechanism single oxide layer devices were also studied. For oxide only structures a different and irreversible trapping process occurs.
9:00 PM - Q6.14
Memory Characteristics of ZnO Thin Film Transistor with SiNx Charge Storage for Nonvolatile Memory.
Eunkyeom Kim 1 , Young Ill Kim 2 , Jack You Jung 2 , K. Lee 3 , D. Kim 3 , G. Parsons 3 , Kyoungwan Park 1 2 Show Abstract
1 Nano engineering, Unversity of Seoul, Seoul Korea (the Republic of), 2 Nano Science & Technology, University of Seoul, Seoul Korea (the Republic of), 3 Chemical & Biomolecular Engineering, North Carolina State University, Raleigh NC , North Carolina, United States
Recently, the oxide semiconductors have been investigated for the channel material of the transparent TFT due to their wide bandgap. Zinc oxide (ZnO), which is a typical oxide semiconductor material with a Wurtzite structure (a = 3.25 Å and c = 5.12 Å) and a wide bandgap (3.35 eV), has become attractive in the OLED display backplane technology because of its moderate mobility, low light sensitivity, and low material cost. Also, low temperature fabrication of ZnO channel layer is concerned for the good compatibility with flexible substrates, such as the plastic materials. In developing the future functional transparent electronic devices, the electrical information storage ability of the oxide semiconductor-based TFT as well as the TFT switching characteristics themselves is important. Among several charge trap types in the nonvolatile memories, the defect-rich SiNx charge trap gate stack is expected to be appropriate for the fabrication of transparent nonvolatile memory based on the ZnO thin film transistor. Here we have fabricated a bottom gate SiNx charge trap nonvolatile memory device based on the ZnO TFT. The thin film of ZnO was deposited by using atomic layer deposition process at T = 125 °C. The ZnO films were investigated by X-ray diffraction and X-ray photoemission measurements. The electrical measurements of the nonvolatile TFT memory showed a field-effect mobility of 2.95 cm2/Vs, a threshold voltage of -7.24 V, a subthreshold swing of 1.7 V/dec., and an on/off ratio of 3.4x105. From the C-V measurement, the memory window of 2 V was obtained.
9:00 PM - Q6.15
Nonvolatile and Programmable Nanowire Circuits for Nanoprocessors.
Hwan Sung Choe 1 , Hao Yan 2 , SungWoo Nam 3 , Yongjie Hu 2 , Shamik Das 4 , James Klemic 4 , James Ellenbogen 4 , Charles Lieber 2 3 Show Abstract
1 Physics, Harvard University, Cambridge, Massachusetts, United States, 2 Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States, 3 School of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts, United States, 4 Nanosystems Group, The MITRE Corporation, McLean, Virginia, United States
For the past decade there has been considerable interest in bottom-up assembly and nanoscale materials for the development of memory and logic element for nanoprocessors. Research addressing this goal has, however, fallen short due to challenges in materials, assembly and architecture on the nanoscale. Here we report design and demonstration of nonvolatile, programmable and scalable logic tiles based on charge-trapping nanowire field-effective transistors (FETs) for nanoprocessors. Ge/Si core/shell nanowires coupled with designed dielectric shells yield single-nanowire nonvolatile FETs with programmable threshold voltages, wide hysteresis windows, high on/off ratio, and long retention times. An architecture was developed for integrating the programmable nanowire FETs into two-dimensional arrays, and defined a logic tile consisting of two interconnected arrays. Our logic tile was realized by combination of bottom-up and top-down methods, and was programmed to realize 1-bit full-adder with a maximal gain of 10. Significantly, the same logic tile could be reprogrammed and was used to demonstrate further full-subtractor, multiplexer, demultiplexer, and clocked D-latch functions. In addition, these new nanowire circuits are compared to conventional CMOS in terms of area, power consumption, and speed aspects. These results and larger-than-unity gain and input-output matching in our nanowire logic tiles open up the potential for cascading multiple interconnected tiles as needed to realize fully-integrated nanoprocessors.
9:00 PM - Q6.16
Rigid-flexible Multi-block Polymers Consisting of Alternating Oligoaniline and Alkane Segments and Their Gold Nanocomposites for Organic Memory Devices.
Taek-Gyoung Kim 1 2 , You-Jin Yim 1 2 , Bo-Hee Park 1 2 , Ji-Woong Park 1 2 Show Abstract
1 School of Materials Science and Engineering, Gwangju Institute of Science and Technology (GIST), Gwangju Korea (the Republic of), 2 , Program for Integrated Molecular Systems (PIMS), Gwangju Korea (the Republic of)
Rigid-flexible multi-block polymers consisting of alternating oligoaniline and alkane segments were synthesized. We studied on their chemical and morphological structures in different oxidation states: leucoemeraldine base (LEB), emeraldine base (EB), and emeraldine salt (ES) states, and their processing to produce nanocomposites that are potentially applicable in organic memory devices. Diamine-capped oligoanilines, whose secondary amino groups were protected with the t-BOC group, were synthesized and polymerized with diisocyanatoalkanes to produce a rigid-flexible multi-block polyurea, poly(oligoanilinealkyleneurea)s. Their oxidation states were precisely controlled by various deprotection chemistries using thermal or chemical methods performed in solid or solution states. Different crystalline microstructures were observed for the polymers produced by different deprotection routes. Polymer/gold hybrid nanocomposites were produced via redox reaction between the t-BOC-protected poly(oligoanilinealkyleneurea) and auric chloride in solution followed by film-casting and evaporation. Organic memory devices were fabricated via optimizing the film thickness, and composition of the nanocomposite. (This work was supported by the Program for Integrated Molecular Systems at GIST)
9:00 PM - Q6.17
Write-once-read-many-times Memory Fabricated with ZnO/MgO/Si Heterojunction for Long-time Archival Storage.
Jing Qi 1 , Jian Huang 1 , Qing Zhang 1 , Jingjian Ren 1 , Jianze Zhao 1 , Jianlin Liu 1 Show Abstract
1 Department of Electrical Engineering, Quantum Structures Laboratory, University of California, Riverside, Riverside, California, United States
Write-once-read-many-times (WORM) memories have extensive applications in archival storage and non-editable database equipments because of their permanent data-storage ability.  Nonvolatile WORM capacitor memory elements were fabricated using an epitaxial ZnO/MgO layer on clean n+-Si (111) substrate, which was grown in a radio frequency plasma-assisted molecular beam epitaxy system.  Thin continuous ZnO layer (60nm) was grown on the Si substrate at 400 oC using a few atomic layers of MgO as a buffer layer. Scanning electron microscope (SEM) results show that ZnO thin film appears to be column structure because of large lattice mismatches among ZnO, MgO, and Si (111) substrate. Ti(10nm)/Au(90nm) square-shaped metal patterns, which act as top contact on ZnO, were grown by an electron beam evaporator, followed by standard lift-off process.Current-voltage (I-V) characteristics show that ON and OFF state current ratio are larger than 104 for over 80% of hundreds of measured devices at a reading voltage of 1V. The large memory window can be perfectly sustained for 105s. As the data trends are extrapolated to 10 8s, two states can still be clearly distinguished without observable decrease of ON/OFF ratio. At the same time, no resistance degradation is observed for the ON and OFF-state after more than 108 read cycles, indicating that both states are insensitive to read cycles. The study also shows that the writing voltage is in a reasonable range of lower than 20V for all devices with area of 600×600, 400×400, 200×200, 100×100, 50×50, and 30×30μm2. The dependence of ON/OFF ratio on device area shows that better memory characteristics can be achieved when the device is scaled down further. SEM and optical microscopy results for ON state devices show that oxygen vacancy filament formation in ZnO during writing process, which is a type of soft breakdown , is responsible for the memory switching mechanism. This mechanism was also further proved by the small bi-stable resistive random access memory (RRAM) effect, which was demonstrated during continuous voltage sweeping measurements with a much larger range on the same device, for example, +10V~-10V~+10V.  S. Moller, C. Perlov, W. Jackson, C. Taussig, and S. R. Forrest, Nature, 426, 166 (2003). Z. Yang, L. Li, Z. Zuo, J.L. Liu, J. Cryst. Growth, 312, 68 (2009). A. Sawa, Material Ttoday, 11, 28 (2008).
9:00 PM - Q6.18
Highly Manufactuable Device Isolation Technology using LEG (Laser-induced Epitaxial Growth) Process for Monolithic Stack Devices.
Yong-Hoon Son 1 2 , Euijoon Yoon 2 Show Abstract
1 Process Development, Samsung electronics, Hwasung-si Korea (the Republic of), 2 Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
Novel isolation technology by using LEG (Laser-induced Epitaxial Growth) process has been introduced to obtain monolithically stacked active silicon without any thermal budget of underlying devices. With the LEG process, the epitaxial behavior is completely understood by solidification modeling. Once the polysilicon in the active layer is selectively melted by incident laser beams, heat in the melt may be preferentially dissipated out through silicon substrate because the thermal conductivity and heat capacitance of silicon substrate are higher than that of both sidewall oxide and air. The molten silicon is rapidly solidified from the interface with the silicon substrate, which acts as a seed for vertical epitaxial solidification with facet plane, leading to a perfect single crystalline LEG-silicon in active layer. It is shown that the characteristics of cell transistors with LEG-active silicon are the same as those with bulk-active silicon, in terms of both performance and distribution using high density 512Mb DRAM devices. For comparison, when a cell transistor on SEG-silicon was fabricated, it was observed that off-leakage was higher than LEG-silicon, which corresponds to the distribution of junction leakage of 176k array cell transistors. Thus LEG process is believed to be a promising device isolation technology for monolithic multi-stack devices.
9:00 PM - Q6.2
Study of Oxide Substrate Surface Morphology Effect on Silicon Quantum Dot Growth.
Jingjian Ren 1 , Jianlin Liu 1 Show Abstract
1 EE, UC,Riverside, Riverside, California, United States
Nanocrystal memory has been nominated as an alternate to extend flash memory since it was first introduced by Tiwari in 1995. Tremendous efforts have been spent on the investigation of nanocrystal growth through various techniques, such as low pressure chemical vapor deposition (LPCVD) , molecular beam epitaxy , ion implantation and subsequent high-temperature annealing ; etc. Memory devices with high nanocrystal density and good performance have been demonstrated based on these techniques . Nevertheless, some problems arise along with the requirement of the large scale industrial production and the scaling of the technology node down to beyond 32nm, including the erasing/writing performance non-uniformity and variable memory windows of the devices on the same chip, which result from the floating dot density variation. Nanocrystal growth on oxide substrate needs to be fully investigated and new nanostructures need to be developed in order to solve the problems and to further enable the scalability. Here we report our effort on studying Si quantum dots (QD) growth on oxide-coated Si substrate with different surface morphology. The original motivation was to explore possible preferential growth to achieve QD self-alignment on oxide-coated Si nanowires for nonvolatile memory applications. Triangular shaped Si wire arrays and pits with smooth surface were fabricated by anisotropic wet chemical etching to form two different types of surface morphologies, namely, convex and concave. Thermal oxidation was used to form a thin layer of SiO2, followed by Si QD growth by LPCVD. Samples grown with different conditions (temperature, growth time, etc.) were characterized by scanning electron microscopy. Likely preferential growth of QD at concave parts of oxide surface was found and growth condition window was defined. The effect of substrate surface morphology on the nucleation and growth of QD was tentatively explained.References1.S.Tiwari, F.Rana, K.Chan, and O.Buchanan, “Volatile and nonvolatile memories in silicon with nano-crystal storage,” in IEDM Tech. Dig., 1995, pp. 521-524.2.Yan Zhu, Bei Li, and Jianlin Liu, “Self-aligned TiSi2/Si Hetero-nanocrystal Nonvolatile Memory”, Mater. Res. Soc. Symp. Proc. Vol. 997.3.A. Nylandsted Larsen, A. Kanjilal, J. Lundsgaard-Hansen, P. Gaiduk, P. Normand, P. Dimitrakis, D. Tsoukalas, N. Cherkashin, A. Claverie, “Ge Nanocrystals in MOS-Memory Structures Produced by Molecular-Beam Epitaxy and Rapid-Thermal Processing”, Mater. Res. Soc. Symp. Proc. Vol. 830.4.Kaori Masuda, Masahiro Yamamoto, Masatoshi Kanaya and Yoshihiko Kanemitsu, “Fabrication of Ge nanocrystals in SiO2 films by ion implantation: control of size and position”, Journal of Non-Crystalline Solids, Volumes 299-302, Part 2, April 2002, Pages 1079-1083. 5.Bei Li, Jingjian Ren and Jianlin Liu, “Synthesis of high-density PtSi nanocrystals for memory application”, Applied Physics Letters 96, 172104(2010).
9:00 PM - Q6.3
Enhancement of Nonvolatile Floating Gate Memory Devices Containing AgInSbTe-SiO2 Nanocomposite by Inserting HfO2/SiO2 Blocking Oxide Layer.
Kuo-Chang Chiang 1 , Tsung-Eong Hsieh 1 Show Abstract
1 Materials Science and Engineering, National Chiao Tung University, Hsinchu Taiwan
Nonvolatile floating gate memory (NFGM) device containing AgInSbTe (AIST)-SiO2 nanocomposite as the charge trapping layer possesses the advantages such as simplified device structure and fabrication process. In this work, performance enhancement of such a NFGM device by inserting an HfO2 or HfO2/SiO2 blocking oxide layer in between the charge trapping layer and Al electrode was presented. For HfO2/AIST-SiO2 NFGM sample, capacitance-voltage (C-V) measurement observed a hysteresis memory window (ΔVFB) shift = 11.6V and charge density = 1.0×1013 cm-2 at ±15V gate voltage sweep. As to the HfO2/SiO2/AIST-SiO2 NFGM sample, extremely large ΔVFB shift = 30.7V and charge density = 2.3×1013 cm-2 at ±23V gate voltage sweeping were achieved. Retention time analysis observed a ΔVFB shift = 19.3V and the charge loss about 13.4% in such a sample after 104 sec retention time. The dramatic improvement of nonvolatile memory characteristics was ascribed to the formation of AIST nanocrystals (NCs) and the presence of (Hf,Si)O2 oxide layer in the samples. Microstructure and composition analyses identified the metallic Sb2Te NC phases about 5 nm in diameter finely dispersed in SiO2 matrix may serve as the charge-storage traps for memory characteristics. Current-voltage (I-V) measurement observed a leakage current density as low as 1.5×10-7A/cm2 at ±3.3 MV/cm bias field, indicating the (Hf,Si)O2 oxide layer may effectively block the electron injection from gate to Sb2Te NCs. I-V measurement also revealed the conduction mechanisms are the Schottky emission at low bias field and the space-charge-limited conduction (SCLC) at high bias filed for both gate injection and substrate injection cases. Addition of HfO2 is able to improve the NFGN device performance owing to its high dielectric constant and large band gap properties; nevertheless, it was found that Hf diffuses into AIST-SiO2 nanocomposite. This results in HfOx and, consequently, its nonstoichiometry generates oxygen vacancies and degrades the device performance. Insertion of SiO2 layer is hence crucial to the dramatic enhancement of nonvolatile memory characteristics since it not only impedes the Hf diffusion but also suppresses the formation of detrimental TeO2 phase in NFGM sample as observed in previous study.
9:00 PM - Q6.4
Fabricating ZnO Thin Film Transistor-memory with Au Nanocrystals Embedded in High-k MgO Dielectric.
Wei-Yu Chen 1 , Jen-Sue Chen 1 Show Abstract
1 Department of Materials Science and Engineering, National Cheng Kung University, Tainan City Taiwan
In this study, ZnO thin film transistor (TFT)-memories with a MgO/Au/MgO gate dielectric layer is fabricated. A thin Au layer (1~3 nm) is inserted into the electron-beam evaporated high-k MgO dielectric layer and transforms into Au nanocrystals after annealing. For charge trapping characteristics, MgO/Au/MgO multilayers with various sizes and distributions of Au nanocrystals are deposited on p-type Si substrates. C-V hysteresis curves of various offset windows are observed, indicating successful modulation of different degrees of charge trapping in Au nanocrystals. The endurance characteristics and retention properties are also investigated. When these Au nanocrystals embedded high-k MgO dielectric layers are incorporated into ZnO TFT-memory devices, a clear clockwise hysteresis characteristic of reciprocated Id-Vg scanning is found. The results suggest that electron trapping in the Au nanocrystals during the voltage sweep and the degree of threshold voltage shift can be controlled. With the used of high-k MgO dielectric layers, the devices can be operated under 1 V.
9:00 PM - Q6.7
Doping GaN Nanowires with Mn for Magnetic Applications.
Gary Harris 1 Show Abstract
1 HNF, Howard University, Washington, District of Columbia, United States
Using Mn metal power as a Mn source, NH3, as a reactive gas and N2 as a carrier gas we have been able to grow and dope nanowires of GaN. The purpose of doping the GaN nanowires with Mn is to produce nanowires that are magnetic and can be used in spintronics. GaN and Mn powder are heated for two hours at 850°C. The length of the wires was measured with typical values between 20 to 200µm. the diameter of the wires range from 20 to 200nm. The flow rates of the gases, growth temperature and distance from the source will be presented in detail. EDS and local photoluminescence have been performed of the as grown samples. Over 5% on Mn was found in the GaN wires. The PL spetrum indicates the presents of both GaN and a impurity level associated with Mn in GaN. We will also report on the structural, magnetic and electrical properties of these nanowires. This work is being supported by NSF under the Partnership for Research and Education in Materials Program.
9:00 PM - Q6.8
Magnetic Properties of Chromium and Cobalt Doped Indium Oxide Dilute Magnetic Ssemiconductors.
K. Ghosh 1 , M. Langhoff 1 , E. Nahlik 1 , A. Ghosh 1 , N. Ukah 1 , Ram Gupta 1 , Y. Kolekar 1 2 , P. Kahol 1 Show Abstract
1 Physics, Astronomy and Materials Science, Missouri State University, Springfield, Missouri, United States, 2 Physics, Pune University, Pune India
Oxide based dilute magnetic semiconductors are key materials for development of next generation multifunctional spintronics devices such as spin transistors and magnetic random access memories (MRAM). However, the success of these devices critically depends on electrical and magneto-transport properties of dilute magnetic semiconductors. Here, we investigate the magnetic properties of Cr and Co doped indium oxides in bulk as well as in thin films. The films were grown using pulsed laser deposition techniques. Structural, electrical, optical, and magnetic properties have been measured using standard techniques. Magnetization versus applied magnetic field and temperature data were collected on all the samples using a superconducting quantum interference device (SQUID) magnetometer at various fields and temperatures respectively. Temperature dependence magnetization measurements for the Co doped indium oxide bulk sample show the presence of a hump around 50 K which could be due to paramagnetic to ferromagnetic transition and the magnetizations versus field study show the hysteresis behavior which confirms the ferromagnetism. The effect of growth parameters on magnetic properties of Co and Cr doped indium oxide thin films were also studied. Preliminary magnetization versus field data for thin films show linear behavior at all temperature down to 5 K. The linear behavior of magnetization with applied magnetic field indicates the presence of paramagnetic or antiferromagnetic phase in the films. Detailed field and temperature dependent magnetization data will be presented. This work is supported by National Science Foundation (Award Number DMR-0907037)
9:00 PM - Q6.9
Manipulation and Study of Mass Selected Magnetic Nanoparticles from a Magnetron Sputter Gas Aggregation Source.
Mukhles Sowwan 1 2 , Jean Bobo 1 3 , Chia Chung 1 , James Groves 1 , Bruce Clemens 1 Show Abstract
1 Materials Science and Engineering, Stanford, Stanford, California, United States, 2 Materials Engineering, Al-QudsUniversity, Jerusalem Palestine, State of, 3 CEMES-CNRS, CNRS, Toulouse France
New techniques able to provide as-deposited dense films of controlled size nanoparticles are being actively developed for many industrial domains. Nanoparticles are expected to be a convenient way for charge and/or magnetic non volatile storage, but the nanoparticles size needs to be accurately controlled for reliable data writing process, as well as for thermal stability issues related to the superparamagnetic limit. We have investigated the morphology and electrical properties of mass selected cobalt nanoparticles produced with a magnetron-sputter gas-aggregation source- on silicon substrate using AFM and SEM . The base pressure in the sputtering system was ~10-8 Torr and the deposition rate was monitored using a quartz crystal microbalance. Cobalt was direct current (dc) sputtered on silicon. Deposition was performed at room temperature with ~0.7 mTorr Ar pressure in the main chamber while the sputter source was maintained in a 300 to 500 mTorr range in order to ensure a good thermalization of the cobalt nanoparticles beam. Our optimized deposition conditions lead to a uniform, spherical and narrow size distribution nanoparticles in the range of 10 to 20 nm. Electrostatic force microscopy was used to study the interaction of nanoparticles with an external electric field; we found that the cobalt nanoparticles are positively charged. Contact mode atomic force microscopy was used to manipulate and study the physical interaction between the deposited nanoparticles and the substrate. We will discuss in detail the influence of various synthesis parameters (particle size, particle density, nature of the substrate…) on the magnetic properties of these samples.
Orlando Auciello Argonne National Laboratory
Panagiotis Dimitrakis Institute of Microelectronics
Yoshihisa Fujisaki Hitachi Ltd.
Eisuke Tokumitsu Tokyo Institute of Technology
Dirk Wouters IMEC
Applied Materials Inc
M. Watanabe &
Park Systems Corporation
Universal Systems Co., Ltd
Q9: Poster Session: Resistive Switch Memories III
Thursday PM, April 28, 2011
Salons 7-9 (Marriott)
1:00 AM -
Q9.9 Transferred to Q10.9
Q7: Resistive Switch Memories I
Thursday AM, April 28, 2011
Room 3002 (Moscone West)
9:30 AM - Q7.1
Ab Initio Study of Copper in Silicon Dioxide.
Martin Zeleny 1 , Jozsef Hegedus 1 , Adam Foster 2 , David Drabold 3 , Stephen Elliott 4 , Risto Nieminen 1 Show Abstract
1 Department of Applied Physics, Aalto University, Espoo Finland, 2 Department of Physics, Tampere University of Technology (TUT), Tampere Finland, 3 Department of Physics and Astronomy, Ohio University, Athens, Ohio, United States, 4 Department of Chemistry, University of Cambridge, Cambridge United Kingdom
Non-volatile memory chips based on resistive switching have attracted much interest due to their high performance, low power consumption and high storage capacity. Their switching mechanism is based on electrochemical metallization occurring due to migration of Ag or Cu ions in oxide glasses as for example silicon dioxide. This process consists of two steps: 1) electro-chemical formation of a metallic filament (“SET” step) and 2) its electro-chemical dissolution (“RESET” step). One of the main problems in developing new non-volatile memory materials is the lack of microscopic understanding of these processes.
In order to clarify the mechanism underlying these processes, we have performed theoretical calculations of copper diffusion in SiO2 driven by external electric field. All calculations in our study are carried out based on first-principles density-functional theory (DFT) using planewave basis sets and the projector augmented-wave method as it is implemented in the Vienna Ab initio Simulation Package (VASP).
We present a total-energy calculation of the barrier along a diffusion path of copper between two equivalent interstitial positions in α-cristobalite. The shape of the path strongly depends on charge of the system, but the height of the migration barrier stays between 0.15-0.2 eV. We also present results of molecular dynamics simulation of drift a copper atom driven by external electric field.
Resistive switching devices are based on amorphous SiO2 but density of α-cristobalite is very close to density of amorphous phase. However our presented results should by used only as a reference point for future calculations in amorphous phase.
9:45 AM - Q7.2
Complementary Resistive Switches (CRS): High Speed Performance for Passive Nanocrossbar Arrays.
Roland Rosezin 1 , Eike Linn 2 , Lutz Nielen 2 , Carsten Kuegeler 1 , Rainer Bruchhaus 1 , Rainer Waser 1 2 Show Abstract
1 Institut fuer Festkoerperforschung, Forschungszentrum Juelich GmbH, Juelich Germany, 2 Institut fuer Werkstoffe der Elektrotechnik 2, RWTH Aachen University, Aachen Germany
Passive nanocrossbar arrays comprising metal-insulator-metal structures with resistive switching materials are envisioned to be the main building block of future non-volatile high density memory and logic devices. However, the passive crossbar array architecture suffers from current sneak paths which can significantly limit array size. Recently, we presented the CRS , which is an anti-serial connection of two bipolar resistive switches. Using CRS cells in crossbar arrays, sneak paths are successfully suppressed.In this report, we show high speed measurements of fully vertically integrated CRS cells with diameters down to 100 nm for the first time. The CRS cells consist of two stacked Cu/SiO2/Pt memristive elements with common Cu electrode, which are known to exhibit excellent switching performance as well as immense scaling potential. Electron beam structuring techniques combined with sputter deposition methods are used to fabricate the stacked device structure. We present measurements of the resulting CRS cells revealing excellent quasi-static I-V-characteristics  as well as fast switching in the 200 ns regime. Due to an intentionally designed probe electrode, we are able to prove proper bipolar switching behaviour of each constituting element, thus confirming the assumptions of our initial report . Based on the resistance ratios of the measured CRS cells, our simulations propose array block sizes of more than 10 million cells. Furthermore, we address the incorporation of CRS cells into crossbar arrays by understanding CRS cells as a single memristive system and evaluating write/read schemes (e.g. V/3) with regard to data stability.
 E. Linn, R. Rosezin, C. Kuegeler, and R. Waser, Nat. Mater., 9, 403-406, 2010.
 R. Rosezin, E. Linn, L. Nielen, C. Kuegeler, R. Bruchhaus, and R. Waser, IEEE Electron Device Letters, accepted.
10:00 AM - Q7.3
Influence of Copper on the Switching Properties of Hafnium Oxide-based Resistive Memory.
Benjamin Briggs 1 , Seann Bishop 1 , Kevin Leedy 2 , Richard Moore 1 , Steven Novak 1 , Nathaniel Cady 1 Show Abstract
1 College of Nanoscale Science and Engineering, SUNY Albany, Albany, New York, United States, 2 AFRL/RYDD, Air Force Research Laboratory, Wright patterson AFB, Ohio, United States
Transition metal oxide resistive memory devices are a leading candidate for next generation non-volatile storage. When compared to current CMOS NAND flash, resistive memory offers lower power operation, increased density through a simpler fabrication process and ultimately, faster operation. Hafnium oxide has been selected as the transition metal oxide for this work due to its large band gap (5.8 eV), the resulting low off-state leakage current, and its wide spread use in CMOS manufacturing as a high-k gate dielectric. Hafnium oxide has been previously studied as the active layer in resistive memory devices by multiple groups. These investigations have demonstrated devices with stable, long-term read/write endurance, low switching energy, and high on/off ratios. Of particular interest to our work is the role of copper doping in HfO2 films. Prior work has shown that resistive memory devices containing copper-doped HfO2 exhibit lower electroforming voltages. Our HfO2 devices have been fabricated as standard metal-insulator-metal (MIM) two-terminal devices. Hafnium oxide with a thickness of 50 nm was deposited at 250 °C using atomic layer deposition (ALD) with tetrakis(dimethylamido)hafnium as the metal precursor and an O2 plasma as the reactant. The substrate was composed of 1 um copper, electroplated on SiO2/SiN/Si. Top metal electrodes (Ni, Pt, Al, Au) were then fabricated by standard optical lithography and metal lift-off techniques. Chemical analyses of our HfO2 films by x-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS) depth profiling have revealed an unintentional copper doping concentration on the order of five atomic percent throughout the HfO2 film. At the HfO2 surface, the copper concentration increases dramatically, resulting in the formation of a conducting surface copper oxide layer ~5 nm thick. This phenomenon has not been previously reported in resistive switching literature and therefore has likely gone unnoticed by other investigators. For this presentation, the influence of the copper dopants/surface layer on the resistive switching properties will be discussed. Electrical testing was performed with both sweep and pulse-mode current-voltage measurements. In both cases non-polar resistive switching behavior was observed, independent of the top metal electrode, without the need for prior forming voltage steps. In addition, set voltages less than +/-2 V and reset voltages on the order of +/-500 mV were observed with Ion/Ioff ratios of 109. The results were concurrent with the state-of-the-art devices that have been reported in the literature. Lastly, since device feature size scaling is important for commercial applications, preliminary fabrication and electrical results of sub-100 nm via-based devices with a similar process flow will be presented.
10:15 AM - Q7.4
Fabrication and Characterization of Copper Oxide Resistive Memory Devices.
Seann Bishop 1 , Benjamin Briggs 1 , Sree Addepalli 1 , Nathaniel Cady 1 Show Abstract
1 College of Nanoscale Science and Engineering, University at Albany, Albany, New York, United States
Resistive memory devices (RMDs) have the potential to revolutionize computing beyond today’s transistor-based systems. Copper oxide is one of the transition metal oxides that exhibits resistance-based memory. Copper oxide RMDs have been produced with ROFF/RON ratios up to 10^5 and endurance values of >10^4 write/erase cycles. Data retention times of >10 years have also been achieved. Despite this progress, there is a significant lack of information available in the open literature on the fabrication of these devices. In this work, a systematic investigation has been performed to determine how the oxide synthesis technique, film properties, and the device fabrication process impact the switching behavior of RMDs. To achieve these goals, copper oxide films to 1 micron in thickness were synthesized by copper oxidation and reactive sputtering on copper bottom electrodes. Platinum, aluminum, and nickel top electrodes were fabricated on these oxides using conventional patterning techniques. For this presentation, the technical challenges encountered with each synthesis technique will be discussed, and the process conditions employed to produce switchable oxide thin films will be introduced. The results from scanning electron microscopy (SEM) and transmission electron microscopy (TEM) show the surface of the copper oxide produced by thermal and plasma oxidation is rough. The surface produced by thermal oxidation was further characterized by atomic force microscopy (AFM); the RMS (root mean square) roughness was 32 nm. Copper oxide thin films deposited by reactive sputtering had a polycrystalline microstructure, with large void areas between grains. In some cases the void area was sufficiently large to permit electrical contact between the top and bottom electrodes, short circuiting these devices. X-ray diffraction (XRD) showed that Cu2O is the dominant phase present in films produced by thermal oxidation and reactive sputtering. The current-voltage (I-V) characteristics of large area devices, consisting of a continuous copper oxide layer, were compared with individually defined “mesa” devices. A mesa etch process was developed to remove the copper oxide layer between top electrodes and prevent parasitic effects between individual devices. Because of the novelty, a brief description of the etch process will be given. Both device schemes exhibit multiple resistance states; however, preliminary results suggest that individually-defined mesa devices exhibit more reliable resistive switching characteristics. Specifically, the latter (with Al top contacts) switched with set voltages ~2 V and reset voltages of less than -1V. The ROFF/RON ratio ranged from 10^3-10^4. The ultimate goal of this work is to characterize micron-scale devices and use these data as a platform to engineer nanometer-scale devices. Our recent results for fabricating copper oxide-based RMDs into ≤100 nm features will also be presented.
10:30 AM - Q7.5
Comparative Study of Doping Effect on Reverse-bias-modulated Bipolar Resistance Switching in Transition-metal Doped ZnO.
Tom Wu 1 Show Abstract
1 , Nanyang Technological University, Singapore Singapore
Resistance random access memory (ReRAM) based on electric field induced resistance switching is known as one of the most promising candidate for next generation non-volatile memory device. The high density memory cells are usually projected in the form of metal-insulator-metal nanostructure. Various materials seem to be available, such as binary transition oxide TiO2, NiO, ZrO2, ZnO, perovskite oxide P1-xCaxMnO3, SrTiO3, SrZrO3, and Ag doped or Cu-doped chalcogenide. Among these material systems, binary oxide has projecting advantages of simple structure and good compatibility with conventional CMOS processing. Although many efforts have been made on the investigation of the ReRAM, the underlying mechanism of this resistance switching phenomena is still controversial, which limits the improvement on operation speed, power consumption and device retention and endurance. To clarify the dominating mechanism, our group currently focus on the metal doping effect on resistance switching of the ZnO thin films. In this work, we conducted a comparative study of doping effect for bipolar resistance switching on R-doped(R=Mn, Cu, Co) ZnO thin films. For Pt/Mn doped ZnO/Si device, we also reported the resistance evolution, reverse bias modulation and our analysis of its conduction mechanism. The conclusion will assist a further improvement on the performance of novel ReRAM.
10:45 AM - Q7.6
In-situ TEM Analysis of Conductive Filament in a Solid Electrolyte Resistance RAM.
Takashi Fujii 1 , Masashi Arita 1 , Yasuo Takahashi 1 , Ichiro Fujiwara 2 Show Abstract
1 Graduate School of Information science and Technology, Hokkaido University, Sapporo, Hokkaido, Japan, 2 , Semiconductor Technology Academic Research Center, Yokohama Japan
A solid electrolyte ReRAM has great potential as a nonvolatile memory. The mechanism of resistance switching is attributed to formation and disappearance of the conductive filament in the solid electrolyte. Therefore, the analysis of the conductive filament must give important information to understand this switching mechanism. However, no detail experimental results to confirm the filament during the switching process have been reported. An in-situ transmission electron microscopy (TEM) with simultaneous electrical measurements has attracted a great deal of attention to satisfy this demand. In this work, we used this in-situ TEM method to understand the switching mechanism of a solid electrolyte. Real-time observations of the filament formation and disappearance process were successfully performed.For in-situ TEM experiments, commercially available Pt-Ir tips for scanning tunneling microscopy were further sharpened by ion milling and were used as substrates as well as the counter electrodes. The Cu-GeS thin film was prepared at room temperature by RF sputtering on this metal substrate. The Cu composition was about 40 at. %. The film thickness was between 8 and 60 nm, and no remarkable difference depending on thickness was recognized. The system is composed of a custom-made TEM holder with a PC-controlled operating system. The conduction properties were measured between the Pt-Ir counter electrode and Cu-GeS/Pt-Ir. The area of the fixed Cu-GeS/Pt-Ir sample was selected by moving the Pt-Ir counter electrode.From TEM images, Cu-GeS was an amorphous phase including nanocrystals. We measured a current-to-voltage (I-V) curve during TEM observation. When the voltage applied to the sample was swept from 0 V to 7 V, from 7 V to -2 V and back to 0 V. A typical resistance switching phenomenon (hysteresis I-V curve) was detected. In corresponding TEM images during this measurement, some deposits appeared at the layer when we applied a positive voltage. The deposit grew by continuously applying the positive bias voltage. Afterward, the deposit was suddenly disappeared with negative voltage. The size of deposit and the current value correspond well to each other. From these results, it is clearly concluded that the deposit observed constitutes the conducting path.We also confirmed the crystal structure of the deposit by observing real-time selected area diffraction (SAD) and the composition of the area where the deposit appeared by means of energy dispersive X-ray spectroscopy (EDX). From SAD and EDX results, the conductive filament was consisted of nanocrystals of Cu or copper compounds. This work successfully performed in revealing the relation between the real-time structure change inside solid electrolytes and the resistance switching operation.
11:30 AM - Q7.7
Understanding of Resistive Switching of Unipolar NiO-based RRAM.
Hyung Dong Lee 1 , Blanka Magyari-Koepe 1 , Kwanghee Cho 1 2 , Yoshio Nishi 1 Show Abstract
1 Electrical Engineering, Stanford University, Stanford, California, United States, 2 NtI, hynix, Icheon, Kyunggi, Korea (the Republic of)
Resistance change random access memory (RRAM) based on transition metal oxides such as NiO, TiO2 had been extensively investigated candidates for the next generation of memory devices, due to their simplicity in composition and scaling capability. Even though the switching phenomena had been observed in various materials, the fundamental understanding of the switching mechanism and its physical origin is still under debate. It had been suggested based on experimental observations, that the so called “filament model” gives a qualitative explanation for the unipolar switching in NiO RRAM. Several theoretical models had been proposed then to explain the formation of the filament,. The model based on the finding that the abundance of metallic type Ni atoms in the NiO films might be responsible for the filament formation has received considerable attention in the past year. In terms of the switching, additional experimental facts associated with the switching mechanism, like oxygen migration and thermal effects, crystal disorder and interfaces with electrode, etc., were found to be important, and new models incorporating these effects are currently being elucidated.In this report, the electronic band structure of ordered anion vacancy clusters along a filamentary structure in NiO is evaluated using density functional theory and the local density approximation with on-site Coulomb corrections, (LDA+U). We propose a microscopic model for the formation and rupture of an electrically active filament in NiO to explain the unipolar resistive switching observed in resistive change memory devices. We show that the formation and rupture process of the filament are associated with the migration of oxygen in the oxide and is coupled with the oxidation and reduction of nickel atoms. The calculated migration barrier is consistent with the observed experimental activation barrier for retention. Based on the obtained migration barrier values the retention time can be evaluated and the retention process is linked to the directional migration of oxygen atoms.
11:45 AM - Q7.8
Reduction in Reset Current of Unipolar NiO-based Resistive Switching through Nickel Interfacial Layer.
Hyung Dong Lee 1 , Seung Wook Ryu 1 , Blanka Magyari-Koepe 1 , Kwanghee Cho 1 2 , Yoshio Nishi 1 Show Abstract
1 Electrical Engineering, Stanford University, Stanford, California, United States, 2 Nt&I, hynix, Icheon Korea (the Republic of)
The role of interface between electrode and NiO on switching characteristics has been investigated for unipolar NiO-based resistive switching. The 10 times reduction of reset current could be achieved relative to a few mA in many literatures by inserting a thin nickel interfacial layer between cathodic electrode and NiO. A model describing the reduction of reset current mechanism was derived from the combination effect of oxygen vacancy formation/migration and the interfacial oxide layer at cathodic electrode. It is critical to optimize the interfacial layer at the cathodic electrode to reduce the reset current and keep the “on” resistance within a reasonable range.
12:00 PM - Q7.9
Influence of Process Parameters on Low-current Resistive Switching in MOCVD and ALD NiO Films.
Xin Peng Wang 1 , Dirk Wouters 1 3 , Michael Toeller 2 , Johan Meersschaut 1 , Ludovic Goux 1 , YangYin Chen 3 , Bogdan Govoreanu 1 , Luigi Pantisano 1 , Robin Degraeve 1 , Malgorzata Jurczak 1 , Laith Altimime 1 , Jorge Kittl 1 Show Abstract
1 , imec, Leuven Belgium, 3 Electrical Engineering, Katholieke Universiteit Leuven, Leuven Belgium, 2 , Tokyo Electron Limited, Tokyo Japan
NiO has become one of the prototype metal-oxide resistive switching materials since the publication of Baek et al. at IEDM 2004. While the most widely used fabrication technique for formation of NiO has been reactive physical vapor deposition, we report on the switching properties of NiO synthesized by chemical vapor deposition techniques MOCVD and ALD, and furthermore on the effects of NiO thickness, of Ti-doping, of post-depostion anneal treatments, and of electrode process and thickness.The NiO films in this study show abrupt unipolar switching when using asymmetric Ni and TiN electrodes. A forming step is required at a forming field of ~2MV/cm. While either TiN or Ni can be top or bottom electrode, the switching polarity for Set as well as Reset is always positive to the Ni electrode. The switching quality was assessed as a function of Ireset (should be minimal) and Roff/Ron ratio (should be maximal). We found that both these parameters are strongly related to the initial filament formation, and we could relate the abovementioned effects of film thickness, process, etc. on how these affect the forming process. Effects on dielectric quality (leakage current and breakdown voltage) can be related to switchability, indicating the role of active defects in the switching process.For best switching films, after initial forming and reset, program current could be further scaled down to the 10 uA range even for the larger area capacitors. These results make these CVD NiO film interesting candidates for scaled RRAM fabrication.
12:15 PM - Q7.10
Bipolar Resistive Switching Characteristics of NiO Thin Film Grown on TiN Substrate Using Radio Frequency Magnetron Sputtering.
Tae Geun Seong 1 , Mi-Ri Joung 2 , Jong-Woo Sun 2 , Ji-Won Moon 3 , Jae-Sung Roh 3 , Sahn Nahm 1 2 Show Abstract
1 Department of Nano-semiconductor, Korea university, Seoul Korea (the Republic of), 2 Department of Materials Science and Engineering, Korea University, Seoul Korea (the Republic of), 3 R&D Div. New memory process part, Hynix Semiconductor Inc., Icheon-si, Kyoungki-do, Korea (the Republic of)
NiO films were grown on a TiN substrate by RF magnetron sputtering using a NiO ceramic target. A polycrystalline NiO phase was well formed for the films grown above 80°C under the 8.0 mTorr oxygen partial pressure. Resistive switching behavior was not found in the NiO films annealed in the air or in ambient O2 after film deposition. However, NiO films annealed in ambient N2 exhibited the bipolar resistive switching properties. The Ni filament was considered to be formed during the set process and the rupture of Ni filament occurred during the reset process by redox reaction. Moreover, Ohmic conduction behavior and Poole-Frenkel emission were observed in the low resistance state (LRS) and high resistance state (HRS), respectively. The resistances of LRS and HRS measured at 0.2 V were 5.5 x 10 and 5.0 x 103 ohms, respectively, within 200 cycles under ± 1.0 V. These resistance values were maintained for 104 seconds at room temperature and 85°C, indicating that the NiO films grown on TiN substrate could be stable for more than 10 years. This NiO film also exhibited the reliable switching voltages (Vset ~ 0.60~0.75 V and Vreset ~ -1.1 V).
12:30 PM - Q7.11
Resistive Switching in Core-shell Ni-NiO Nanowires for Crossbar Memory Arrays.
Carlo Cagli 1 , Bruce Harteneck 2 , Federico Nardi 1 , Zhongkui Tan 2 , Yuegang Zhang 2 , Daniele Ielmini 1 Show Abstract
1 , Politecnico di Milano, Milano Italy, 2 , Lawrence Berkeley National Lab, Berkeley, California, United States
Resistive switching in metal oxides, such as NiO, is attracting a broad interest as a memory concept for possible future high density devices.The reversible resistance change in NiO is based on the formation and rapture of a nanoscale conductive filament shunting the insulating layer.Resistive switching memory (RRAM) usually employs planar metal-insulator-metal structure which are compatible with conventional top-down CMOS technology platforms. However, demonstrating bottom-up RRAM technologies based on self-assembled nanoparticles would strongly improve the actual scaling perspectives in terms of memory cost/size[3,4].Recently, nanofabrication has achieved huge improvements in the synthesis and assembly of nanowire (NWs), exploiting template-based growth methods and self-assembling techniques.Core-shell NWs is one of the most attractive nano-building blocks for self-assembled structures.The possibility to self-assemble NWs cross structures arrays featuring resistive switching at each NW cross-point may lead to an ultimate cell scaling of below 10 nm, corresponding to a memory density higher than 0.25 Tb/cm2.This work reports the synthesis and assembly of Ni/NiO core/shell NW crossbar structures, demonstrating for the first time the resistive switching through the NiO shell layer at the contact point between two NWs, providing electrical characterization of set and reset transitions and cycling endurance. This is the first demonstration of a crossbar RRAM based on metal oxide core-shell nanowires.Ni NW were grown by electroplating and assembled on SiO2 substrate. Pads for electrical measurements were deposited by e-beam litho with standard lift-off. NWs were characterized by SEM,HRTEM,EELS and electron diffraction, showing a thin NiO shell of about 15nm. The crossbar structures were electrically characterized by standard electric probes.The NW-based RRAM display set/reset characteristics with a typical reset current of 0.5-5mA and set voltage around 1-3V, in agreement with previous data for planar NiO RRAMs.We conclusively demonstrates that resistance switching took place at the cross point between the top and bottom NW by measuring all resistances between the crossbar terminals after set/reset.Full NW-NW crossbars and hybrid crossbars consisting of a NW crossed by an e-beam deposited metal strip were fabricated and their electrical performance were compared, allowing for a deeper understanding of switching and failure mechanisms toward an optimization of cycling endurance in NW-NW devices.Work at the Molecular Foundry was supported by the Office of Science, of the U.S. Department of Energy(Contract No.DE-AC02-05CH11231)M.-J.Lee et al.,IEDM Tech. Dig. 771 (2007)U.Russo et al.,IEEE Trans.Electron Devices 56,186 (2009)N.A.Melosh et al.,Science 300,112(2003)Y.Dong et al., Nano Lett.8,386(2009)X.Zhao et al.,Appl.Phys.Lett.93,152107(2008)W.Liu,C. M. Lieber,Nature Mat.6,841(2007)
12:45 PM - Q7.12
The Resistive Switching Characteristics of Pt-NiO-Au Segmented Nanowires Synthesized by Electrochemical Deposition.
Sae-eun Lee 1 , Dong-uk Kim 1 , Dong Hyeok Lim 2 , Dong Hyuk Shin 3 , Bongyoung Yoo 1 3 Show Abstract
1 Department of Bionanotechnology, Hanyang University, Ansan Korea (the Republic of), 2 Institute of Physics and Applied , Yonsei University, Seoul Korea (the Republic of), 3 Department of materials science and engineering, Hanyang University, Ansan Korea (the Republic of)
Resistive switching random access memory (ReRAM) has been intensively studied in the form of metal-oxide-metal structures as a strong candidate for the future nonvolatile memory, because of its low power consumption and high scalability between different resistance states. However high reset current and resistance fluctuations are critical barriers for practical utilization. The mechanism of resistive switching is generally accepted that conducting filament is formed and ruptured in the binary oxide when a critical voltage is applied. Recently many researchers proposed that a redox process in the anode interface plays an important role in a resistive switching mechanism. To improve the performances of the resistive memory device, it is important to reduce the thickness of the oxide layer with nano-size at least lower than 50nm. Oxygen vacancies at the interface have very crucial roles for resistive switching. Also, impurity doping could impact on the behaviors of oxygen vacancies and can control the band gap of the interface in the MIM structures. However, so far, influences of doping on a transient metal oxide have been rarely studied. In this study, we report on the fabrication of the Pt-NiO-Au segmented nanowire structure by template directed electrochemical deposition method. The interface in each segment in the nanowire structures are simply synthesized without any etching damages. Nano sized diameter of oxide layer could enhance the surface to volume ratio, resulting in a different switching behavior. Finally so we investigated the changes of switching properties of nanowire structure device by doping the second materials to metal oxide segment.
Q9: Poster Session: Resistive Switch Memories III
Thursday PM, April 28, 2011
Salons 7-9 (Marriott)
9:00 PM - Q9.1
Oxygen Migration at Pt or Cu/HfO2 Interface under Bias Operation: Oxide Based ReRAM Application.
Takahiro Nagata 1 , Masamitsu Haemori 1 , Yoshiyuki Yamashita 1 2 , Hideki Yoshikawa 2 , Keisuke Kobayashi 2 , Yuta Iwashita 1 , Toyohiro Chikyow 1 Show Abstract
1 Advanced Electric Materials Center, National Institute for Materials Science, Tsukuba Japan, 2 NIMS Beamline Station at SPring-8, National Institute for Materials Science, Hyogo Japan
Resistive random access memory (ReRAM) has been proposed as a new application for oxide materials. An oxide sandwiched between two metal electrodes shows reversible electric field–induced resistance switching behaviors. Recently, hafnium oxide (HfO2), which is used as a high-k gate insulator for advanced complementary metal-oxide-semiconductor (CMOS) technologies, has shown resistance switching phenomena and been increased interest in the use of HfO2 and related oxides as potential ReRAM materials. For the oxide based ReRAM, two mechanisms of resistance switching have been proposed. One is the filament model, which comprises the generation and rupture of a metal filament using a metal such as Ag and Cu acting as a fast mobile ion in oxides. The other model is that of oxygen vacancy nucleation at the metal/oxide interface. To put the high-k dielectric oxide based ReRAM on practical applications, understanding on controls of metal/oxide interface is essentially important. Here, we employed hard x-ray photoelectron spectroscopy (HX-PES) under bias operation, which enabled us to observe bias-induced compositional changes around the metal/oxide interface and the oxide film region, to examine the electronic structure of Pt or Cu/HfO2 interface in an operating device.A 30-nm-thick HfO2 layer was deposited on a 100-nm-thick Pt bottom electrode, which was deposited on a sapphire substrate, by employing pulsed laser deposition. 10-nm-thick Pt or Cu top electrodes were formed on the HfO2 film by DC sputtering at room temperature using a shadow mask to define a 3-mm-square electrode. The interface electronic states were measured with HX-PES in the SPring-8 BL15XU undulator beamline. The incident X-ray energy was 5.95 keV and the total energy resolution was 240 meV. In the case of the Pt/HfO2/Pt diode, applying a forward bias increased the Pt–O bonding peak, indicating evidence of Pt electrode oxidization and oxygen vacancy formation around the Pt/HfO2 interface. In contrast, the application of a bias to the Cu/HfO2/Pt diode reduced the copper oxide bonding state, providing evidence of oxygen reduction and Cu diffusion into the HfO2 layer. We achieved direct observation of oxygen migration at the metal/HfO2 interface under device operation, which is the key to controlling the electrical properties of oxide based ReRAM. The relationship between the interface structure and the electrical properties will be discussed in detail.The authors are grateful to HiSOR, Hiroshima Univ. and JAEA/SPring-8 for the development of HX-PES at BL15XU of SPring-8.
9:00 PM - Q9.10
Oxygen-content-dependent Unipolar Resistive-switching Memories of Nonstoichometric TiOx Thin Films.
Jae Hee Park 1 , Keun Yong Lim 1 , Min Choul Kim 1 , Suk-Ho Choi 1 Show Abstract
1 Department of Applied Physics, Kyung Hee University, Yongin, Kyungkido, Korea (the Republic of)
Resistive switching (RS) memory characteristics of Al/TiOx/Pt structures were investigated as a function of oxygen flow rate during TiOx layer deposition. 30 nm TiOx thin films were fabricated on Pt/Ti/SiO2/Si substrates by varying oxygen flow rate from 0.6 to 1.4 sccm during ion-beam sputtering deposition. Al electrodes with 200 µm diameter were deposited on top of the TiOx films to make metal-insulator-metal device structures by thermal evaporation. Reproducible unipolar RS characteristics were observed for 1.1 ~ 1.4 sccm flow rates. For these samples, sufficient resistance ratios of high resistance state (HRS) to low resistance state (LRS) (>100) remained with almost no degradation of resistive switching after over 50 cycles despite some fluctuations of HRS and LRS resistances. Less fluctuations of switching voltage and HRS resistance were observed at smaller flow rate. In contrast, no RS memories were observed for flow rates smaller than 1.1 sccm, possibly resulting from larger-amount metallic Ti in the films. These results are discussed based on the mechanism of conducting-filament formation/rupture associated with defects such as oxygen vacancies and grain boundaries.
9:00 PM - Q9.11
A Survey of Metal Oxides and Top Electrodes for Resistive Memory Devices.
Seann Bishop 1 , Benjamin Briggs 1 , Kevin Leedy 2 , Sree Addepalli 1 , Nathaniel Cady 1 Show Abstract
1 College of Nanoscale Science and Engineering, University at Albany, Albany, New York, United States, 2 AFRL/RYDD, Air Force Research Laboratory, Wright Patterson AFB, Ohio, United States
Resistive memory devices have been fabricated using a wide array of metal oxide insulator/metal electrode combinations. Few studies rigorously compare devices fabricated from multiple electrode/insulator combinations. In this study, Cu2O, HfO2, and TiO2, with four top electrodes (TEs), Ni, Au, Al, and Pt, have been evaluated for resistive memory applications. Devices were fabricated as metal-insulator-metal devices with copper as the bottom electrode. TiO2 films 100 nm thick were deposited by RF sputtering: (1) in an argon atmosphere and (2) in an argon atmosphere with an 0.1% oxygen partial pressure. HfO2 with a thickness of 50 nm was deposited using ALD. Cu2O films were synthesized by partially oxidizing the copper electrode. The TEs were then fabricated by standard patterning techniques. Electrical characterization was performed with sweep mode IV measurements (see the table below). TiO2 devices exhibited similar resistive switching properties when Au (unipolar) and Pt (bipolar) were the TEs. For the latter, set voltages were ~0.7 V, reset voltages were less than -0.4 V, and the ROFF/RON ratio was 10^6. Switching properties differed when Al and Ni were used. For both contact materials, TiO2 deposited in an oxygen partial pressure exhibited diode-like IV curves, while the TiO2 deposited in pure argon showed resistive switching behavior. A distinguishing feature of the TiO2-based devices was contact bubbling and delamination. This phenomenon is well documented by multiple research groups and is thought to be the result of oxygen released from the bulk TiO2. Contact bubbling was most pronounced when Au was the TE. Ultimately, contact bubbling will limit the integration of TiO2-based memory devices with CMOS systems if this issue is not addressed. HfO2-based devices exhibited non-polar switching behavior independent of the TEs and without the need for a forming voltage. In addition, set voltages less than +/-2 V and reset voltages on the order of +/-500 mV were observed with an ROFF/RON ratio of 10^9. Copper oxide devices switched with bipolar behavior with Pt and Al TEs. Our preliminary data suggest that the Cu2O devices with Al TEs switch with more consistent voltages than those fabricated with Pt. For the Cu2O devices with an Al TE, set voltages were ~2 V, reset voltages were less than -1V and the ROFF/RON ratios were >10^3. In summary, this study is one of the first to comprehensively compare the effect of varying both the metal oxide insulator and the metal TE (independently) and evaluate the impact on electrical switching behavior.
9:00 PM - Q9.12
Complementary Resistive Switching for Diode Free Cell Array with TiO2-x Multi Layers.
Yoon Cheol Bae 1 2 , Ah Rahm Lee 1 2 , June Sik Kwak 2 , Jin Pyo Hong 1 2 Show Abstract
1 Division of Nano-Scale Semiconductor Engineering, Hanyang University, Seoul Korea (the Republic of), 2 Novel Functional Materials and Devices Lab, Hanyang University, Seoul Korea (the Republic of)
Different each other TiO2-x multi-layer homo-junctions were explored as resistive switching elements, where TiOx layers were designed to have rich oxygen ion (i.e. oxygen vacancy poor) and TiOy layers were designed to have poor oxygen ion (i.e. oxygen vacancy rich) region. Each bilayer homojunction with TiOx/TiOy and TiOy/TiOx shows bipolar resistive switching behavior. And from depth profile X-ray photoelectron spectroscopy measurement, in the interface region transition of metallic and insulating Ti sub-oxide induced by migration of oxygen ions is the origin of bipolar resistive switching phenomena. And those two switching elements stack for complementary resistive switching structure as the solution of sneak-path problem in a cross bar memory array. In our structure, we could achieve the diode free memory cell with same kind of materials and without any middle electrode.
9:00 PM - Q9.13
Effect of NiO Growth Conditions on the Bipolar Resistance Memory Switching of Pt/NiO/SRO Structure.
Chunli Liu 1 , Chang Uk Jung 1 , Fran Kurnia 1 , ShinBum Lee 2 , SangMo Yang 2 , CheolSeong Hwang 2 Show Abstract
1 Physics, Hankuk University of Foreign Studies, Yongin,, Kyounggi-Do, Korea (the Republic of), 2 Department of Physics, Seoul National University, Seoul, Seoul, Korea (the Republic of)
We deposited NiO thin films with SrRuO3 thin film bottom electrodes on SrTiO3 (001) substrates by using pulsed laser deposition. The growth temperature and the oxygen pressure were varied in order to obtain NiO films with different structural and electrical properties. We investigated the I-V characteristics of the Pt/NiO/SRO structures and observed a strong dependence of bipolar resistance switching on the growth conditions of the NiO thin films. Stable bipolar memory resistance switching was observed only in the devices with NiO films deposited at 400 oC and 10 mTorr of O2. The on- and off-state I-V curves of bipolar switching were fitted to various conduction mechanisms, and the results showed that the on-state followed the Ohmic conduction, and the off-state was governed by the Schottky effect, indicating its origin in the NiO/SRO interface. Our results suggest that the growth conditions of NiO may affect the bipolar switching behavior through the film’s resistance, the film’s crystallinity, or the status of the grain boundaries.
9:00 PM - Q9.15
Forming-free Resistive Switching Characteristics in La2O3 doped HfO2 Thin Films.
Chin Shiang Peng 1 , Su-Jien Lin 1 Show Abstract
1 , National Tsing Hua University, Hsinchu Taiwan
In this study, the effects of the doped La2O3 layer on reversible resistive switching (RS) behaviors of HfO2 thin films is discussed. By first principles calculation, the formation energy of oxygen vacancies can be reduced by trivalent dopant doping in HfO2. For this reason, the La2O3:HfO2 thin films by the multi-stack like structure were deposited. The La2O3 doped HfO2 (La2O3:HfO2) thin films were sequentially deposited on TiN bottom electrode by atomic layer deposition method which control thickness of the oxide film precisely with high quality. The experimental results show that the forming process can be removed by La2O3:HfO2 thin films via a post-annealing process. According to the X-ray diffraction (XRD) patterns, the La2O3:HfO2 thin films remain amorphous before and after post-annealing. The forming-free La2O3:HfO2 memory device shows the reproducible resistive switching behavior and there is no data loss found in the non-destructive readout test under 0.3V. The retention characteristics performed over 105 s at room temperature and 150oC, respectively. The aforementioned results demonstrate the possible application memory of the La2O3:HfO2 memory device.
9:00 PM - Q9.16
Resistive Switching and Electrochromic Multi-level Memory Device.
Wei-Ting Wu 1 , Jen-Sue Chen 1 , Jih-Jen Wu 2 Show Abstract
1 Department of Materials Science and Engineering, National Cheng Kung University, Tainan Taiwan, 2 Department of Chemical Engineering, National Cheng Kung University, Tainan Taiwan
A novel resistance random access memory (RRAM) device combining the electrochromic (EC) and resistive switching performances is firstly proposed. This ECRRAM is achieved by using only one material, tungsten oxide (WO3), as the active layer and it possesses multilevel states which can be easily tuned by varying the applied voltage. The device’s structure is FTO-glass/WO3/Al/LiClO4/ITO-glass. WO3 is a cathodic electrochromic material and possesses the resistive switching behavior, too. This ECRRAM exhibits a repetitive bipolar switching and these two distinct resistance states can be simultaneously operated with the multilevel electrochromic states via different degrees of intercalation/extraction of Li ions. Furthermore, this ECRRAM configuration may be applied in displays, e-books or smart windows integrated with memory cells through a significantly simplified procedure.
9:00 PM - Q9.17
Switching and Memory Effects in Metal-intrinsic Oxide-InSe Structures.
S. Drapak 1 Show Abstract
1 , Frantsevich Institute of Material Sciences Problems, National Academy of Sciences of Ukraine, Chernivtsi Ukraine
The interest to investigations on the structure and chemical composition of the conducting intrinsic oxide (Ox) formed on the surface of layered InSe at various time-temperature regimes is caused by the possibility to use “Ox-InSe” heterocontacts as radiation stable photodiodes, solar cells, sensors of polarized radiation, etc. As follows from the literature data, the Ox formed on the InSe surface consists mainly of In2Se3 at T = 593-693 K; In2Se3, In2(SeO4)3 and In2O3, at T = 693-873 K and In2O3 at T higher than 873 K. It is accepted that any oxide phase on the InSe surface at T less than 593 K is not formed. Recently we have shown that Ox films formed on the InSe surface at Tless than 373 K consists of Se2O5 (dielectric matrix) with the inclusions of nanoparticles of pure In (average size 19-20 nm). The mechanisms of charge transfer in such Ox films are investigated. It is shown that the ohmic I-V characteristic at low fields is due to hopping of thermally excited electrons from one isolated state in the Ox to another. With increasing electrical field the trap-filling and space-charge-limited current regimes become observed. At high fields the current dominated by the Poole-Frenkel effect at T less than 283 K and the Schottky emission at T higher than 593 K. It is established that asymmetry of current transfer in the “Ox-InSe” heterocontacts is due to the different concentration and different distribution of traps on energy at regions closed to the “Ox/semiconductor substrate” and the “Ox/contact at the surface of the oxide films” interfaces. At T higher than 283 K after exposure of samples in high electric fields during 1-3 minutes the switching and memory phenomena in Ox films are observed. And in “high resistivity condition” Ox films are characterized with typical for semiconductor multiple-quantum-well structures or superlattices (including disordered ones) Z- and N-shaped current-voltage characteristic. The qualitative model for interpretation of experimental results is suggested.
9:00 PM - Q9.18
A Three Layer Nano-ionic Conductive Bridge Memristor Experiment Using One Mask.
Steve Wald 1 , Muhammad Rizwanlatif 1 , Nader Rafla 1 , Maria Mitkova 1 Show Abstract
1 College of Engineering, Boise State University, Boise, Idaho, United States
In silicon IC production, generally at least one mask is used for each material layer such as Poly, Metal or Contact, but for our present research it is desired to reduce mask costs, while the amount of processed silicon produced is not a major concern. This paper presents an experimental approach, processing three layers using a single mask intended for formation of a conductive bridge memristor (CBM). The method is extendable in principle to any number of masks, but limited to just a few for practical reasons. Our intent with this method is to build a viable CBM. The memristor is a fourth passive two terminal electronic device, postulated by Leon Chua in 1971, and rediscovered in 2008. Our CBM changes its resistance in response to current passing through it by building up or tearing down a conductive molecular bridge in an otherwise insulating chalcogenide film.The use of a single mask to process our multi-layer experiment has been demonstrated in the laboratory with a Quintel Q4000 contact aligner. The tradeoffs introduced by the scheme are discussed as well as the limitations of alignment equipment for its implementation.Solutions are discussed to the problems of:*Physically creating a single mask to represent three layers of data. *Operating the alignment equipment to match appropriate mask and wafer positions together.*Processing in the presence of large dead spaces between layer sets.Additional problems were encountered in the lab for which we were obliged to seek solutions.*Open mask window size tradeoff.>Our original dark field mask did not have large enough open windows to allow recognition of alignment marks on the wafer through the mask.>We encountered a liftoff problem with the large open windows in a new mask – the liftoff process requires a more matched area profile between features.*Recognition of the true experiment from the false shadow patterns on the wafer.*Limited alignment motion. Our aligner has limited movement in fine adjustment mode which is not quite enough to reach each of the separate mask layer sets. More movement can be achieved with coarse adjustment, but if the coarse limit is neared, fine adjustment cannot be achieved.*The multi-layer mask is not easily usable for working with smaller wafer pieces.*Our photo-resist has a tendency to stick to the original Quartz mask, but is not a problem for Soda-Lime masks.
9:00 PM - Q9.2
Effect of Doping Concentration on Resistive-switching-memory Performance of Cu-doped ZnO Films.
Keun Yong Lim 1 , Min Choul Kim 1 , Chang Oh Kim 1 , Suk-Ho Choi 1 Show Abstract
1 Department of Applied Physics, Kyung Hee University, Yongin, Kyungkido, Korea (the Republic of)
100 nm Cu-doped ZnO films were fabricated on Pt/TiO2/Si substrates by RF magnetron sputtering by varying Cu concentration (nCu) from 0 to 4 mol % and subsequently, Pt electrodes of 200 μm diameter were deposited on top of the films for resistive-switching-memory (RSM) devices. The memory properties including high resistance state (HRS) and low resistance state (LRS) were analyzed by measuring current-voltage curves. All RSM devices exhibited unipolar resistive switching behaviors after forming process, and had similar reset voltages from 0.4 to 0.7 V. The set voltages were uniformly distributed at nCu = 2 and 3 mol %. The conduction in the LRS was completely Ohmic for all devices. The conduction in HRS also obeyed the Ohmic behavior at voltages ≤ 0.4 V, but at voltages > 0.4 V, it followed very different mechanisms depending on nCu; Poole-Frenkel emission mechanism for nCu ≤ 3 mol % and space-charge-limited conduction mechanism for nCu = 4 mol %. The on/off ratio was about 300 at nCu = 3 mol %, whilst it was under 100 at other nCu’s. Both HRS and LRS showed good retention properties with no obvious decay within 104 s for all devices. These results suggest that nCu is an important factor for determining the RSM properties. Possible RSM mechanisms are discussed to explain the experimental results
9:00 PM - Q9.3
The Electrolytic Resistive Switching in Both Amorphous and Crystalline Ag10Ge15Te75 Films.
Zhiguo Liu 1 2 Show Abstract
1 National Laboratory of Solid State Microstructures, Nanjing University, Nanjing China, 2 Department of Materials Science and Engineering, Nanjing University, Nanjing China
Both resistive switching random access memory (RRAM) and phase change random access memory (PCRAM) are regarded as candidates of next generation non-volatile memory. Among them RRAMs based on solid state electrolytes are usually composed of solid state electrolyte film sandwiched between a reactive electrode and an inert electrode and utilize electrochemical control of nanoscale quantities of metal in thin films of solid electrolyte to switch the device by using bipolar electrical pulses. PCRAMs are composed of phase change material films sandwiched between two inert electrodes, in which the resistive switching is due to an amorphous/crystalline phase change caused by thermal effect of unipolar electrical pulses. It is attractive to create a new type of memories by combining the advantages of the two kinds of memories.In this work the amorphous/crystalline phase change behavior and resistive switching behavior of Ag10Ge15Te75 (AGT) electrolyte were investigated. Satisfactory electrolytic resistive switching phenomenon were observed in the memory cells composed of amorphous or crystalline AGT films sandwiched between Ag and Pt electrodes. The measured high and low resistance values of amorphous cells and crystalline cells are in different order of magnitude and constitute 4 distinguishable states. It is proposed that if the repeated and reversible electrically driven amorphous/crystalline phase change of these cells can also be realized, together with controlling and using the electrolytic resistive switching in amorphous and crystalline cells a new type of 4-state memory might be created. As another step towards this goal, the electrically driven amorphous/crystalline phase change has been achieved in the AGT cell composed of AGT films sandwiched between top and bottom Pt electrodes. Further work is now on the way.
9:00 PM - Q9.4
Bipolar Resistive Switching Characteristics in Ag/ZnO/Pt Schottky Diodes.
Zi-Jheng Liu 1 , Jyun-Yi Wu 1 , Jon-Yiew Gan 1 , Su-Jien Lin 1 , Tai-Bor Wu 1 Show Abstract
1 Department of Materials Science and Engineering, National Tsing-Hua University, Hsinchu Taiwan
Conductive bridging random access memory (CBRAM) has received considerable attention duo to potentially excellent properties of nonvolatility, simple structure, small cell size, reliable endurance and retention. In this work, switchable Ag/ZnO/Pt diodes were prepared by radio frequency magnetron sputtering, and the initial rectifying behaviors can be controlled by the deposition parameters of ZnO thin films. The origin of rectification is ascribed to the asymmetric Schottky barriers at the Ag/ZnO and ZnO/Pt interfaces. In addition, the voltage and current-driven resistive switching characteristics have also been studied. The Ag/ZnO/Pt diodes exhibited reproducible bipolar switching behaviors with a narrow dispersion of the resistance states. We suggest that the bipolar resistive switching phenomenon may be caused by the electrochemical formation and annihilation of a silver filament which penetrates along the grain boundaries of c-axis textured ZnO thin films.
9:00 PM - Q9.5
Nonvolatile Resistance Switching in Ruthenium Doped Zinc Oxides.
Shih Ming Lin 1 Show Abstract
1 , National Tsing Hua University, Hsinchu Taiwan
ReRAM used resistance switch to be data memory. When resistance is from HRS (high resist. state) to LRS (low resist. state) which be called SET or ON state. Then, resistance is from LRS to HRS which be called RESET or OFF. Zinc oxide is common materials to be RRAM. That is simple to fabricate ZnO insulator for RRAM and there are high stable resistance switch, endurance cycles, large ON/ OFF ratio and so on.ZnO RRAM belongs to VCM (valence change memory) which used anion oxygen to transport. It is important role that defects makes ZnO film has filament effect to switch resistance. Using RuO2 doped ZnO fabricated “I” of “MIM” structure to find higher switch speed and endurance cycles. ZnO thin films of 50nm thick were deposited on Pt/Ti/SiO2/Si substrates at room temperature by rf magnetron sputtering with an Ar working pressure of 5×10−3Torr using a ceramic RuO2 doped ZnO target. First of all, Pt top electrodes of 220 μm in diameter were deposited by RF magnetron sputtering with a metal shadow mask. The typical I-V resistive switching characteristic was observed on the Pt/RZO/Pt capacitor. ZnO films are extensively used as TCO (transparent conducting oxide). Second of all, TCO films substitute for Pt to be top electrode and were deposited on RZO/TCO/glass substrate. In 20% H2 and Ar mixed gas, the ZnO: RuO2 films nearly 100 nm thick were deposited on RRAM insulator to be TCO/RZO/TCO structure. The results indicate that Pt/RZO/Pt capacitor I-V switching characteristic was forming voltage in this work is about 13V, and the values of HRS are somewhat fluctuant in the early cycles but become quite steady after 20 cycles. In addition, the influences of RuO2 doped on bonding conditions have also been studied.
9:00 PM - Q9.6
Improved Resistive Switching Characteristics in ZnO Thin Films by Ti Doping.
Zhenguo Ji 1 , Qinan Mao 1 2 Show Abstract
1 College of Materials and Environmental Engineering , Hangzhou Dianzi University, Hangzhou, Zhejiang, China, 2 Department of Materials Science and Engineering, Zhejiang University, Hangzhou, Zhejiang, China
Recently, resistive random access memory (RRAM) has been intensively studied because it is regarded as a potential candidate for the next generation non-volatile memory. Compared with FLASH, it has the advantages of fast writing speed, high density storage and simple device structure. Despite these superior characteristics, improvements should be made in RRAM before it is put into commercial production. Switching voltage instability is one of the main issues during resistive switching, which may lead to write failure and operating confusion. Here, we report improvement of resistive switching in ZnO by Ti doping. Pt/ZnO:Ti/n+-Si structures were fabricated. In these structures, ZnO thin films with various Ti doping concentration were realized by cosputtering of Zn and Ti metal targets. Unipolar resistive switching phenomena were observed in all the samples. Compared with the undoped ZnO, the operation voltage dispersion and the endurance of write cycle are improved in Ti-doped ZnO. The resistive switching characteristics are optimized in ZnO with 2% Ti concentration. These improvements are attributed to more oxygen vacancies induced by Ti doping.
9:00 PM - Q9.7
Resistive Switching Characteristics of ZnO Thin Films Fabricated by Atomic Layer Deposition Process.
Kuan-Yu Chou 1 , Hsin-Wei Huang 1 , Tai-Bor Wu 1 , Su-Jien Lin 1 Show Abstract
1 Department of Material Science and Engineering, National Tsing-Hua University, Hsinchu Taiwan
Recently, resistance random excess memory (RRAM) has attracted great attention because of its potential to replace flash memory in next generation nonvolatile memory applications. The current-voltage (I-V) characteristics of the metal-insulator-metal (MIM) structure exhibit an extreme change of resistance between the high resistance state (HRS) and low resistance state (LRS) for logic signal (off and on states). Among many materials, the binary oxides are more compatible with semiconductor manufacturing process. In our previous work, ZnO had reliable and stable resistive switching behavior on the Pt/ZnO/Pt structure. ZnO also has several advantages such as abundant availability in nature, rugged structural and chemical behavior, highly evolved growth technologies, environmental friendliness, and compatibility with complementary metal oxide semiconductor technology. In our preceding work, we used radio frequency (RF) sputter to deposit ZnO films. In this study, we choose atomic layer deposition (ALD) due to its precise control of film thickness and high coverage ability. And this device fabrication method hasn’t been used. We prepared different film thicknesses to find out their resistive switching properties. Then we apply heat treatment like rapid thermal annealing to improve RRAM properties. Finally, devices are characterized by a combination of (1) scanning electron microscopy (SEM) to analyze surface microstructure, (2) high resolution transmission electron microscopy (HRTEM) to analyze surface microstructure and element analysis, (3) X-ray photoelectron spectroscope (XPS) to analyze element components, (4) X-ray diffraction (XRD) to analyze crystallinity, and (5) current-voltage (I-V) measurement to analyze resistive switching characteristics.
9:00 PM - Q9.8
Transparent Resistive Random Access Memory Based on Homojunction and Heterojuction Stacked Structures.
Chan-Yu Tseng 1 , Su-Jien Lin 1 Show Abstract
1 , National Tsing Hua University, Hsinchu Taiwan
Fully transparent resistive random access memory (TRRAM) devices were successfully prepared by radio frequency magnetron sputtering. The TRRAM devices composed of a ZnO thin film sandwiched between indium tin oxide (ITO) or aluminum-doped zinc oxide (AZO) electrodes exhibited reliable endurance and retention behaviors. However, the ITO/ZnO heterojunction and AZO/ZnO homojunction may induce different resistive switching characteristics, such as the resistance ratio, switching voltage, and conduction mechanisms dominating the low and high resistance states. The observations and experimental results suggest that the resistive switching phenomenon may result from the connection and rupture of a conducting filament consisted of movable oxygen vacancies.
Orlando Auciello Argonne National Laboratory
Panagiotis Dimitrakis Institute of Microelectronics
Yoshihisa Fujisaki Hitachi Ltd.
Eisuke Tokumitsu Tokyo Institute of Technology
Dirk Wouters IMEC
Applied Materials Inc
M. Watanabe &
Park Systems Corporation
Universal Systems Co., Ltd
Q10: Resistive Switch Memories IV
Friday AM, April 29, 2011
Room 3002 (Moscone West)
9:30 AM - **Q10.1
Materials and Device Optimization for Nanoscale Resistive Random Access Memories (ReRAMs) Based on the New Anderson-Mott Correlated Electron RAM (CeRAM) Device Paradigm Concept.
Carlos Paz de Araujo 1 2 , Jolanta Celinska 2 , Xue Kanhao 2 , Chris McWilliams 2 , Dave Czaplewski 3 , Wei Li 4 , Orlando Auciello 3 4 Show Abstract
1 , University of Colorado at Colorado Springs, Colorado Springs, Colorado, United States, 2 , Symetrix Corporation, Colorado Springs, Colorado, United States, 3 Center for Nanoscale Materials, Argonne National Laboratory, Argonne, Illinois, United States, 4 Materials Science Division, Argonne National Laboratory, Argonne, Illinois, United States
Resistive Random Access Memories (ReRAMs) are ideally suited for nanoscale integration of System-on-Chip Non-volatile Memories because of their scalability and materials compatibility with advanced CMOS. However, stable devices suitable for operation in nanoscale regimes are still elusive after more than seven years of research. This review describes a ReRAM device concept under optimization both from the device and material models point of views for which storage states, transport and switching properties are based on the Anderson-Mott (AM) phase transition paradigm. In such a case, the Metal-Insulator (MI) transitions relating to the two resistance states of the ReRAM, are caused by electron and hole doping conditions which modify the electron-electron correlation responsible for the two configurations of the Transition Metal Oxide (TMO) density of states (DOS). In this new device concept paradigm, named by us as Correlated Electron Random Access Memory (CeRAM), the device performance optimization is based on control of oxygen vacancies, ion excess and depletion, non-electroforming oxide material (NiO) preparation, and doping, using transition and non-transition metal species, and materials synthesis, all aimed at control of the density-of-states (DOS). Nanoscale devices from 70 to 20 nm line width are investigated, demonstrating the effectiveness of the optimization strategies and area dependence of the parasitic diode contained in the intrinsic device. The unique CeRAM device operating principle is based on the presence of carbonyl species at the electrode/NiO interfaces, with tailored C:Ni ratios, which control surface morphology and electron doping and are key in achieving device stability. Optimization of device performance is achieved by using metallorganic decomposition (MOD) for synthesis of NiO layers and doping, which results in exceptional memory retention up to 400°C.The applicability of the AM model to the characteristic MI transitions of the ReRAM switching and storage mechanisms is demonstrated and used to guide device development and optimization based on correlated electrons, as opposed to the conventional oxidation-reduction mechanisms and other interpretations based strictly on oxygen vacancies filament region models.This work was supported by US Department of Energy, Office of Science, Office of Basic Energy Sciences-Materials Science. The Use of the Center for Nanoscale Materials and Electron Microscopy Center was supported by the U. S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.
10:00 AM - Q10.2
Electronic Resistance Switching in Si-based RRAM Devices: The Nanometallicity Concept.
Albert Chen 1 , Byung Joon Choi 1 , Xiang Yang 1 , Soogil Kim 1 , I-Wei Chen 1 Show Abstract
1 Materials Science and Engineering, University of Pennsylvania, Philadelphia, Pennsylvania, United States
A new type of electronic resistance switching was found in Si-based random solid solutions that may be used for non-volatile memory. Conventionally, metallic random material must contain electrons that can travel an infinite distance, but a random material in which electrons can travel only a finite distance (at 0K) ζ is still regarded as an insulator. In a film thinner than ζ, however, this random material is conducting across the thickness just like a metal. Following this concept of “nanometallicity”, we have used SiO2 or Si3N4 with atomically dispersed Pt to design a device that can reversibly switch between the nanometallic metallic and insulating states under a voltage stimulus. The film has a thickness (10-30 nm) less than the initial ζ, and is conducting in the virgin state; then a critical voltage of a few V triggers electron trapping that shortens ζ and renders the film insulating. The switching behavior is purely electronic—the insulator to metal transition can be triggered by UV without a voltage, and the switching voltage is independent of temperature and switching speed. The switching polarity and voltages are predictably correlated to the work functions of the top and bottom electrodes (Pt, Mo, SrRuO3, Ag, Ta) and the electron affinity of the dielectric matrix (SiO2 or Si3N4). The I-V features of an abrupt “set” transition (metal to insulator) and multi-step “reset” transitions (insulator to metal)—at lower voltages, further depict the nature of charge-trapping states: the trapped electrons have a higher energy than itinerary electrons due to charge localization, and they interact with itinerary electrons via Coulomb repulsion. The switching behavior is highly stable and uniform; the standard deviation of the switching voltage/resistance is only 6%. These and other characteristics (long retention time, fast switching speed and good scalability) make this device a good new candidate for RRAM.
10:15 AM - Q10.3
Feasibility of a Purely Electronic-switching Memory in SiO2 Thin Films with Dispersed Pt: A Device Viewpoint.
Byungjoon Choi 1 , Albert Chen 1 , Xiang Yang 1 , Soogil Kim 1 , I-Wei Chen 1 Show Abstract
1 Materials Science & Engineering, University of Pennsylvania, Philadelphia, Pennsylvania, United States
Resistance switching random access memory (RRAM) has attracted considerable interest because of fast write/read access, high write/erase cycle number and scalability. Although most RRAMs rely upon ionic transport and/or redox mechanisms, purely electronic switching is also possible in wide band gap materials by charge storage either at the interface or at immobile traps in the bulk. Simmons and Verderber demonstrated such a device, but it required a high voltage (~10V) and a long dead time (for charge migration) because of the shortage of the trap sites in the amorphous insulator. Considering these and other problems of electronic switching, Waser et al. concluded that a purely electronic switching device will face an insolvable “voltage-time dilemma”: that the requirements of a long retention time (10 years) and a short read/write pulse (<100ns) for a highly integrated memory are incompatible. In this study, we will report the device characteristics of an amorphous SiO2 thin film with dispersed Pt, which provides both the conducting paths and the trap sites, that has overcome this dilemma. With a Mo bottom electrode and a lithographically patterned Pt top electrode, this device showed a very uniform and reliable bipolar resistance switching behavior with a fast operation speed (<100ns), a Roff/Ron ratio > 100, and a >10 years retention time under a low reading voltage. Further device characterization measured the actual transient pulse voltage and current supplied to the cell during sub-100ns switching, the waveform oscillation during SET operation due to charge trapping, and the AC impedance of various resistance states reflecting different electronic connectivity. A new scalability strategy taking advantage of a novel (exponential) thickness dependence of the Roff (high resistance state) will be introduced to direct future integration of high density memory.
10:30 AM - Q10.4
Resistive Switching Characteristics of Maghemite Nanoparticle Assembly.
Tae-sik Yoon 1 , Quanli Hu 1 , Sung Mok Jung 2 , Hyun Ho Lee 2 Show Abstract
1 Department of Nano Science and Engineering, Myongji University, Yongin, Gyeonggi-do, Korea (the Republic of), 2 Department of Chemical Engineering, Myongji University, Yongin, Gyeonggi-do, Korea (the Republic of)
Resistive switching random access memory (ReRAM) operates by the resistance change of metal oxides between high resistance state (HRS) and low resistance state (LRS) by the externally applied electric field or current. The resistive switching characteristics of the assembly of maghemite (γ-Fe2O3) nanoparticles having a diameter of ~ 10 nm were investigated in the structure of Al/γ-Fe2O3 nanoparticle multilayer (~ 300 nm thick)/Al-plate. The nanoparticle multilayer on Al plate was formed by repeating dip-coating processes. The multilevel (five states) resistive switching was observed with the average resistance values of 4.8×105, 2×105, 6.5×104, 8.6×103, and 2.7×103 Ω, depending on the externally applied voltage. The multilevel switching is thought to originate from the repetitive and reversible formation and rupture of multiple conducting filaments through local phase transition of γ-Fe2O3 nanoparticles. The local compositional change (atomic redistribution) should be accompanied for the phase transition of γ-Fe2O3 nanoparticles. In particular, the nanoparticle assembly has large volume of interface between nanoparticles, where the atomic density is much lower than that inside the nanoparticles. These interfaces can afford to accept or donate the atoms and vacancies. As a result, they facilitate efficiently the redistribution of atoms and vacancies for the local phase transition of nanoparticles. The electrical conduction in nanoparticle assembly follows Ohmic conduction at low voltage and space charge limited current (SCLC) conduction as increasing the voltage owing to the presence of interface traps between nanoparticles. Though a further study is required, the facilitated formation and rupture of multiple filaments in the γ-Fe2O3 nanoparticle assembly demonstrates the feasibility for the application to multilevel resistive switching elements.
10:45 AM - Q10.5
Planar Non-volatile Memory based on Metal Nanoparticles.
Asal Kiazadeh 1 , Henrique Gomes 1 , Ana Da costa 1 , Jose Moreira 1 , Dago De Leeuw 1 , Dago De Leeuw 1 , Stephen Meskers 1 Show Abstract
1 Center of Electronics Optoelectronics and Telecommunications (CEOT), University of Algarve , Gambelas, Algarve, Portugal
Metal nanoparticles embedded in an insulating matrix can lead to electrical resistive switching. The phenomenon is being intensively investigated. The objective is to develop a resistive random access memory (RRAM), a possible competitor for: flash memories, dynamic RAM and hard-disk drives. In this work we characterize resistive switching properties of metal nanoparticles hosted in a insulating matrix (such as poly(N-vinyl-2-pyrrolidone). As a novelty, we fabricated and characterised planar structures (in contrast with prevailing sandwich type structures). Furthermore, planar structures have the conduction channel exposed and accessible to surface analytical techniques (SEM, AFM) providing access to a detailed analysis upon electrical switching. The non-volatile memories have on/off resistance ratio as high as 103 under an electrical field of a few kV/m. These devices exhibit good sweep endurance and good retention time (months). In spite of dramatic changes in the resistance upon switching, the transport remains weakly thermal activated (meV) suggesting that nanoparticles will not aggregate into a metallic conductive filament. The observed current-voltage (I-V) characteristics appear to be dominated by space-charge-limited-current (SCLC) conduction. It is also shown that the electrical conductivity of the host matrix plays a crucial role on the ability of the system to develop resistive switching phenomena.
11:30 AM - Q10.6
Resistive Random Access Memories (RRAMS) Based on Metal-oxide Polymer Structures: Switching Dynamics.
Paulo Rocha 1 , Henrique Gomes 1 , Dago Leeuw 2 , Stefan Meskers 3 Show Abstract
1 Center of Electronics Optoelectronics and Telecommunications, Universidade do Algarve, Faro Portugal, 2 Research Labs, Philips, Eindhoven Netherlands, 3 Molecular Materials and Nanosystems, Eindhoven University of Technology, Eindhoven Netherlands
The ability of a metal/oxide polymer memory to switch reversible between two different resistance states is controlled by a number of processes not yet fully elucidated. The most well-know is the one referred as “dead-time” which impedes switching at high repetition rates. In this contribution it is shown that besides the dead time constant, other mechanisms can influence the dynamic response to a programming pulse.This study addresses non-volatile memories based on metal-aluminum oxide polymer diodes. We make a thorough investigation into the dynamic behavior by recording current-voltages characteristics with varying voltage ramp speed. It is demonstrated that these structures have an internal capacitive double-layer structure, which inhibits the switching at high repetition rates. This behavior is explained in terms of an equivalent circuit where the oxide layer is shunted at high voltage ramp rates For the case of single switching events, it is shown that the time to switch from a high resistance to a low resistance state depends exponential on the applied voltage and this time to switch is thermally activated. The physical mechanism behind this process is also discussed.
11:45 AM - Q10.7
Retentivity of RRAM Devices Based on Metal / YBCO Interfaces.
Carlos Acha 1 2 , Alejandro Schulman 1 2 Show Abstract
1 Physics, University of Buenos Aires, Buenos Aires Argentina, 2 , IFIBA (CONICET), Buenos Aires Argentina
The retention time of the resistive state is a fundamental parameters that characterizes the utility of a memory device. Besides this technological necessity, the knowledge of the mechanism beneath the time relaxation of the information state may be essential to improve their performances. Here, we focus our attention to RRAM devices based on metal / YBCO interfaces.We found that after producing the switching of the resistance from a low to a high state or vice versa, the resistance evolves to its previous state in a small but noticeable percentage. We have measured long relaxation effects on the resistance state of devices composed by metal (Au, Pt, Ag) / ceramic YBCO interfaces. This time-relaxation can be described by a stretched exponential law that is characterized by a power exponent n=1/2, which is typical of hierarchical processes. The origin of the relaxation effect can be related to oxygen diffusion processes which were recently associated to the mechanism of bipolar switching. The characteristics of the relaxation effects pointed out by our work may reveal the particular mechanism that dominates the diffusion process.
12:00 PM - Q10.8
Direct Imaging of Microstructural and Electronic Changes during Resistive Switching in PrCaMnO via In-situ Transmission Alectron Microscopy.
Stephanie Raabe 1 , Jonas Norpoth 1 , Malte Scherff 1 , Bjoern-Uwe Meyer 1 , Joerg Hoffmann 1 , Dong Su 2 , Lijun Wu 2 , Yimei Zhu 2 , Christian Jooss 1 Show Abstract
1 Institute of Materials Physics, University of Goettingen, Goettingen Germany, 2 Dept. of Condensed Matter Physics and Materials Science, Brookhaven National Laboratory, Upton , New York, United States
Persistent resistance changes under electric stimulation in metal-oxide sandwich structures show an extremely rich phenomenology depending on complex issues such as electric history of the samples, electrode materials, oxygen deficiency, interface structure and synthesis and preparation details. Electrochemical processes and charge injection seems to be key basic elements for understanding electrically induced microstructural changes, however, a major open issue is to identify whether the resulting changes are dominant at the interface or within the functional oxide, and how they result in changes of electronic properties and electric transport mechanisms. Using a piezo-controlled nanotip in a transmission electron microscope, the structural and electronic changes induced by the switching between high- and low resistance states are directly observed in Pr0.68Ca0.32MnO3 thin films sandwiched by noble metal electrode materials (Pt, Au, Ag). During electric stimulation, the formation of a high resistance state can be related to a structural phase transition to the well-known charge-ordered state and its incommensurate variant. It is accompanied by oxygen vacancy migration and resulting change in the Mn valence which is measured by annular dark field imaging combined with electron energy loss spectroscopy. Based on a detailed structural modeling of the observed incommensurate lattice modulation, we discuss the relation between oxygen vacancy-induced changes in doping, disorder and the implications for the electric transport mechanism. This sheds light onto the role of long range polaron ordering, polaron trapping, disorder in the octahedral tilt system and oxygen vacancies for the formation of switchable high resistance states.
12:15 PM - Q9.9
Structural and Electrical Properties for VO2 Thin Films Grown on TiO2 (100) Substrate by Low Pressure Chemical Vapor Deposition.
Xing Zhong 1 2 , Xueyu Zhang 1 4 , Patrick LeClair 1 2 , Arunava Gupta 1 3 4 Show Abstract
1 MINT Center, University of Alabama, Tuscaloosa, Alabama, United States, 2 Department of Physics and Astronomy, University of Alabama, Tuscaloosa, Alabama, United States, 4 Department of Chemistry, University of Alabama, Tuscaloosa, Alabama, United States, 3 Department of Chemical and Biological Engineering, University of Alabama, Tuscaloosa, Alabama, United States
Epitaxial vanadium dioxide (VO2) thin films have been deposited on TiO2 (100) substrates in order to study the nature of the metal-insulator transition, and its potential application to non-volatile resistive memories. Structural characterization indicates an elongation of the in-plane b- and c-axis and a compression of the out-of-plane a-axis. This results in a reduction of the metal-insulator transition temperature (TMI) from 341 K for the bulk to 325 K for the deposited films. The crossover from the low-temperature insulating state to the high-temperature metallic state has been further characterized by impedance spectroscopy from 100 Hz to 1 MHz. Below TMI, the films behave as a parallel RC network, while above TMI the capacitance of the film vanishes and the resistance drops sharply. In the insulating phase, the capacitance remains roughly constant with decreasing temperature, while the resistance increases. These results suggest a transition from metallic to hopping conductivity upon crossing TMI. The implications of these results for high-speed nonvolatile memories will be discussed.
12:30 PM - Q10.10
Vertical Integration of a-Si Based Crossbar Array on CMOS Circuits for Memory Applications.
Kuk-Hwan Kim 1 , Siddharth Gaba 1 , Wei Lu 1 Show Abstract
1 EECS, Univ. of Michigan, Ann Arbor, Ann Arbor, Michigan, United States
We report 3D vertical integration of nanoscale a-Si based crossbar switch arrays on CMOS circuits. The nanoscale resistive switching devices were based on our previous studies using a-Si as the active layer. However, to obtain rectifying behavior at on-state with minimal current at reverse bias to prevent crosstalk in the array, poly-Si was used previously as the local bottom electrode. The high temperature process of poly-Si deposition, on the other hand, is not compatible with CMOS integration in a back-end-of-line process. In this study, alternative local electrode materials such as polycrystalline SixGe1-x film were investigated. It was found that with careful control of the surface roughness and Ge concentration of the SixGe1-x film, built-in diode characteristics can be preserved in the device fabricated at temperature of 400oC or lower, with favorable resistive switching characteristics including speed, endurance and retention. Detailed studies of XPS, XRD, and AFM data from various films will be also presented in this report. Finally, a 10 by 10 crossbar array with 300nm pitch was directly integrated on top of a CMOS chip fabricated using 180nm technology node, after solving issues such as temperature budget, surface roughness, and overlay between memory array and CMOS vias. The CMOS chip in this study provides address decoding while the crossbar array provides high-density, multi-value memory storage. This demonstration of 3D, vertical integration of crossbar memory with CMOS circuitry could possibly be used in high-density memory and neuromorphic applications.
12:45 PM - Q10.11
Fabrication, Characterization and Modeling of a Metal Oxide Memristive Device.
Ting Chang 1 , Patrick Sheridan 1 , Wei Lu 1 Show Abstract
1 , University of Michigan, Ann Arbor, Michigan, United States
A memristor is essentially a two-terminal electronic device whose conductance can be continuously modulated by controlling the charge or flux through it. Due to its unique characteristics, great attention has been drawn from various fields of studies including, but not limited to, resistive random-access memory (RRAM), synaptic computation, neuromorphic systems, Boolean logic implementation, and signal processing, and analog/digital circuit design. Here we report our studies on nanoscale memristive devices using tungsten oxide as the switching layer. The devices show the characteristics of a flux-controlled memristor such that the conductance change is governed by the history of the applied voltage signals, leading to synaptic behaviors including long-term potentiation and depression. The memristive behavior is attributed to the migration of oxygen vacancies upon bias which modulates the interplay between Schottky barrier emission and tunneling at the WOX/electrode interface. Furthermore, a physical model incorporating ion drift and diffusion effects using an internal state variable representing the area of the conductive region has been proposed to explain the observed memristive behaviors. A SPICE model has been further developed that can be directly incorporated into existing circuit simulators. This device can be fabricated with low-temperature processes and has potential applications in memory as well as analog circuit components. Simple circuits using the memristors as active components will also be discussed.