Graphene Nanoribbon-Based Field-Effect Transistors for High-Performance Logic Technology

Silicon has powered computing for decades through miniaturization, facilitated by innovations such as strained silicon, high-k dielectrics, fin field-effect transistor (FinFET), and the latest industry trend: gate-all-around FET (GAAFET) architectures. However, silicon is reaching its limits as miniaturization yields diminishing benefits. This necessitates a new 'wonder' material that can potentially take some pressure off silicon’s shoulders and meet the increasing demands of computationally intensive technologies such as AI. Bottom-up synthesized, atomically precise graphene nanoribbons (GNRs) feature extremely high theoretical charge carrier mobility and on-state drive current capability at the atomic scale, making them highly promising transistor channel materials over silicon for high-performance logic applications. In this invited talk, I will begin with an introduction to GNRs, explaining the features that make them promising for FETs, detailing the bottom-up synthesis, discussing techniques used for their characterization and device fabrication, presenting the current state of the art with transistors made from them, and addressing the remaining key issues. In the next part, I will detail our recent studies, involving enhancing electrostatic control of the GNR channel through the deposition of an ultrathin high-k top HfO₂ dielectric layer, ultimately scaling transistors with GNRs, and optimizing the channel-contact interface through contact engineering to reduce contact resistance. Finally, I will address the remaining challenges and potential enhancements in materials, processes, device integration, and related areas that could enable GNRs to approach outstanding theoretical predictions and explore future opportunities in the field.