Chalcogenide-Superlattice Interfaces and Intermixing Modulating Phase-Change Memory Performance

Phase change memory (PCM) based on chalcogenide-superlattices has shown promise with the low-power operation and low resistance drift required for neuromorphic computing applications [1-3]. However, the effects of the <i>internal </i>chalcogenide<i>-</i>superlattice interfaces (interface density and degree of intermixing) on superlattice PCM devices are not well understood to date, especially when these interfaces are very dense, just a few Angstroms apart.<br/><br/>Here, we uncover a key correlation between the internal superlattice (SL) interfaces and superlattice PCM (SL-PCM) device performance using nanometer-thin layers of Ge₂Sb₂Te₅ and Sb₂Te₃. We uncover that both switching current density and resistance drift coefficient decrease as the SL period thickness is reduced (i.e., higher interface density) – however, interface intermixing within the SL increases both. The signatures of distinct vs. intermixed interfaces also show up in scanning transmission electron microscopy (STEM), X-ray diffraction (XRD), and thermal conductivity measurements of our SL films.<br/><br/>To understand the role of SL interfaces, we sputtered alternating layers of phase-change chalcogenides Sb₂Te₃ (ST) and Ge₂Sb₂Te₅(GST) with varying period thicknesses, while keeping the total stack thickness fixed (~65 nm). High-resolution STEM images of a 2/1.8 nm/nm ST/GST SL, reveal atomically sharp interfaces separated by van der Waals (vdW) gaps, representing a good quality SL. In contrast, an ST/GST SL with the sub-nm thin period (0.5/0.45 nm/nm) shows stronger intermixing within layers, more stacking faults, and rougher interfaces. We note that for this SL, the individual ST/GST layers are smaller than the unit block thicknesses of ST (1 nm) and GST (1.8 nm); therefore, a higher intermixing is expected. XRD spectra for the as-deposited SLs confirm their polycrystallinity, while non-out-of-plane peaks appear in the more intermixed SL spectra.<br/><br/>The measured thermal conductivity of our SLs decreases with the increasing number of interfaces i.e., with decreasing period thicknesses from 16/14.4 nm/nm (4 interfaces) to 2/1.8 nm/nm (32 interfaces). This is attributed to the vdW-like gaps impeding cross-plane thermal transport [4]. However, the thermal conductivity increases for more intermixed SL films due to loss of vdW-like gaps within the SL, also evident from our STEM.<br/><br/>Electrical measurement of our fabricated mushroom-cell ST/GST SL-PCM devices (110 nm bottom electrode diameter) reveals that the reset current (<i>I</i>_reset) decreases with an increasing number of SL interfaces, due to improved heat confinement. Low and high resistance states of the devices also increase with more interfaces pointing to higher cross-plane resistivity due to more interfaces. However, a larger <i>I</i>_reset in the more intermixed SL-PCM (0.5/0.45 nm/nm) highlights the detrimental effect of intermixing within SL layers. Resistance drift coefficient (<i>v</i>) also shows a clear trend with the number of interfaces with <i>v</i> decreasing from GST (no internal interfaces) to SL with 4 interfaces to ST/GST SL with 32 interfaces. On the other hand, deliberate intermixing within SL (0.5/0.45 nm/nm) increases <i>v</i>. Utilizing such correlation between SL-PCM key performance indicators and SL interface property, we simultaneously achieve low switching current density (3-4 MA/cm²) and low resistance drift coefficient (0.002) in ST/GST SL-PCM, approaching the best corner on the PCM technology.<br/><br/>In summary, we demonstrated that the key material and thermal properties of SLs are controlled by the number of interfaces and their degree of intermixing, which ultimately plays a crucial role in controlling SL-PCM device performance. These results also provide key insights towards new superlattice material design and optimization for SL-PCM technology.<br/><br/>1. A.I. Khan, E. Pop et al., Science <b>373</b>, 1243 (2021)<br/>2. K. Ding et al., Science <b>366</b>, 210 (2019)<br/>3. A.I. Khan, E. Pop et al., IEEE EDL <b>43, </b>204-207 (2022)<br/>4. H. Kwon, E. Pop et al., Nano Lett. <b>21</b>, 5984 (2021)