Atomic Precision Patterning and Alignment for Dopant-Based Quantum Devices

Hydrogen Depassivation Lithography (HDL) using an STM tip has become established as a method for atomic-precision patterning for 2D dopant-based devices. Patterning is required over multiple length scales. For devices such as the ‘single atom transistor’[1], single dopant atoms need to be placed precisely relative to other device elements, such as electrodes, gates, and other single dopant atoms. For 2D quantum metamaterials [2], arrays of dopant patches, either single dopants or small clusters of dopants, must be placed with atomic precision relative to each other, as the coupling strength changes significantly with each dimer row (0.768 nm) of spacing. At a larger length scale, these atomic-level device elements need to be connected to µm-scale bond pads, which are used to connect the buried dopant structures to the outside world. With multiple dopant species, such as in bipolar junction transistors, the second dopant pattern must be aligned with atomic precision to the first dopant pattern.<br/>We are developing automated STM lithography tools to improve the throughput of the patterning process, and create a viable manufacturing process for atomically-precise devices.<br/>First, the patterning process requires extremely high precision in positioning of the STM tip to perform the lithography. At the atomic scale, the major sources of position error are piezo creep and thermal drift. On the larger scale of the interconnects and bond pads, hysteresis errors also become significant. For accurate device patterning, position errors at both length scales need to be corrected. In our control software, we perform real-time corrections of creep, hysteresis and drift to mitigate these position errors. The error correction algorithms require careful calibration. We have developed scripts which measure the creep, drift and hysteresis and enable us to calibrate these error correction processes. Fine adjustments to the correction coefficients are still typically required. For array patterning, the various different types of errors result in different distortions of the written array. Images of written arrays can therefore allow us to identify which type of error correction needs adjusting.<br/>For the automated patterning of large device elements, we create device patterns in a standard CAD program, and convert the pattern into a script file, comprising a list of STM tip vectors; the pattern is then created automatically without further human oversight.<br/>For bipolar devices, we pattern the n-type regions first, incorporate the dopants, then repassivate the substrate. A second round of patterning and dopant incorporation is then required for the p-type regions that must be aligned to the n-type regions. To achieve this alignment, we find that normal topographic STM imaging does not give good contrast of the incorporated dopants. We have developed a high-speed dI/dV imaging method [3], which provides much stronger contrast of the incorporated dopants, and allows much more precise alignment.<br/>With a combination of these methods, we hope to develop an automated atomic-precision manufacturing process for 2D dopant-based devices.<br/>[1] M. Fuechsle, J. A. Miwa, S. Mahapatra, H. Ryu, S. Lee, O. Warschkow, L. C. L. Hollenberg, G. Klimeck, and M. Y. Simmons, <i>Nat Nano</i> <b>7</b> 242-246 (2012)<br/>[2] https://www.zyvexlabs.com/2d-workshop/workshop-overview/<br/>[3] Alemansour, H. <i> et al. </i> High Signal-to-Noise Ratio Differential Conductance Spectroscopy. <i>J. Vac. Sci. Technol. B</i> <b>2021</b>, <i>39</i>, 010601.