Diamond Integration on GaN HEMTs: Overcoming the Challenges for Device-Level Thermal Management

In the realm of higher frequency devices, where the gain is of utmost importance, the effective management of heat becomes crucial to maintain Power Added Efficiency (PAE) [1]. Ensuring efficient heat removal necessitates minimizing the thermal boundary resistance (<i>TBR</i>) between the heat source and the heat spreader, as well as establishing a low thermal resistance path to the heat sink [2]. The integration of diamond near the hot spot holds excellent potential due to its exceptional thermal properties. By incorporating diamond, heat can be effectively spread, thereby enhancing the heat transfer coefficient [3, 4]. The integration of diamond onto GaN HEMTs poses significant challenges, regardless of whether a diamond-first or device-first approach is employed.<br/>In the diamond-first approach, the primary challenge lies in diamond surface roughness, which imposes a limitation on gate length &lt;2 µm through lithography, non-uniformity in the diamond etching, and contacts/pads damage after diamond etching. To address this issue, we have implemented a polishing technique through ion-milling, achieving a surface smoothness of less than 10 nm RMS roughness before carrying out E-beam lithography, and developed a more selective etching process using O₂/SF₆ mixture in RIE. Additionally, a slanted etching technique was developed for rough diamond surfaces that starts with a 2 µm opening at the top and achieves a gate footprint of less than 100 nm, suitable for X- to W-band applications.<br/>In the device-first approach, two key challenges arise: gate dielectric leakage (2-10 mA/mm) and ohmic loss (R_c=1.4 Ω.mm, R_sh=250 Ω/■). To overcome gate leakage, we have modified the gate metal stack from Au/Ni to Mo and employed a low-temperature (LT) diamond growth technique at 350-400°C [5], effectively reducing the leakage to &lt;1 µA/mm. As for ohmic loss, we have successfully tackled it by incorporating a thicker N+ regrown region and using a 400°C diamond growth temperature (R_c=0.24 Ω.mm, R_sh=225 Ω/■). These combined measures have proven to be effective solutions in mitigating gate dielectric leakage and reducing the ohmic loss for higher current capabilities ~ 1 A/mm.<br/>We have successfully integrated LT diamond on GaN HEMTs using the above-mentioned approaches. By implementing the all-around diamond scheme and connecting the top diamond to the heat sink through diamond vias, the channel thermal resistance (<i>R_th</i>) was reduced by 34% from 6.9 to 4.6 K.mm/W, realizing a higher heat transfer coefficient from the channel. This integration resulted in no dispersion (pulsed I-V at 400 ns gate pulse) and lower channel temperature (<i>T_ch</i>) compared to the case without diamond. With low <i>TBR</i> (3-5 m²K/GW) and high thermal conductivity (<i>TC</i>:300-1000 W/m/K depending on the grain size and thickness), the average and peak <i>T_ch</i> dropped by 35% (200 to 130°C at 25 W/mm, measured by I-V thermometry) and over 50% (120°C at 20 W/mm, measured by thermoreflectance imaging), respectively [6]. Our technique not only addresses thermal management challenges for GaN-based power amplifiers but is also compatible with other technologies such as InP, Ga₂O₃, SiC, and Si. Proper thermal management can enhance the device’s reliability and lifetime while providing a higher power at higher frequencies.<br/><br/>[1] A. Nigam et al., AIP Advances, 7 (8), 085015, 2017.<br/>[2] D. Shoemaker et al., IEEE Trans. Compon. Packaging Manuf. Technol., 11 (8), 1177-1186, 2021.<br/>[3] M. Malakoutian et al., Cryst. Growth Des., 21 (5), 2624–2632, 2021.<br/>[4] M. Malakoutian et al., ACS Appl. Mater. Interfaces, 13 (50), 60553–60560, 2021.<br/>[5] M. Malakoutian et al., Adv. Funct. Mater., 32, 2208997, 2022.<br/>[6] R. Soman et al., IEDM, San Francisco, CA, USA, 30.8.1-30.8.4, 2022.