Symposium EP10—Heterovalent Integration of Semiconductors and Applications to Optical Devices

Abstract: Semiconductor electronic and optoelectronic materials and devices have experienced very rapid development for more than half a century. The recent progress in development of quantum materials and their applications in quantum computing, communication, and sensing also calls for in-depth understanding of interfaces between dissimilar semiconductors, semi-metals, and superconductor, and broad exploration of new heterovalent integration of these materials from different families. Thin layer quantum structures and their interfaces consisting of materials families such as group II-VI (MgZnCdHg)(SeTe), III-V (AlGaIn)(PAsSb), IV-IV (SiGeSnPb), and IV-VI Pb(Se,Te) grown on GaAs, InP, GaSb, InAs and InSb substrates offer a very broad spectrum of interface configurations, alloy combinations and their quantum properties for both fundamental physics study and device applications. This talk will focus on the latest progress in the MBE growth of these heterovalent structures and their potential applications in quantum materials research, solar cells, midwave IR light emitting devices, and photodetectors.

Optically-pumped semiconductor disk lasers (SDLs), also commonly known as vertical external cavity surface-emitting lasers (VECSELs), are of particular interest for applications that require high spatial and/or spectral brightness at novel wavelengths. A typical SDL gain structure consists of a multi-quantum-well resonant periodic gain region on a monolithic distributed Bragg reflector (DBR). This gain mirror is then optically-pumped and aligned within a conventional air-spaced laser resonator. With their relatively high output power (multi-Watt) and high finesse cavities, SDLs are ideally suited for narrow linewidth operation, demonstrating low frequency and intensity noise; properties we are currently exploiting to develop visible SDLs with sub-kHz linewidth for application in quantum technology, specifically atomic clocks. SDLs have been demonstrated from the deep ultraviolet to the mid-infrared via a combination of III-V semiconductor bandgap engineering and intracavity nonlinear frequency conversion; however, direct emission at wavelengths around the so-called ‘green-gap’ would offer many advantages in size, efficiency, and tunability as well as removing a nonlinear conversion step towards the UV. With the advent of high power GaN pump lasers, un-doped II-VI materials show promise for optically-pumped gain structures in this spectral region, and there is already a large body of work on II-VI-based vertical structures on GaAs, including high quality DBRs. Our interest is in ZnMgCdSe on InP substrates, which offers optical gain from the blue to the red. Optically-pumped edge-emitting lasers in the blue, green, and red were previously demonstrated by the Tamargo group. DBRs are in development with the possibility of using the superlattice technique that has proved successful for material lattice-matched to GaAs; however, SDLs need not have a monolithic DBR if the quantum well gain region can be transferred to a transparent substrate. Here we present an overview of our recent work in visible narrow linewidth SDLs, and our progress on the design, growth, processing and characterization of ZnCdMgSe multi-quantum well vertical gain structures, including transfer of gain regions to single crystal diamond windows.

The selective combination of closely lattice-matched group II-VI/group III-V semiconductors offers potential benefits due to the wide range of band-gap energies achievable and novel effects at the interface arising from the valence-mismatch. Very little has been done so far to exploit these opportunities, in part due to challenges in determining the structure and properties of the interface, for instance using scanning transmission electron microscopy (STEM) techniques.

The combination of CdTe (II-VI) and InSb (III-V) implies the existence of a heterovalent non-common-atom (NCA) interface which must contain mixtures of II-V and/or III-VI bonds. Because of the close atomic numbers of the constituent elements, high-angle annular dark-field (HAADF) and large-angle bright-field (LABF) STEM, as well as electron energy-loss spectroscopy measurements from the interface region are inherently difficult to interpret. In contrast, we show here that the use of the 002 dark-field (DF) imaging technique emphasizes the interface location by comparing differences in structure factors between the two materials. Additionally, detailed analysis of the diffracted 002 DF TEM intensity allows quantification of the interface width to be made, which further allows the possibility to address questions such as exploring the presence of (unintentional) interfacial layers or mechanisms governing the interface formation in these complex valence-mismatched interfaces. The approach adopted here for the interface analysis relies on the comparison of experimental and simulated contrast profiles at the CdTe-on-InSb interface, where different functional dependences (e.g. sigmoidal function, error function) for the atomic species are assumed. Since the contributions of the III- (II-) and V- (VI-) elements need to be separately considered, the cation and anion intermixing are independently determined. Furthermore, information at the monolayer level can be unambiguously obtained. Finally, our study reveals that the CdTe-on-InSb interface is structurally abrupt to within about 1.5 nm (10-to-90%-criterion).

The method is of general applicability, and it will be applied in the future to other NCA heterovalent interfaces. Hence, it opens a new route for investigation of the long aimed correlation between the interface-related electronic properties and transport phenomena and the interface characteristics.

Silicon CMOS has become a gold standard as the signal processor for various optoelectronic devices. Therefore, it is highly desirable to have the devices built on the sensing materials epitaxially grown on Si base composite substrates to ensure reliable low temperature operation due to thermal match between the device structure and Si CMOS. In addition, super scalability of readily available Si substrate enables fabrication of large area and low cost optoelectronic devices. However, due to the very large lattice mismatch between semiconductors at 6.1Å and 6.4Å and the Si substrate (about12% and 19% respectively), a buffer layer has to be used to bridge the gap and to accommodate the misfit dislocations generated at the interface, as show in figure 1. Considering the advantageous properties of II-VI material in accommodating misfit dislocation, we choose ZnTe and CdTe as buffer materials to fabricate ZnTe/Si and CdTe/Si composite substrates for optoelectronic materials at 6.1 Å, such as GaSb or InAs base type-2 superlattice and HgCdSe IR material, and at 6.4 Å, such as HgCdTe IR material, respectively. Furthermore, a small percentage of Se added into either the ZnTe or CdTe matrix will create a composite substrate lattice matching to the targeted optoelectronic materials, which will minimize the dislocations generated in device material. In this paper we will present our systematic studies on the molecular beam epitaxial (MBE) growth of Cd(Se)Te/Si and Zn(Se)Te/Si with emphases on the techniques to reduce dislocations generated in the buffer layer as well as on control of Se concentration to achieve lattice matching with over-grown device layer. The quality of the buffer layers were evaluated by x-ray diffraction, transmission electron microscopy and etched pit density. Our results indicate a buffer layer of CdTe or ZnTe with dislocation as low as 10⁵cm^-2 can be grown on Si substrate. Photodiodes fabricated from Hg_0.78Cd_0.22Te grown on a lattice-matching CdSeTe/Si composite substrate exhibit excellent I-V characteristics [1]. The results validate the Cd(Se)Te/Si as a low-cost, scalable and high quality composite substrate for optoelectronic device at 6.4 Å.

We report the growth of in-situ silicon doped InAs layers over In_0.53Ga_0.47As/InP/Si by atomic layer epitaxy (ALE). The use of ALE enables us to obtain uniform smooth layers with Si doping concentration in excess of 5E19 cm^-3 at growth temperatures of 400^oC. This high doping level is typically hard to achieve with metal organic chemical vapor deposition (MOCVD) at similar growth temperatures. Furthermore, the growth was selective to silicon dioxide, with deposition taking place only over semiconductor surfaces. We have used tertiarybutylarsine (TBA) as a source for As, trimethylindium (TMIn) as a source for In, and silane (SiH₄) as a source for Si.
ALE is also a unique tool for investigating amphoteric doping with silicon (a group IV element) in III-V materials. We designed two ALE cycles for growing Si doped InAs. The first cycle comprised of the following pulses:
(1) TBA, (2) purge with H₂, (3) TMIn + SiH₄, (4) purge with H₂.
The second cycle comprised of:
(1) TBA + SiH₄, (2) purge with H₂, (3) TMIn (4) purge with H₂.
In the first ALE cycle, Si doping was introduced with the group-III element, while in the second ALE cycle, Si doping was introduced with the group-V element. Secondary-ion mass spectrometry (SIMS) showed that incorporation of Si was 20x larger when Si was introduced with group-III. Furthermore, while the growth rate as a function of the TMIn pulse length saturates, longer SiH₄ pulses did result in higher doping for pulse durations we studied.

Ge on insulator (GOI) technology has been widely studied for lowering the fabrication cost and improving the device performance of Ge metal-oxide-semiconductor field-effect-transistors. Solid phase crystallization (SPC) is a simple method to directly form polycrystalline Ge (poly-Ge) thin films on glass substrates at low temperatures [1]. Recently, we found that the control of the atomic density of an amorphous Ge precursor for SPC dramatically enlarged the grain size and updated the maximum value of hole mobility of semiconductor thin film on insulators [2-4]. The electrical properties of these Ge layers greatly depended on the film thickness, suggesting that the underlying interface influences the electrical properties [3]. Generally, it is known that the grain size of the Ge layer changes depending on the type of the underlayer [5,6]. In this study, we investigated the effects of the underlayer insertion on the SPC-Ge and broke the record with a hole mobility of 560 cm²/Vs by employing a GeO₂ underlayer. Furthermore, we achieved a hole mobility of 500 cm²/Vs even on a plastic substrate.

To investigate the effects of the underlayer material, we prepared a 50-nm-thick insulating layer (SiN, Al₂O₃, GeO₂) on a SiO₂ glass substrate using RF magnetron sputtering. After that, amorphous Ge (a-Ge) precursors were prepared using a Knudsen cell of a molecular beam deposition system (base pressure: 5 × 10⁻⁷ Pa) while heating the samples at 150 °C. The thickness of the a-Ge layer was ranged from 100 to 600 nm. The samples were then loaded into a conventional tube furnace in a N₂ atmosphere and annealed at 450 °C for 5 h to induce SPC. After that, we performed post annealing (PA) at 500 °C for 5 h to enhance the electrical properties. For comparison, samples without forming an insulating layer were also prepared. In addition, a sample with a GeO₂ coated plastic (polyimide) substrate was prepared, which was annealed at 375 °C for 150 h. After annealing for SPC, the grown Ge layers were evaluated by using electron backscattering diffraction (EBSD) analysis. The electrical properties of the SPC-Ge layers were evaluated using Hall effect measurements.

The EBSD images showed that the crystal grain size of the Ge layer on glass varied depending on the type of the underlayer. This suggests that the frequency of Ge nucleation was changed because of the change of the underlayer material. The Hall effect measurements showed that the larger grain size provided the lower hole density and the higher hole mobility. From the above results, it was found that the GeO₂ underlayer provides the largest grains and the highest hole mobility among the underlayer materials. The 400-nm-thick Ge on a GeO₂ coated glass substrate, annealed at 450 °C, exhibited a hole mobility of 440 cm²/Vs. Furthermore, the hole mobility was improved to 560 cm²/Vs by the PA at 500 °C due to the defect compensation effect.
Based on the above results, we prepared a 400-nm-thick Ge layer on a GeO₂ coated plastic (polyimide) substrate, and induced SPC at 375 °C. The resulting Ge layer exhibited a grain size of 9.1 μm and a hole mobility of 500 cm²/Vs. This hole mobility is the highest record among that of semiconductor thin films directly synthesized on a plastic substrate. This achievement will give a way to realize advanced electronic and optical devices simultaneously allowing for high performance, inexpensiveness, and flexibility.

[1] K. Toko et al., Solid-State Electron., 53, 1159 (2009).
[2] K. Toko et al., Sci. Rep. 7, 16981 (2017).
[3] R. Yoshimine et al., Appl. Phys. Express 11, 031302 (2018).
[4] K. Moto et al., Sci. Rep. 8, 14832 (2018).
[5] K. Toko et al., APL. 99, 032103 (2011).
[6] K. Toko et al., CrystEngComm 16, 2578 (2014).

Solar cells based on heterojunction with intrinsic thin layer (HIT) technology use heterojunctions to optimize the collection of photogenerated carriers. The silicon heterojunction (SHJ) solar cell design uses a combination of doped amorphous silicon [a-Si:H(p/n)] and intrinsic amorphous silicon [a-Si:H(i)] to form a contact that is selective to either electrons or holes. This design leads to a heterointerface which is formed between amorphous silicon (a-Si:H) and crystalline silicon (c-Si) which is critical to overall device performance; and consequently, it is imperative to understand the underlying physics that governs transport.

There is still debate about the impact of the a-Si:H(i) layer and the defects in this layer on transport and on overall device performance. There have been experimental studies that have attempted to study the modes of hole transport through the a-Si:H(i) layer for a a-Si:H(p) emitter SHJ solar cell. Taguchi et al. did temperature dependent IV measurements and inferred that a multi-phonon process must be dominant[1]; Crandall et al. performed transient capacitive experiments and concluded that 'hopping' transport is the dominant mode transport [2]. However, many simulation studies which use commercial simulation tools are unable to rigorously study transport while studying cell level properties [3,4]. In this paper we explicitly simulate the transport of holes across the a-Si:H(i)/c-Si heterointerface and correlate it to overall device performance. We use a traditional drift-diffusion model to calculate the electric fields and potentials within the device for device operating conditions. Previously, we have also developed an ensemble Monte Carlo solver that calculates the energy of photogenerated carriers at the heterointerface [5]. We then use a kinetic Monte Carlo (KMC) to explicitly study hole transport through the a-Si:H(i) layer for particular device operating conditions. This method allows us to explicitly study transport mechanisms such as multi-phonon injection/extraction, defect assisted 'hopping' transport, Pool-Frenkel emission, thermionic emission etc.

In this work we used the KMC to simulate hole transport across the a-Si:H(i) layer. This was done for various device conditions. Our simulations indicate that increasing a-Si:H(i) layer thickness (4 nm → 18 nm) at 300 K at short circuit condition leads to an increase in average collection time for holes (10^-3 → 10² sec). However, the average collection time saturates at higher a-Si:H(i) layer thicknesses (>12 nm). Simulations were also conducted for varying temperature, interface defect density, optical phonon energy, and at open-circuit condition and maximum power point conditions for solar cells. We also replicated an experimental study (given in ref 2) by simulating time dependent carrier decay across the a-Si:H(i) barrier and obtained very similar trends. Our simulations in conjunction with the experimental studies strongly indicate that the hole are collected via 'hopping'. We are currently trying to quantitatively correlate our transport simulations to device performance parameters such efficiency, fill factor and open-circuit voltage.

[1] M. Taguchi, E. Maruyama, and M. Tanaka, Jpn. J. Appl. Phys., vol. 47, no. 2 PART 1, pp. 814–818, 2008.
[2] R. S. Crandall, E. Iwaniczko, J. V. Li, and M. R. Page, J. Appl. Phys., vol. 112, no. 9, 2012.
[3] R. Lachaume, W. Favre, P. Scheiblin, and X. Garros, Energy Procedia, vol. 38, pp. 770–776, 2013.
[4] R. Varache, J. P. Kleider, M. E. Gueunier-Farret, and L. Korte, Mater. Sci. Eng. B Solid-State Mater. Adv. Technol., vol. 178, no. 9, pp. 593–598, 2013.
[5] P. Muralidharan, K. Ghosh, D. Vasileska, and S. M. Goodnick, in Photovoltaic Specialist Conference (PVSC), 2014 IEEE 40th, 2014.

Semiconductor nanowires are used in optoelectronic devices, such as light-emitting diodes, lasers, solar cells, and photodetectors [1]. Formation of multiple twin boundaries during the growth of nanowires is very common. However, the effects of these planar defects on the electronic and optical properties of nanowires are not very well understood. It is unclear whether twin boundaries act as recombination centers and if they introduce any barriers/traps for charge transport.

Here, we combine ab initio electronic structure calculations with experimental techniques to study these effects [2]. Twin boundaries in GaP are shown to act as an atomically-narrow plane of wurtzite phase with a type-I band alignment homostructure. Presence of twin boundaries leads to the introduction of shallow trap states. Trapped optical excitations have a weak but finite dipole matrix element. It results in optical transitions that are otherwise suppressed in the indirect band gap GaP. Sub-band gap peaks observed in photoluminescence studies of GaP nanowires are attributed to twin boundaries and extended regions of wurtzite GaP.Implications of the presence of twin boundaries on the performance of nanowire-based devices will be discussed.

[1] R. Yan, D. Gargas, and P. Yang, Nat. Photonics 3, 569 (2009).
[2] D. Gupta, N. I. Goktas, A. Rao, R. Lapierre, and O. Rubel, ArXiv:1810.01194 [Cond-Mat.Mtrl-Sci] (2018).

The importance of studies of various types of III-V-based inorganic materials is increasing rapidly due to their attractive properties, such as their thermal, chemical and moisture stability, direct bandgaps, and the high electrical properties of these materials and related devices. Moreover, research on micro- or nano-patterned devices with III-V-based materials has been very active owing to the suitability of these materials in commercialized optoelectronic devices given their enhanced lifetimes, high brightness levels, and the high efficiency of novel optoelectronic devices. Here, an AlGaInP/GaAs one-dimensional (1D) microrod was fabricated for use in one-directional micro/nano devices by a top-down approach. These 1D microrod structures, which were fabricated by transferring a 1D patterned microsphere as a mask and using plasma dry etching, in this case reactive ion etching (RIE) and inductive coupled plasma (ICP), can be used as a horizontally aligned single microwire device. To fabricate the 1D AlGaInP/GaAs microrod, SiO₂ thin films deposited by plasma-enhanced chemical vapor deposition (PE-CVD) were fabricated as microrod arrays to be used as a mask for etching the AlGaInP/GaAs microrod arrays. In this study, relative etching rates and etching selectivity of the AlGaInP/GaAs layer were studied to fabricate vertical aligned III-V microrods. The morphological properties of the AlGaInP/GaAs microrod were studied by scanning electron microscopy (SEM) and transmission electron microscopy (TEM). A defect analysis was conducted of the dry etching process and the enhanced optical properties of the 1D microrod were analyzed in terms of the photoluminescence (PL) and cathodoluminescence (CL).

Tin dioxide (SnO₂) belonged to a class of transparent conducting oxide materials and had high transparency in the visible spectrum as well as high electrical conductivity [1]. Pure SnO₂ was a n-type semiconductor with a bandgap of 3.6 eV [2]. Structure defects and the presence of impurities had great influence on electronic and optical properties of semiconductors [3]. Doping with heterovalent elements (Sb, F) allowed for modification of the electronic structure: the position of the conduction band minimum and valence band maximum may be shifted, thus altering the bandgap value [4].
Systematic study of heterovalent systems of semiconductors established correlations between composition, structure, and electronic properties, allowing for directed synthesis of new materials with desired properties. First principle simulations provided structure and properties predictions for new compounds. Such simulations were based on the density functional theory (DFT) and could be performed within either the local density approximation (LDA) or by use of the generalized gradient approximation (GGA). Both approaches demonstrated severe underestimation of the bandgap especially in the case of systems with strong d-electron interactions (TiO₂, NiO, ZnO, SnO₂). Bandgaps obtained with the use of hybrid functionals were close to experimental values, although such simulations were much more computationally expensive and were often incomplete.
Our study involved the influence on crystal structure and electronic properties as a result of heterovalent substitutions (up to 10% mol) of Sn and O by Sb, Ta, and F. Using different functionals implemented in VASP code [5], we performed relaxation to find optimized cell parameters for pure SnO₂ and its solid solutions with Sb, Ta and F. While GGA and LDA predict the bandgap of SnO₂ with 80% and 60% error respectively, hybrid functional based on Heyd, Scuseria, and Ernzerhof (HSE) [6] showed an accurate bandgap value of 3.62 eV in comparison with the experimental value. It was shown that heterovalent substitution of Sn by Sb led to a linear decrease of the bandgap from 3.62 to 3.01 eV for the range of 0 to 11% mol. When Oxygen was substituted by Florine the bandgap decreased to 3.06 eV for 10.2% mol of F. The influence of dopant concentration on the bandgap was linear for all functionals used, indicating this was a possible key to manipulating the bandgap in aliovalently substituted Tin Dioxide.

[1] Lewis, Paine, MRS Bulletin 25, 22 (2000)
[2] Batzill, Diebold, Prog. Surf. Sci. 79, 47 (2005)
[3] Van de Walle, J. Appl. Phys. 95, 3851 (2004)
[4] Shanthi, Subramanian, Ramasamy, Cryst. Res. Technol. 34, 1037 (1999)
[5] Kresse, Furthmüller, Phys. Rev. B 54, 11169 (1996)
[6] Krukau, Vydrov, Izmaylov, Scuseria, J. Chem. Phys. 125, 224106 (2006)

In this study, we characterized remote-type single-package (single-PKG) white-light-emitting diodes (WLEDs) using the narrowband CaMgAl₁₀O₁₇:Eu,Mn (CAM:Eu,Mn) green phosphor and the line-emitting K₂SiF₆:Mn⁴⁺ (KSF:Mn) red phosphor in order to enhance the color gamut and luminous efficacy of WLEDs at a correlated color temperature (CCT) of 10000K.
We synthesized, optimized and mixed green-emitting CAM:Eu,Mn phosphors and red-emitting KSF:Mn phosphors. The mixed green and red phosphors were successfully applied to conventional blue LEDs (432 nm) to fabricate a remote-type single-PKG white LED. The luminous efficacies of white and the associated red, green and blue LEDs were measured and found to have reasonable values of ~70, 15, 35, and 5 lm/W, respectively, at 20 mA. This resultant color gamut (~111 %) of a filtered white LED is superior to that of the highest ever color gamut of reported phosphors, such as the sharp γ-AlON:Mn,Mg green and KSF:Mn red phosphor (~102.4 %) as well as the commercialized InP/ZnS QD-based QDEF for LCDs (~100 %). The widest color gamut of a backlight consisting of an InGaN blue LED, the CAM:Mn green phosphor, and the KSF:Mn red phosphor can meet the color requirements for backlighting in LCD displays.

The market for non-volatile memory is potentially about to hit a brick wall with the flash technology as it might not be scalable beyond the 14nm node. The need for other storage devices is a hot topic in said market, and one possibility is Resistive RAM (ReRAM) devices. These devices can store information through a reversible switch from high to low resistance. Two mechanisms bipolar and unipolar are used to explore the reset process. Bipolar switching uses reverse bias to cause recombination of the oxygen atoms. In this project the applicability of Ni_0.8Fe_0.2O_1-d in ReRAM devices is being investigated.
Device test wafers with different oxygen concentration and thicknesses were made by reactive RF magnetron sputtering on n and p type Si substrates ((100) test grade 0-100 Ohm.cm). The native oxide was removed using HF 2 minutes before loading the samples in the vacuum chamber. The oxide was deposited by reactive RF co-sputtering using two guns on opposite sides of the sampleholder. To further improve the homogeneity of the oxide layer, the substrate holder was rotated during deposition. Samples were deposited at two different oxygen flow rates. The deposition rate was dependent on the flow and varied from 0.15 (40% O2) to 1.1 (10% O2) A/sec. The Au electrodes were deposited through a stainless steel shadow mask which contained 1312 devices ranging in diameters from 800 micrometers to 50 micrometers with a thickness of 100nm. A quartz coupon was used to shield areas of the Si-wafers from the Ni₈₀Fe₂₀O layer during the previous deposition step, both Si-Au and Si-NiFeO-Au devices were available for characterization on each wafer. After finishing the total device stack the SiO2 on the back of the wafers was removed by HF and covered with a 100 nm Aluminum layer using thermal evaporation.
A linear four point probe was used to determine the resistivity of the Permalloy Oxide (PyO) thin films on the quartz coupon. Low Oxygen concentration samples yielded a resistivity of 4E5 Ohm cm. High Oxygen concentration samples yielded a resistivity of 5E3 Ohm cm. A Summit 12000 probe station of FormFactor and a Keysight B1500A Semiconductor Analyzer were used to characterize the device wafers. Current-voltage relationships were measured at room temperature. This probe system is completely automated which allows for instant access to each of the 1312 devices on the wafer. Heterojunction on n-type silicon showed strong rectification with Ifor/Irev>50 for low O2 flow devices and Ifor/Irev>10,000 for high O2 flow devices. The heterojunction on p-Si showed negligible rectification. As for the devices on p-Si two states were identified, an initial high resistance state and a non-linear IV curve with much larger currents after burn in. The electric characteristics scales with the device area for n-type substrates but not for p-type substrates. Our preliminary results suggest the p-type nature of Permalloy Oxide sputtered at high oxygen flow. The strong rectification of the heterojunctions on n-Si indicates that NiFe-oxide sputtered at high oxygen flow could be useful as a hole-blockers in photodetectors [1] or a selector for cross-bar ReRam chips [2].
We acknowledge financial support from Texas State University and DOD (HBCU/MI grant W911NF-15-1-0394) and a DOD HBCU/MI equipment/instrumentation grant (W911NF-16-R-0024)
[1] A. H. Berg, G. S. Sahasrabudhe, R. A. Kerner, B. P. Rand, J. Schwartz, and J. C. Sturm, in Proc. 74th Annu. Device Res. Conf. (DRC), Jun. 2016, pp. 1–2, doi: 10.1109/DRC.2016.7548444.
[2] Hiroyuki Akinaga, Hisashi Shima, Proc. Of the IEEE 98 (2010) 2237-2251.

Native oxides used as protective passivation layers on semiconductors, inhibit high quality epitaxial growth, increase contact resistance, and decrease reliability of measurements. For opto-electronics, a better understanding of native oxides and their removal is needed for heterovalent integration of semiconductors. In this work, the surface energies, the oxygen areal coverage, and the oxidation states of Te-doped n+ GaAs(100) and B-doped p- Si(100) surfaces are investigated before and after wet chemical etching in order to bond Ga and Si via NanoBonding^TM[1]. Heterovalent integration via NanoBonding^TM consists of direct bonding between two surfaces using surface engineering where both surfaces’ hydro-affinity are reversed from hydrophobic to hydrophilic, and vice-versa. Surface Processing modifies electron donor/acceptor interactions, increasing electron exchange via precursor phases. This catalyzes cross-bonding between both etched surfaces.

The van Oss-Chaudhury-Good (vOCG) theory computes the surface energy, γ^T, of semiconductors from its three components via Three Liquid Contact Angle Analysis (3LCAA), combining molecular interactions or “Lifshitz-Van der Waals” energy, γ^LW, with energy of interaction of electron donors, γ⁺, and acceptors, γ^-. The image analysis algorithm “Drop and Reflection Operative Program^TM” (DROP^TM) enables fast and accurate extraction of contact angles without subjectivity, reducing the typical ~5° error in manually extracted contact angles to < 1° . With multi-angle data, DROP^TM yields γ^T within 3%. 3LCAA determines the effects of etching on hydro-affinity and oxidation states and is correlated with compositional changes.

Before etching, GaAs(100) is initially hydrophobic with γ^T of 33 ± 1 mJ/m², whether for doped or semi-insulating GaAs. After etching [1], γ^T increases by a factor of two or 100% to 66 ± 1 mJ/m², making etched GaAs highly hydrophilic. Hydro-affinity and reactivity are modified by increasing electron donor/acceptor interactions by a factor of three to ten while γ^LW increases by at most 50%.
High Resolution Ion Beam Analysis (HR-IBA) combines <111> channeling with 3.039 ± 0.01 MeV (16O, 16O) nuclear resonance. Ga, As, and O coverage are measured to within ± 0.2 monolayer (ML) before and after etching by matching SIMNRA simulations to HR-IBA spectra . IBA shows that after the etch, oxygen coverage on GaAs decreases 50 ± 4% from 7.2 ± 0.2 ML to 3.6 ± 0.2 ML. The 53:47 stoichiometric ratio of Ga to As remains constant after etching within ± 1%. The areal surface density shows that decreasing oxygen coverage by a factor two is commensurate with decreasing displacement of Ga and As surface atoms, implicating etching doesn’t corrode GaAs or alter stoichiometry.

X-Ray Photoelectron Spectroscopy (XPS) measured oxidation states and uniformity of the surface for C, O, Ga, and As on two locations of two wafers for both native oxide and etched GaAs(100). GaAs native oxides include binary oxides (Ga₂O₃, As₂O₃, As₃O₅), ternary oxides (GaAsO₄), and metallic arsenic. The proportion of oxidized Ga increased from 40 ± 1% to 47 ± 1% while the proportion of oxidized As decreased from 21 ± 1% to 19 ± 1%. This change in As oxidation reverses the hydro-affinity of GaAs(100) as the decrease in fully oxidized As increases the amount of unfilled bonds of As, increasing γ^T.

In summary, 3LCAA measured a change in GaAs hydro-affinity before and after etching by a factor of two from strongly hydrophobic (γ^T = 33 ± 1 mJ/m²) to strongly hydrophilic (γ^T = 66 ± 1 mJ/m²). HR-IBA accurately determined to within 0.2 ML decreased oxygen coverage and stoichiometry as a function of wet chemical etching. XPS was then correlated with IBA to establish modifications in the proportion of oxidized Ga and As atoms and in their oxidation states. Modification of oxidation states help explain the dramatic change observed in hydro-affinity.

[1] US Patents #9,018,077; #9,589,801, Herbots N. et al (2015); (2017)

The reduced graphene oxide (rGO) has drawn much attention as gas sensing material in the field of gas detection. However, there are still some challenges for its application because of the poor stability and selectivity. Therefore, it is particularly significant for the functionalization of rGO. As a new ternary semiconductor, CuSbS₂ quantum dots (QDs) have many special advantages, such as large specific surface area, tunable band-gap, high carrier mobility, which enables to be applied to enhance the gas sensing properties of rGO.
In the present work, rGO sheets are prepared by Hummers method and CuSbS₂ QDs/rGO composites are synthesized by hot injection method, and then CuSbS₂ QDs/rGO composites are self-assembled by a solution method. It is found that there are some wrinkles on the rGO sheets and the average size of CuSbS₂ QDs in the composites is 4.9 nm with the even and dense dispersion on rGO sheets. The gas sensing properties of CuSbS₂ QDs/rGO composites are tested by a static measurement system, and the detection limit of the composites to NH₃ is 500 ppb at room temperature with the response value to 50 ppm NH₃ of 1.45, which proves that the gas sensing properties are enhanced substantially compared with pure CuSbS₂ quantum dots and rGO. The good gas selectivity of the composites is verified as well. The excellent gas sensing properties of the composites are mainly due to the obvious synergistic effect between rGO and CuSbS₂ quantum dots indicated by UPS, UV-vis and other measurements. Besides, the gas reaction process on the surface of the composites is specifically discussed by DRIFT test.
In conclusion, the utilization of CuSbS₂ quantum dots can significantly improve the gas sensing properties of rGO, and the low detection limit at room temperature indicates that CuSbS₂ QDs/rGO composites can be expected to be a good candidate of the gas sensing material in NH₃ detection.

In this presentation I will discuss three examples of heterovalent integration of semiconductors and magnetic films as a means of controlling their magnetic properties. Let us begin with the alloy GaMnAs, a well known ferromagnetic semiconductor grown by low-temperature molecular beam epitaxy (MBE). The Curie temperature of this material naturally depends on the concentration of the Mn magnetic ions in the crystal lattice. It is well known that the divalent Mn ions incorporated into the GaAs lattice act as acceptors, and that the Fermi level of the holes created by this process puts a limit on how much Mn can be incorporated into the crystal, thus naturally putting a limit on the Curie temperature that can be achieved. [1] We have shown that the hole concentration can, however, be controlled by integrating GaMnAs with Ge (which are very closely lattice-matched), either by epitaxially growing GaMnAs on Ge, or Ge on GaMnAs. [2] This possibility is enabled due to the specific valence band offset that exists between these two materials.
As a second example, I will discuss the effect of integrating Fe with either Ge, GaAs or ZnSe. Epitaxial films of bcc alpha-Fe are nearly perfectly lattice matched with these three fcc semiconductors, enabling epitaxial growth of very high quality single-crystal Fe films on these materials. I will show that the magneto-crystalline anisotropy of the resulting alpha-Fe films (a property of major importance in spintronic devices) is strongly related to the semiconductor on which the Fe film is grown. Specifically, it has been demonstrated by using ferromagnetic resonance (FMR) and magnetotransport that magneto-crystalline anisotropy of alpha-Fe films integrated with Ge is perfectly cubic; that it is weakly uniaxial in Fe integrated with ZnSe; and that magnetic anisotropy of Fe grown on GaAs is quite strongly uniaxial. [3,4] I will discuss the physical reasons for each of these cases. The effects on magnetic anisotropy of Fe arising from integration with Ge, GaAs or ZnSe become important because of current interest in forming magnetic tunnel diodes and related structures involving GaMnAs and Fe, where GaAs, ZnSe or Ge can be used as non-magnetic barriers between the two magnetic layers. [5]
Finally, I will discuss the interesting case when the ferromagnetic semiconductor GaMnAs is integrated with the topological insulator Bi2Se3. Unlike the preceding two examples, in this case the lattice match is not critical because of the van der Waals forces involved in epitaxial growth of Bi2Se3. It has been shown that such integration has two rather profound effects on the ferromagnetic magnetic properties of GaMnAs. First, the proximity of Bi2Se3 results in a significant increase of the Curie temperature of GaMnAs. And second, equally as important, this proximity profoundly changes the magnetic anisotropy of GaMnAs, and results in a significantly higher magnetic coercivity of GaMnAs. [6] The physical mechanism behind this effect is at present not fully understood, and efforts are continuing to resolve this interesting puzzle.

[1] K. M. Yu, et al., Physical Review B 68, 041307 (2003).
[2] J. C. Leiner, Ph.D. Dissertation, University of Notre Dame, 2012 (unpublished).
[3] K. Tivakornsasithorn, Journal of Applied Physics 116, 043915 (2014).
[4] H. Jeong, et al., Solid State Communications 200, 1 (2014).
[5] S. Lee, et al., Scientific Reports 7, 10162 (2017).
[6] S.-K. Bac, et al., Journal of Electronic Materials 4, 4308 (2018).

Si-based tandem solar cells have become a topic of great interest over the past several years due to the fact that Si single-junction cells are approaching their practical efficiency limits. The highest Si-based tandem efficiency of 32.8% was achieved by bonding a III-V solar cell to Si. Perovskite/Si tandems are next highest in the efficiency race, attaining 27.3% efficiency at the time of writing. The efficiency of epitaxial III-V/Si tandems has also risen rapidly, though remains behind the approaches listed above. In this work I will describe our recent work to separately demonstrate 16.5% efficient GaAsP top cells and 7.8% efficient GaAsP-filtered Si bottom cells (both certified by NREL). High short-circuit current density was attained in the Si bottom cell due to strong light-trapping, and our best Si bottom cells produce significantly more current than our best GaAsP top cells. We calculate that when combined, our current-mismatched 1J cells could reach a two-terminal tandem efficiency of 23.9%, and progress towards this goal will be reported.

Recently, Transparent Conducting Oxides (TCOs) were one of the central issue in modern life due to their applications such as flat-panel displays, solar cells, and touch screen displays. For TCOs applied as transparent electrodes, the thin films should own lower resistivity, lager transmittance in visible light range, and enduring stability. Zinc Oxide (ZnO) doped with group-III impurities such as Al and Ga had shown satisfactory optical and electrical properties as a relatively inexpensive alternative TCO material. The common deposition technics of GZO thin films including Sputtering technics, Pulsed Laser Deposition, and so on. These process needed to change Ga to Zn ratio target for different Ga doping concentration and relatively high temperature to grow well quality GZO films. In contrast, Atomic Layer Deposition (ALD) system could operate GZO films easily in different Ga doping concentration at low temperature with great uniformity. Traditionally, ZnO films doped with group-III impurities utilized multi-layer deposition method which deposited several ZnO layer plus one impurity Oxide layer to control impurity doping concentration, the process would cause the restriction of thickness and electricity due to the multi-layer depositing and high resisted impurity oxide layer.
Here, we developed a method of in-situ doping with flow rate-interruption to grow GZO thin film by ALD system. The difference between traditional multi-layer growth and in situ doping growth is that Ga, Zn, and O are all in the same layer on the process. The advantages of this method are optimized reaction time, controllable doping concentration, low precursor consumption, high step coverage, stable crystal structure growth, and controllable film thickness. A (002) highly prefer orientation crystal GZO thin film was successfully grown on 1 um of amorphous Silicon Dioxide (SiO₂) film, which normally promotes random crystal structure growth. In this study, the in-situ doping with flow rate-interruption method demonstrated better crystalline and enhanced-control doping concentration in GZO thin films.
The in-situ doping flow rate-interruption GZO thin films were grown with different TEGa pulsed time at 300 degree Celsius by the ALD system. To understand the composition and structural properties of GZO thin films, EDS spectrum and Gonio scan were measured. The EDS results showed the different Ga composition ratio of 0.67, 1.28, 1.74, 2.86, and 2.42 at% with the pulsed time of 10, 50, 80, 100, and 130 msec, respectively. The results indicated that Ga doping concentration can be controlled by TEGa pulsed time, and concentration reached saturation after 100 msec. The Gonio scan results showed that the trend of GZO thin films were from poly crystal structure to (002) highly prefer orientation crystal structure with increasing Ga doping concentration from 0.67 to 1.74 at%. When the Ga doping concentration exceeded 1.74% the film reverted back to poly crystal structure.
In order to realize the electrical and optical properties of GZO thin films, Hall measurement and Ellipsometry was used. The carrier concentration and electrical resistivity GZO film was about 10²² /cm³ and 10^-4 Ω-cm respectively, which was comparable to ITO TCO glass. The steady growth rate of 0.67 to 1.74 at% GZO thin films were 1.3 Å/cycles and roughness were around few nanometers by Ellipsometry fitting, agreed with SEM cross section data. The refractive coefficient of the pure ZnO film was at n=2, however the coefficient down to n=1.8 with Ga doping in visible light at 633 nm. The lowest refractive coefficient was achieved n=1.76 at 1.74 at% Ga of GZO film. Interestingly, in contrast to ZnO nearly no absorption, the GZO films strongly absorbed with the extinction coefficient k=0.7 at 1.55 um in near-infrared range.

The growth of single domain ZnTe layers on heterovalent materials is expected for the devices utilizing Electro-Optic (EO) effects. The EO coefficient of ZnTe is one of the highest among the conventional semiconductor materials. (110) or (111) oriented ZnTe layers should be prepared on the heterovalent substrate which does not exhibit the EO characteristics. The transparent substrates should be used since the optical alignment tunings could be simplified. Sapphire was focused on for the substrate, and MBE growth of ZnTe layers have been performed on various substrate surface orientations. It was revealed that the insertion of the low temperature grown thin buffer layers, as well as the high temperature annealing (at 1000 to 1500^oC for ten to forty hours) of the sapphire substrate surface to realize atomically smooth surfaces were effective in achieving high crystal quality layers of ZnTe. The single domain ZnTe epilayers with the x-ray rocking curve linewidth of about 400 arcsec were achieved on c-plane (0001) sapphire substrates so far.
The nano-facet formation was observed for the m-plane sapphire substrate after the similar annealing. The characteristic nucleation profiles on various nano-facet structures were studied in this study to obtain the insight of the heterovalent interface and the epitaxial relationship. RHEED, AFM and XRD pole figures were mostly used to characterize the interface properties. The un-annealed substrate surface exhibited the featureless surface with the RMS roughness of about 0.3 nm. The m-plane was disappeared after the annealing, and the annealed substrate surface is covered with the periodic nano-facet structure consisting from 5 to 40 nm size of alternately appearing facet structures of r-planes and S-planes. The size of the structure was varied by the annealing condition, and height was about 5 to 10 nm when it was annealed at 1100^oC. The height was increased to 30 nm when the annealing temperature was increased to 1300^oC. The nucleation profiles of the low temperature buffer layer was drastically varied by those surface structures. RHEED patterns suggested that substrate surfaces of un-annealed and annealed at 1100^oC were fully covered with the amorphous layer after 3.5 nm of the deposition at around 100^oC. On the other hand, the RHEED pattern of the substrate was barely changed for the 1300^oC annealed substrate surface. The low temperature deposition of ZnTe on the r-plane substrate was also monitored in past and the RHEED pattern was barely changed even after the deposition of about 3.5 nm, which suggested that sticking of ZnTe on r-plane sapphire was very poor. It is notable that the deposition of ZnTe buffer layer at such low temperature range was affected by the substrate surface profile. The orientation of ZnTe layers on those various surfaces was similarly varied. The (211) oriented ZnTe layer was confirmed when the thick layer was grown on the un-annealed substrate. The orientation was shifted to (331) when the layer was grown on the 1100^oC annealed substrate. The epitaxial relationship of ZnTe on S-plane sapphire was studied in past, and the epitaxial relationship of ZnTe (111)//S-plane sapphire was confirmed. The (331) layer formation on the nano-facet structures was observed because this epitaxial relationship was maintained. The poor sticking of ZnTe on the r-plane of nano-facet has resulted in the preferential formation of ZnTe (111) on the S-plane of the nano-facet. The mixture of (211) and (331) ZnTe layer formation was observed for the layer formed on the 1300^oC annealed substrate surface. Insufficient formation of the buffer layer has probably caused the deterioration of the crystal quality.

This work was supported in part by the Waseda University Research Initiatives, by the Waseda University Grant for Special Research Projects, and by the Japan Society for the Promotion of Science Research.

High-resolution, flexible solid-state lighting displays have been recently emerging for mobile display applications.[1] Among many types, micro-light-emitting diode (LED) displays, which are fabricated by stamping–transfer-based assembly of mini-LED chips on foreign substrates,[2] would be promising for future flat panel displays of high color purity, ultrahigh on/off contrast, power efficiency, ultrafast response time, high-temperature tolerance, long lifetime, etc.[3] However, at the fabrication stages, there are lots of issues arising, such as defect-free assembly, high assembly cost, difficulty in LED-miniaturation for high-definition, and so on. Selective-area epitaxy, as a monolithic integration technique based on area-confined crystal growth, can be a surrogate technology for the integration of micro-sized LED arrays.
This talk deals with three topics of (i) selective-area epitaxy of microrod heterostructure LED arrays, (ii) van der Waals epitaxy of vertical nanorod arrays on graphene, and (iii) remote epitaxy of microrod across graphene for transferable and flexbile optoelectronic device applications. In detail, the selective-area metal–organic vapor-phase epitaxy (MOVPE) of GaN/ZnO microrod heterostructure LED microarrays are presented.[4] The structure for color-tunable nanorod LEDs are introduced, briefly.[5] Then, the use of graphene substrate is demonstrated. We focus to discuss the role of graphene as epitaxial seed and remote epitaxial template, which enables flexible and transferable device applications, respectively. For the use of graphene substrates, the nanoepitaxy of InAs nanowire arrays on graphene is presented. The critical factors leading to nucleation–growth of semiconductor nanostructures on graphene are discussed.[6] The thinnest substrate, that is single-layer graphene, is demonstrated for the epitaxy of vertical semiconductor nanowires.[7] We also show the epitaxial InAs/graphene/InAs double heterostructure fabricated via growth of InAs on both sides of suspended graphene. The method for position-controlled nanoepitaxy on graphene is presented as well. The nanorod LED arrays grown on graphene are presented, which work in a flexural form. Finally, remote epitaxy of ZnO microrod arrays on polar and apolar ZnO substrates across graphene is also introduced,[8] which signifies the ability of ultrathin graphene penetrating the electric field endowed from substrate. Based on the remote epitaxy, we present the transferable epitaxial microrod overlayer through delaminating the microrod/graphene from the mother substrate. The challenges and opportunities of selective-area epitaxy of semiconductors on graphene substrates are discussed toward future flexible, transferable displays technology.

References
[1] T.-H. Kim et al. Nat. Photon. 5, 176 (2011).
[2] S.-I. Park, Y. Xiong, R.-H. Kim et al. Science 325, 977 (2009).
[3] J. Day, J. Li, D. Y. C. Lie, C. Bradford, J. Y. Lin, and H. X. Jiang, Appl. Phys. Lett. 99, 031116 (2011).
[4] Y. J. Hong et al. Sci. Rep. 5, 18020 (2015); J. Jeong et al. Appl. Phys. Lett. 109, 101103 (2016); R. Mo et al. Appl. Phys. Lett. 111, 132104 (2017).
[5] Y. J. Hong et al. Adv. Mater. 23, 3284 (2011).
[6] Y. J. Hong and T. Fukui 5, 7576 (2011).
[7] Y. J. Hong et al. Nano Lett. 12, 1431 (2012); Adv. Mater. 25, 6847 (2013).
[8] J. Jeong et al. (to be published).

Monolithic integration of electronic and optoelectronic materials is a key technology for fabricating next generation devices such as three-dimensional large-scale integrated circuits and multifunctional mobile terminals. Fabricating semiconductor thin films on insulators (e.g., SiO₂, glass, and plastic) is one of the most promising solutions for the monolithic integration. The direct synthesis of semiconductors on insulators is attractive from the perspective of process cost compared to layer transfer techniques; however, the process temperature is strictly limited by the heat resistant temperature of the substrates and underlying devices. Moreover, most insulating materials are amorphous with no crystal structure. Hence, it has been quite a challenge to achieve high-quality semiconductor films on insulators at low temperature.

Group IV semiconductors including Si are non-toxic, inexpensive, and have high affinity with existing mature Si processes. We have developed technologies to synthesize group IV semiconductors such as Si [1,2], Ge [3-8], SiGe [9-11], GeSn [12,13], and graphene [14,15] on insulators at low temperature. Among these, we will introduce the following research topics.

(1) Advanced solid-phase crystallization leading to polycrystalline Ge having a hole mobility of 620 cm²/Vs, the highest value reported to date among semiconductor layers grown on insulators [7,8,11,13].

(2) Metal-induced layer exchange for large-grained (>50 μm), orientation-controlled Si_1-xGe_x (x: 0-1) layers working as a template for compound semiconductors and aligned nanowires [1-6,9,10].

(3) Ultralow temperature synthesis (< 100 °C) of Ge(Sn) for flexible electronics based on inorganic materials [12].

[1] R. Numata et al., Cryst. Growth Des. 13, 1767 (2013).
[2] K. Toko et al., J. Appl. Phys. 115, 094301 (2014).
[3] K. Toko et al., Appl. Phys. Lett. 101, 072106 (2012).
[4] K. Toko et al., Appl. Phys. Lett. 104, 022106 (2014).
[5] K. Toko et al., ACS Appl. Mater. Interfaces 7, 18120 (2015).
[6] R. Yoshimine et al., J. Appl. Phys. 122, 215305 (2017).
[7] K. Toko et al., Sci. Rep. 7, 16981 (2017).
[8] R. Yoshimine et al., Appl. Phys. Express 11, 031302 (2018).
[9] K. Toko et al., J. Appl. Phys. 122, 155305 (2017).
[10] K. Kusano et al., ACS Appl. Energy Mater. 1, 5280 (2018).
[11] D. Takahara et al., J. Alloys Compd. 766, 417 (2018).
[12] K. Toko et al., Appl. Phys. Lett. 106, 082109 (2015).
[13] K. Moto et al., Sci. Rep. 8, 14832 (2018).
[14] H. Murata et al., Appl. Phys. Lett. 110, 033108 (2017).
[15] H. Murata et al., Appl. Phys. Lett. 111, 243104 (2017).

Several transition-metal nitrides have lattice constants close to that of GaN or AlN and they possess very interesting electronic properties, therefore, offering intriguing possibilities for heterogeneous integration of functional materials on a powerful semiconductor platform. In this talk, I will share our recent work to epitaxially incorporate Nb and Sc in the AlGaN heterostructures. NbN is a well-known superconductor with a transition temperature about 17 K and typically its thin film is deposited using sputtering. Recently, NbN has been epitaxially grown using molecular beam epitaxy on SiC or AlN, which shows an excellent crystallographic registry to the underlying single crystalline substrate. This in turn enabled growth of AlN epitaxially on top of NbN, followed by a GaN high electron mobility transistor heterostructure [Rusen Yan et al, GaN/NbN epitaxial semiconductor/superconductor heterostructures, Nature 555, 183 (2018)]. Alloying Sc into AlN can significantly enhance the piezoelectricity of the resultant thin film, which has led to much improved performance in bulk acoustic wave (BAW) based on AlScN over AlN. More recently, AlScN is reported to be even ferroelectric [Simon Fichtner et al, AlScN: a III-V semiconductor based ferroelectric, arXiv:1810.07968, 2018].

The wide band gap II-VI compounds reported here are Zn_xCd_yMg_1-x-ySe-based, with x and y varying independently from 0 to 1. The large tunability of the band gap energy from 1.75 eV (CdSe) to 3.7 eV (MgSe) (at room temperature) makes the material system very attractive for optoelectronic device applications. One specific application is to fabricate intersubband devices that work at short wavelengths by utilizing the large conduction band offset offered by heterostructures made from the material system. Intervalley scattering, which is typically seen in III-V intersubband quantum structures when short wavelength limit is approached, does not exist in the II-VI material system due to the large energy difference among conduction band energy minima along different directions in wide band gap II-VI semiconductors. This may potentially boost the device efficiency when intraband electron energy transitions are employed to realize light generation, detection or modulation.

We report the growth and properties of Zn_xCd_yMg_1-x-ySe-based II-VI intersubband device structures. The structures were grown by molecular beam epitaxy (MBE) on III-V substrates and therefore can be vertically integrated with III-V devices and are compatible with mature III-V device fabrication technologies. By applying band structure engineering to semiconductor quantum structures, intersubband transition in the optical communication wavelength of 1.55 μm has been realized in metastable CdSe/MgSe coupled quantum well structures. The metastable structures were stabilized by the insertion of thick ZnCdSe spacer layers during MBE growth. Both the MgSe barrier layers thickness and the MgSe coupling layer thickness were optimized to achieve structures with the best intersubband transition characteristics.

Quantum-well infrared photodetectors (QWIPs) working in long wave IR and medium wave IR, the two important atmospheric windows, have been fabricated with the Zn_xCd_yMg_1-x-ySe-based II-VI materials. Different QWIP structures covering a relatively very large spectral range can all be grown lattice-matched on InP substrate. This can ensure the high absorption quantum efficiency of the detectors and is especially advantageous for two-color or multi-color QWIPs grown on the same substrate.

Topological insulators (TIs) are materials with a bulk bandgap crossed by surface states that exhibit linear dispersion and spin-momentum locking. Electrons occupying these surface states have low mass and large Fermi velocity, while the spin-momentum locking leads to a reduction in scattering, since a change in momentum requires a spin flip. Due to their unique band structure, these materials are promising for applications in electronics, spintronics, and optics. The crystal structure of standard TIs like Bi₂Se₃ is layered: one quintuple layer (QL) of Bi₂Se₃ is bonded to the next in the c-direction by van der Waals (vdW) bonds. The QLs are strongly bonded in the a-b plane. The weakness of the vdW bonding implies that thin films of Bi₂Se₃ can be grown using vdW epitaxy on a variety of substrates regardless of crystal structure and lattice constant. Although it is easy to obtain the correct crystal phase on multiple types of substrates, thin films tend to show substantial trivial carrier doping and low carrier mobilities regardless of growth conditions. This has made it difficult to create optoelectronic devices from these materials.
In this work, we show that the use of a trivially-insulating lattice-matched buffer layer between the Bi₂Se₃ film and the substrate substantially improves the electrical properties of the film. This implies that defects at the film/substrate interface are responsible for much of the unwanted doping in the film despite the use of vdW epitaxy. For TIs grown on sapphire substrates, a trivially-insulating buffer layer of (Bi_1-xIn_x)₂Se₃ (BIS) deposited between the film and substrate reduces the carrier density by more than a factor of two while providing a modest increase in mobility. We then applied this technique to TIs grown on GaAs(001), a technologically-relevant substrate. We find that BIS grown on GaAs(001) shows a variety of morphologies. In a narrow growth window, this material shows an extremely flat, hexagonal morphology. This is in contrast to the triangular, wedding cake morphology normally observed for vdW materials. We explain this morphology by examining the site-preferential incorporation of indium and bismuth. Although Bi₂Se₃ grown on this flat buffer still shows the triangular, wedding cake morphology, these films show a substantial decrease in bulk doping and an increase in mobility.
Finally, we show data demonstrating that these materials are excellent THz plasmonic materials. By etching the films into stripes, we are able to excite plasmonic resonances from the two-dimensional massless surface electrons. These Dirac plasmons are tunable across the THz band and show exceptionally large effective indices while maintaining long plasmon lifetimes. Films grown using the buffer layer technique show improved lifetimes when compared to films grown directly on sapphire. These materials are therefore extremely promising for THz plasmonic applications like gas sensing or on-chip waveguiding.

Laterally grown III-V epitaxial layers offer multiple advantages over conventional vertically grown layers for fabricating novel semiconductor devices, including choosing growth facets and lowering thickness of fins. To laterally grow epitaxial films, pre-fabricated dielectric templates are used to confine the growth and its direction. This technique was originally developed for Si [1,2] and later used for fabricating III-V semiconductor device structures on Si [3,4]. Such grown nanostructures often suffer from high densities of planar defects like stacking faults and rotational twins. Owing to the sub-micron scale of these embedded epitaxial layers, it is challenging to characterize them. Here we use scanning electron microscopy (SEM), transmission electron microscopy (TEM) and electron channeling contrast imaging (ECCI) to characterize the Confined Epitaxial Lateral Overgrowth (CELO) structures grown by chemical beam epitaxy (CBE) and metal organic chemical vapor deposition (MOCVD) on patterned InP (001) and InP (110) substrates. We explore the influence of growth conditions, growth direction, substrate orientations and fabrication procedures on the evolution of facets and the nature of defects observed. We further show growth and characteristics of CELO heterostructures and superlattice structures.

CBE growths were performed in a VG-Semicon V80H system using phosphine and trimethylindium as precursors with temperatures varying from 470-520 °C. Tilted SEM images show that the facets are dependent on the growth directions. Vertical facets form in structures growing in the <1-10> direction, while <001> oriented overgrowths show slanted {111}B facets for a InP(110) substrate. Cross sectional TEM images confirm these facets and reveal stacking faults in the {111} planes propagating throughout the growth. While the growth interface shows excellent crystalline quality in most cases, residues from improper cleaning during fabrication lead to formation of irregular facets. Both the (110) and the (001) oriented InP wafers exhibit similar stacking fault densities, while a reduction of the fault density is observed at higher temperatures. High angular annular dark field scanning TEM (HAADF-STEM) images of MOCVD-grown CELO InP/InAs and InP/GaAs heterostructures, as well as InP/InGaAs superlattice structures show that atomically thin heterojunctions can be realized in the lateral direction using this growth technique. While TEM shows more microstructural detail, ECCI provides an alternate way to qualitatively compare stacking fault densities and twin domains in these structures, with a much faster throughput and minimal sample preparation.

This work was supported by National Science Foundation and Semiconductor Research Corporation.

[1] A.Ogura et.al.Appl. Phys. Lett. 57, 2806(1989)
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[3] L.Czornomaz et.al. 2015 Symp VLSI Tech. Digest of Tech. Papers T172
[4] Moselund et.al.IEEE Trans.Elec.Dev.63,4233(2016)

Group III-V semiconductors have been a hot topic for decades due to the fact that they revolutionize electronics and optoelectronics because of their superior physical and optoelectronic properties including high carrier mobility, direct bandgap and band structure engineering capability. Reducing their dimension to the nanometer level not only brings many unique properties, such as large surface-area-to-volume ratio, high aspect ratio, carriers and photons confinement effect, but also enables the miniaturization of devices. Various nanostructures have already been demonstrated and applied to solar cells, lasers, light-emitting diodes, transistors, photoelectrochemical water splitting, etc. However, to date most efforts on the growth of group III-V nanostructures have been limited to zero- or one-dimension, such as quantum dots, nanowires and nanotubes. In this work, we demonstrate selective area growth of InP nanostructures, showing the possibility of obtaining other functional nanostructures, capability beyond the limitation of rod-like nanostructure and opening the way to more advanced device geometries.
Selective area growth of InP nanostructures with shapes such as tripod nanowires, nanocrosses, nanomembranes was conducted on InP substrates of different orientations. We investigate the link between the crystal structures, shapes, designed patterns and substrate orientations. For example, we found the crystal phase transitions from wurtzite to zinc blende with increasing nanoslot length along the certain crystallographic directions, indicating a strong correlation between crystal orientation and pattern confinement on the growth mechanism. Moreover, depending on the growth condition and substrate orientation, nanomembranes can be grown either vertically or tilted with respect to the substrate. Our results provide an insightful understanding on the growth mechanism of various InP nanostructures by selective area epitaxy, which favors the achievement of III-V/Si-integrated devices, and opens up many new possibilities for the shape engineering of III-V nanostructures.

A light hole ground state in a quantum dot is highly suitable for single spin optical manipulation due to the versatile optical selection rules [1]. By contrast to Stranski-Krastanov growth which results in flat quantum dots under compressive strain, hence a heavy-hole ground state, the dot-in-a-nanowire configuration is extremely flexible and virtually any material combination, any dot shape and any built-in strain can be realized. It allows one to engineer the hole states in semiconductor dots, and tailor their orbital and spin states: the ground state of a very long (L/D>>1) quantum dots is a light hole.
The vapor–solid–solid (VSS) growth mechanism is well adapted for the size and compositional control. Indeed it can result in compositionally abrupt interfaces and well-controlled aspect ratio by restraining the so-called reservoir effect normally observed in the most common vapor-liquid-solid (VLS) growth method.
ZnTe nanowires incorporating CdTe quantum dots and a ZnMgTe shell were grown by molecular beam epitaxy, at temperatures such that the Au nanoparticles are solid, as observed by RHEED.
VSS growth still remains much less understood than VLS. In particular, up to now, the role of the catalyst nanoparticle has been mainly overlooked. We show that different epitaxial relations with respect to the substrate coexist: this plays a key role in the nucleation of the nanowires.²
For all the growth steps, the effect of temperature appears to be crucial, particularly when considering the growth of CdTe used to form the quantum dot. The sublimation of CdTe and of the evaporation of Cd from the Au nanoparticles is crucial: these two effects must be taken into account in modelling the growth. ³
As a result, ZnTe nanowires incorporating very long (L/D>>1)^3,4 and very short (L/D<1)⁴ CdTe insertions and a ZnMgTe shell of controlled shape and composition were studied. Combining cathodoluminescence, micro-photoluminescence spectroscopy and autocorrelation measurements, we identify single dot exciton lines corresponding to excitons, bi-excitons and possibly charged ones. From linear polarization measurement in emission we found that for elongated quantum dots the intensity of the exciton line becomes stronger for polarization parallel to the nanowire axis, suggesting a light hole type ground state, as confirmed by a more complete study of the emission diagram and of magneto-optical spectroscopy ⁵.
References
¹ Y. H. Huo et al. Nature Physics 10, 46 (2014).
² M. Orrù et al., Appl. Phys. Lett. 110, 263107 (2017).
³ M. Orrù et al., Phys. Rev. Materials 2, 043404 (2018).
⁴ P. Rueda-Fonseca et al., J. Appl. Phys. 119, 164303 (2016).
⁵ M. Jeannin et al., Phys. Rev. B 95, 035305 (2017)

Heteroepitaxial structures between semiconducting nanowires and magnetic materials are of great interest for future nanoelectronic and spintronic devices. We have demonstrated the selective-area growth of vertical ferromagnetic MnAs nanoclusters/semiconducting InAs heterojunction nanowires by metal-organic vapor phase epitaxy, which is a catalyst-free bottom-up fabrication method. [1-3] These heterojunction nanowires provide new possibilities and versatility in the creation of novel vertical nanowire devices, e.g., spin-light-emitting diodes, surrounding gate spin-transistors, and THz-emitters. It is crucial to control the MnAs nanocluster formation and improve the size uniformity of heterojunction nanowires for such nanowire devices, and to investigate magnetotransport properties in detail. [4] This invited paper focuses on recent results of the formation and transport characterizations of vertical MnAs/InAs heterojunciton nanowires as well as single host InAs nanowires. The vertical heterojunciton nanowires were fabricated by endotaxial MnAs nanoclustering after the selective-area growth of host InAs nanowires on partially-SiO₂-masked GaAs (111)B substrates. The fabrication processes are described elsewhere in detail. [1, 2] The <0001> direction of hexagonal NiAs-type MnAs nanoclusters is parallel to the <111>B direction of zinc-blende-type InAs nanowires, as revealed by transmission electron and magnetic force microscopies. After the growth, the nanowires were detached from the substrates by ultrasonic vibration in isopropanol solution, and then, deposited on a SiO₂/Si substrate. In order to obtain ohmic contacts, the native oxide layer was removed by Ar milling at 30 W for 60 sec. Afterwards electronic contacts of Ti/Au (25 nm/165 nm) were structured by electron-beam evaporation and electron-beam lithography. A large positive ordinary magnetoresistance effect up to 150% is observed for temperatures between 120 K and 280 K. Angle-dependent transport measurements reveal additional boundary scattering due to the confined transport channel of InAs nanowire. In addition, magnetotransport characterization results of a single host InAs nanowire show universal conductance fluctuations and weak Anderson localization at low temperatures. A single MnAs/InAs heterojunction nanowire, on the other hand, shows only a negative magnetoresistance effect up to 10% at 10 T, which linearly decreases with magnetic field. Refs.: [1] Jpn. J. Appl. Phys. 55, 075503 (2016) open access; [2] Jpn. J. Appl. Phys. 56, 06GH03 (2017); [3] J. Cryst. Growth 464, 80 (2017); [4] Adv. Mater. 26, 8079 (2014) review paper.

Interface and extended defects severely affect ZnSe/GaAs based heterostructures. Many studies have been devoted to the improvement of this heterovalent interface, and, to the understanding of the defect generation mechanisms during growth and during operation of related optoelectronic devices. The lattice constants of ZnSe (0.5668 nm) and GaAs (0.5653 nm) are very close, however, the slight lattice mismatch produces a small compressive strain parallel to the interface of -0.00265 which is enough to produce misfit dislocations when the ZnSe film reaches the critical thickness h_c ~ 80 nm. On the other hand, due to the large lattice mismatch, h_c for CdSe (0.6077 nm) on ZnSe is only around 3.5 monolayers, after h_c is reached the excitonic emission of CdSe/ZnSe ultra-thin quantum wells (UTQWs) is negligible or even absent. Therefore, under typical growth conditions only 1 to 3 monolayers (MLs) thick UTQWs of CdSe/ZnSe/GaAs(001) with good crystalline quality and intense excitonic emission can be obtained.¹ One ML of the binary refers to the thickness of the cation-anion bilayer given by a/2, where a is the lattice constant. The 1 ML CdSe UTQW represents the thinnest CdSe QW that is possible to grow and some of its physical properties still deserve a detailed explanation and interpretation regarding its high excitonic emission intensity, the quite narrow full width at half maximum (FWHM),² and the peak energy dependence on growth parameters. Here, we present a study of a nominal 1 ML CdSe UTQW grown by atomic layer epitaxy (ALE) on GaAs(001) at 275 °C within a ZnSe barrier of 20 nm (the barrier adjacent to the substrate, i.e., the buffer layer forming the ZnSe/GaAs heterovalent interface), and a second ZnSe barrier of 25 nm (cap layer). The thickness of each layer and the total thickness of the heterostructure are chosen in such a way that each material is below its critical thickness, so we can obtain a fully strained heterostructure without misfit dislocations, expecting an UTQW with a high-quality crystalline structure. The 19 K photoluminescence spectrum presents an intense excitonic peak at 2.685 eV with a FWHM of 12.3 meV, which is narrower than previous results in CdSe UTQWs grown on relaxed ZnSe barriers.³ The evolution of the excitonic peak as a function of temperature follows very closely the expected smooth, monotonic behavior, indicating the absence of QW potential fluctuations due to thickness or composition inhomogeneities. The intensity of the excitonic peak in the photoluminescence experiments decreases rapidly with increasing temperature and it is difficult to observe at room temperature. This can be taken as an indication of the lack of exciton localization caused by potential fluctuations which, as mentioned before, are absent or negligible in the QW structure.

References
¹ I. Hernandez-Calderon, M. García-Rocha, P. Díaz-Arencibia, Phys. Status Solidi (b)24, 558 (2004).
² See, for example, T. V. Shubina, G. Pozina, A. A. Toropov, Phys. Status Solidi B254, 1600414 (2017).
³ I. Hernández-Calderón, AIP Conf. Proc. 809, 343 (2006).

Germanium-tin is a promising material for novel devices for optical sensing in the mid-IR region. For sufficiently high Sn compositions, the material has a direct band-gap near 0.5 eV, and could have applications either as a detector or as an emitter. The main challenge to growth of high-quality single crystals is the large lattice mismatch of the system (~14% for diamond cubic Sn on Ge) and the low equilibrium solubility of Sn in Ge (~1%). Demonstrations of core-shell Ge/GeSn nanowire structures have shown that it is possible to take advantage of a thin nanowire as a compliant substrate for high quality single crystal growth.^1,2 In this work, we show that a Ge nanowire can act as a template for both axial and radial growth of Ge/GeSn heterostructures by controlling H₂ partial pressure during CVD growth of GeSn. We are also able to achieve different Sn compositions varying from 2% to 10% using this method as confirmed by STEM-EDS and photoluminescence measurements. With control over axial to radial growth of GeSn heterostructures, a much wider possibility of device architectures can be achieved.

¹Meng, A. C., et al., Nano Letters (2016) 16 (12), 7521.
²Assali, S., et al., Nano Letters (2017) 17 (3), 1538.