Symposium Organizers
Tingkai Li Sharp Laboratories of America, Inc.
Yoshihisa Fujisaki Hitachi Ltd.
Jon Slaughter Freescale Semiconductor, Inc.
Dimitris Tsoukalas National Technical University
I1: Organic Nonvolatile Memories
Session Chairs
Tuesday PM, April 10, 2007
Room 3006 (Moscone West)
9:30 AM - **I1.1
Organic- and Bio-based Digital Memory Devices.
Yang Yang 1 2 3 , Ricky Tseng 1 3 , Liping Ma 1 2
1 Materials Sci. & Eng., UCLA, Los Angeles, California, United States, 2 California Nano System Institute, UCLA, Los Angeles, California, United States, 3 FENA Center, UCLA, Los Angeles, California, United States
Show Abstract10:00 AM - I1.2
Memory Effect in Organic Diodes containing Self-assembled Gold Nanoparticles
Hai Ping Wang 1 , S. Pigeon 2 , R. Izquierdo 3 , R. Martel 1
1 Chimie, Université de Montréal , Montréal , Quebec, Canada, 2 Thin films and microfabrication laboratory, OLA Display Corp., Montréal , Quebec, Canada, 3 Département d'informatique, Université du Québec à Montréal, Montréal , Quebec, Canada
Show AbstractElectrical bistability is reported in metal-organic-metal diodes. The device consists of two Al electrodes separated by a layer of organic material that contains embedded Au nanoparticles (NPs) supported by parylene nanopillars. The organic materials used in present work are 2-amino-4, 5-imidazoledicarbonitrile (AIDCN) and aluminum tris(8-hydroxyquinoline) (Alq3). Electrical characterization of the device made under vacuum condition shows two well-defined states with high (OFF) and low (ON) impedances. The ON/OFF ratio is about 104 for both kinds of devices. A negative differential resistance (NDR) in the current-voltage (I-V) characteristics is clearly observed. These bistable devices can be programmed and maintained in either the ON or OFF state for 8 months in air without any evidence of degradation. This conspicuous memory effect is rationalized in terms of charge storage mediated by the NPs states. The fabrication method is general and provides a good control on both the size-uniformity and the self-assembly of Au NPs embedded in the organic materials. The relationship of the electrical bistability to the nature and the thickness of the organic materials as well as the density of Au NPs will be addressed.
10:15 AM - I1.3
Programmable Memory Devices Using Semiconducting Nanoparticles in Insulating Polymers.
Basudev Pradhan 1 , Sudip Batabyal 1 , Amlan Pal 1
1 Dept. of Solid State Physics, Indian Association for the Cultivation of Science, Kolkata, West Bengal, India
Show Abstract10:30 AM - I1.4
Synthesis and Magnetism of 2D Mn(II) Carboxlates: Evidence of Remnant Moment at Room-Temperature
Shengming Liu 1 , Marshall Bremer 1 , Brandon Brandon 1 , John Lovaasen 1 , Anthony Caruso 1 , Douglas Schulz 1
1 Center for Nanoscale Science and Engineering, North Dakota State University, Fargo, North Dakota, United States
Show AbstractInitial studies toward the development of manganese(II) metal-organic complexes that possess a remnant moment at room temperature led us to the isolation of a new class of materials. A manganese(II) mixed-carboxylate complex, {Mn5(OC(O)CH3)6(OC(O)C6H5)4}n, was synthesized through a ligand exchange reaction under solvothermal conditions. Single-crystal XRD reveals a honeycomb-like 2D structure with the basic hexagonal Mn12 loops sharing edges. The sheets are spaced at 12 Å and linked into a 3D network with phenyl(benzoate) groups from one sheet interacting with both phenyl(benzoate) and methyl(acetate) groups of an adjacent sheet. Magnetic susceptibility characterization of {Mn5(OC(O)CH3)6(OC(O)C6H5)4}n) indicates antiferromagnetic exchange with a Weiss constant of -174 K and a transition toward ferromagnetic exchange below 10K observed in the χT(T). The absence of an imaginary component in the variable temperature susceptibility data indicates true antiferromagnetism yet no remnant moment was observed in M vs. H at 5K. By way of comparison, a closely related complex with the nominal stoichiometry Mn5(OC(O)CH3)5(OC(O)C6H5)5 does exhibit a remnant moment at room-temp (i.e., Hc = 30 Oe at 305K) with a powder x-ray diffraction pattern similar to {Mn5(OC(O)CH3)6(OC(O)C6H5)4}n. Recent results of this investigation will be discussed.
10:45 AM - I1.5
Resistance Switching in Organic–Based Devices; Mechanism and Addressability Issues.
Fredrik Jakobsson 1 , Xavier Crispin 1 , Magnus Berggren 1
1 Department of Science and Technology, Linköping University, Norrköping Sweden
Show AbstractIn the past few years, an increasing number of scientific contributions have reported bias-induced resistance switching for organic-based devices. These devices are appealing due to their low cost manufacturability, e.g. printing, and since they can be integrated into simple cross-point arrays.One example of such an organic memory device is Rose Bengal sodium salt sandwiched between indium tin oxide (ITO) and aluminum (Al) electrodes. Up to now, proposed switch mechanisms include electroreduction and field-induced conformational changes of the organic dye molecules (Bandyopadhyay et al, Appl. Phys. Lett. 2004, 84(6), 999-1001 and J. Phys. Chem. B 2003, 107, 2531-2536). However, conclusive evidence for either mechanism has not yet been presented.Here, we present a systematic study to rule out various mechanisms for the switching (redox reaction with ion motion, bistability of charge transfer salt, conformational changes). Similar switching behaviors are measured for many other molecules. The switch property does not appear to depend on the chemical nature of the organic molecules. Moreover, upon trying various electrode materials, ITO and/or Al electrodes have been identified to be the origin of the switch phenomenon. ITO and Al electrodes separated by the organic layer form conducting filaments, as demonstrated by the local dissipation of heat from the filaments analyzed using a high-resolution IR-camera.Switching of filaments has been reported for several decades, both in organic and inorganic materials. However, the switch behavior of Rose Bengal devices is polarity dependent, indicating that the switch mechanism is not of the same thermal run-away kind suggested for filamentary switch devices in the past. Moreover, the same filaments seem to be active after cycling the devices many times, indicating reversible filament formations. Similar results were recently reported for material systems commonly employed for organic light emitting diodes (M. Cölle et al, Org. El. 7 (2006) 305-312).When it comes to systems such as cross-point arrays of switch devices, several issues needs to be considered. A potential problem with filamentary switch devices is that they commonly require a very high current density to switch. This might result in problems such as potential drop along interconnect lines as well as very high circuit input currents (F.L.E. Jakobsson et al, Appl. Phys. Lett. 87, 063503 (2005)). By adding an extra semiconducting layer on top of the switch layer, leakage current from unaddressed devices can be greatly reduced, thus significantly improving system performance.
11:00 AM - I1: Organic
BREAK
11:30 AM - **I1.6
Silicon/Molecule Hybrid Devices.
James Tour 1
1 , Rice University, Houston, Texas, United States
Show AbstractAlthough a number of alternatives to silicon-based materials have been proposed, silicon remains the stalwart of the electronics industry. Generally, the behavior of silicon is controlled by changing the composition of the active region by impurity doping; while changing the surface (interface) states is also possible. As scaling to the sub-20 nm-size region is pursued, routine impurity doping becomes problematic due to its resultant uncertainty of distribution. Provided back-end processing of future devices could be held to temperatures that are molecularly permissive (300-350°C) and taking advantage of the dramatic increase in the surface-area-to-volume-ratios of small features, it is attractive to seek controllable modulation of device performance through surface modifications. If there is no intervening oxide between the p-rich molecules and the silicon, sequentially tuned molecular-structure changes can predictably regulate the device performances over a wide range. In this contribution, an electronically controlled series of molecules, from strong p-electron donors to strong p-electron acceptors, were prepared and systematically covalently attached as molecular monolayers onto the channel region of pseudo-MOSFETs (back gated), and the device modulation was studied. Changes of >2.5 V could be obtained in the threshold voltages by attaching monolayers atop the active regions of the transistors. Additionally, three-terminal field-effect transistors (FETs) were fabricated using intrinsic Si nanowires. Forming an F-terminated oxide surface significantly decreased the resistivity, increased the mobility, and they had a large hysteresis, enabling their possible use in memory devices.
12:00 PM - I1.7
Co Nanocyrstal Memory Devices Using Diblock Copolymer Micelle Templates
Chiyoung Lee 1 , Yongmu Kim 1 , Jang-Sik Lee 1 , Jaegab Lee 1 , Jeonghwa Kwon 2 , Byeong-Hyeok Sohn 2
1 School of Advanced Materials Engineering, Kookmin Univ., Seoul Korea (the Republic of), 2 Chemistry College of Natural Sciences, Seoul National Univ., Seoul Korea (the Republic of)
Show Abstract In this work, we present self-assembled diblock copolymer micelles can be used as a template to assemble Co nanocrystal arrays for charge storage layers in flash memory devices. Co-embedded diblock copolymer micelles were synthesized on the p-Si substrates having thin tunneling oxide of HfO2. Micelle templates were successfully removed by oxygen plasma treatment, resulting in CoOx nanocrystal arrays. It is demonstrated that CoOx nanocrystals were reduced to metallic Co by the hydrogen annealing. The resulting metallic nanocrystals were confirmed with a chemical shift of the Co2p3/2 peak by X-ray photoelectron spectroscopy analysis. We employed high-k dielectrics (HfO2 for both tunneling and blocking oxides) and high-work function metal gate (Pt) to engineer band-structures of memory devices. Co nanocrystals show very good distribution uniformity and the densities can be increased by a novel process. Devices exhibit program/erase characteristics that depend on the density of Co nanocrystals and thickness of tunneling oxide. The effects of nanocrystal density and tunneling oxide thickness on the memory windows as well as data retention characteristics will be discussed in detail.This work was supported by the ERC(CMPS, Center for Materials and Processes of Self -Assembly) program of MOST/KOSEF(R11-2005-048-00000-0)
12:15 PM - I1.8
Hierarchically Self-assembled Gold Nanoparticles in Polymer Matrix for Nonvolatile Memory.
Jung-Ah Choi 1 , Seong Jae Choi 2 , Sangkyu Lee 1 , Taeseup Song 1 , Chul Kim 1 , Jae-Young Choi 2 , Ungyu Paik 1
1 Division of Advanced Materials Science Engineering, Hanyang University, Seoul Korea (the Republic of), 2 Display Device & Material Lab, Samsung Advanced Institute of Technology, Yongin Korea (the Republic of)
Show Abstract12:30 PM - I1.9
Organic Composite Submicron Rods for Memory Applications.
Ashavani Kumar 1 , Victor Pushparaj 1 , Saravanababu Murugesan 2 , Jin Xie 2 , Caterina Soldano 1 , George John 3 , Omkaram Nalamasu 1 , Ajayan Pulickel 1 , Robert Linhardt 2
1 Materials Science and Engg., Rensselaer Polytechnic Institute, troy, New York, United States, 2 Department of Chemical and Biological Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States, 3 Department of Chemistry, City college of New York, New York, New York, United States
Show Abstract12:45 PM - I1.10
Electrical Properties of CuTCNQ Based Organic Memories Targeting Integration in the CMOS Back End-of-line.
Robert Mueller 1 , Joris Billen 1 3 , Rik Naulaerts 1 3 , Olivier Rouault 1 4 , Ludovic Goux 2 , Dirk Wouters 2 , Jan Genoe 1 , Paul Heremans 1 3
1 MCP/PME, IMEC vzw., Leuven, Vlaams-Brabant, Belgium, 3 ESAT, KULeuven, Leuven, Vlaams-Brabant, Belgium, 4 , INSA Toulouse, Toulouse France, 2 SPDT/FE, IMEC vzw., Leuven, Vlaams-Brabant, Belgium
Show AbstractI2: Nano-Particle and Advanced Flash Memories
Session Chairs
Erwin Prinz
Dimitris Tsoukalas
Tuesday PM, April 10, 2007
Room 3006 (Moscone West)
2:30 PM - **I2.1
Materials Challenges in Automotive Embedded Non-Volatile Memories.
Erwin Prinz 1
1 Technology Solutions Organization, Freescale Semiconductor, Austin, Texas, United States
Show AbstractSilicon-based nonvolatile memories are widely used in microcontrollers, where they are embedded into a monolithic system on a chip (SoC) which also includes high speed logic transistors, cache SRAM, and peripheral circuits for communicating with the external world. The physical principle most widely exploited for nonvolatile code and data storage is charge storage in floating gates. Recently, charge storage in nitride traps and nanocrystals also has been explored. The most demanding use profiles with respect to temperatures, data retention times, and low failure rates are encountered in automotive engine control applications, where junction temperatures up to 150°C are common, for 1000's of hours. Starting with the 130nm technology node, embedded Flash technology has been integrated with copper interconnects, and at the 90nm node, low dielectric constant interlevel dielectrics are also employed to increase circuit performance. To achieve automotive reliability, the materials surrounding the silicon floating gate, nanocrystal, or nitride charge storage area must be evaluated for parasitic charge storage, write/erase stress-induced leakage current, and other parameters important for reliability. Any movement of parasitic charge, potentially over a long period of time, can reduce the sensing window of the Flash EEPROM bitcell.In this talk, materials options for the various parts of the Flash bitcells are outlined, and the state of the art for 90nm embedded nonvolatile memory is summarized. Aspects of scaling to 65nm and beyond are also discussed.
3:00 PM - I2.2
Formation of Ge Nanocrystals in Lu2O3 High-k Dielectric and its Application in Non-Volatile Memory Device
Mei Yin Chan 1 , Pooi See Lee 1
1 Materials Science and Engineering, Nanyang Technological University Singapore, Singapore Singapore
Show AbstractA simple technique for the formation of Ge nanocrystals embedded in amorphous Lu2O3 high-k dielectric was demonstrated by pulsed laser ablation followed by rapid thermal annealing in N2 ambient. The structure and composition of the Ge nanocrystals in the oxide matrix have been studied by atomic force microscopy (AFM), transmission electron microscopy (TEM) and x-ray photoelectron spectroscopy (XPS). A significant change in the structural properties and chemical composition of the film was obtained upon annealing. Dot-shaped topography was observed from AFM characterization on the surface morphology of the annealed sample indicating the formation of Ge nanocrystals. Cross-sectional and plan-view TEM images confirmed the formation of small Ge nanocrystals in amorphous Lu2O3 matrix with a mean size of about 9nm in diameter and a high areal density of 7 x 1011cm-2. The nanocrystals are well-isolated by the amorphous Lu2O3 in between, with almost spherical shape which are favorable for non-volatile memory (NVM) application due to an effective charge confinement. XPS measurements on the as-deposited sample indicate the existence of Ge in its oxidized state, consisting of GeO2 and Ge suboxides. A complete reduction of GeO2 and GeOx was obtained after the annealing treatment which provides Ge nuclei for nanocrystal formation. It is found that a low annealing temperature of 400oC is sufficient to dissociate the GeO2 and GeOx leading to the formation of Ge nanocrystals. The application of the nanocrystals in NVM devices was demonstrated by C-V characterization of the memory capacitor devices fabricated with Al2O3 control oxide layer. C-V results show a significant effect of the structure and composition of the film on the electrical performance of the device. The annealed device exhibits good memory behavior with a large memory window of 1.2Vachieved with a low operation voltage.
3:30 PM - I2.4
Floating Nanodot Gate Memory Fabrication with Biomineralized Nanodot as Charge Storage Node.
Atsushi Miura 1 , Yukiharu Uraoka 1 , Takashi Fuyuki 1 , Ichiro Yamashita 1 2
1 Graduate School for Materials Science, Nara Institute for Science and Technology, Ikoma Japan, 2 , JST, Kawaguchi Japan
Show AbstractFloating nanodot gate memory (FNGM) is a promising candidate for future non-volatile memory. The performance of FNGM depends on the characteristics of utilized nanodots such as material, size, shape, distribution and density. Although the control of these issues is major challenge, it is still difficult by conventional methods. We adopted a biological path to solve these issues. Utilization of a cage-shaped supramolecular protein, ferritin, is potential option to achieve uniform and high-density memory node fabrication with size defined nanodots. Ferritin can biochemically form varieties of inorganic nanoparticle in its cavity by biomineralization such as metal oxides and compound semiconductors. Biomineralized nanodots are uniform in size and shape due to the restricted size of protein shell. Moreover, chemical flexibility of protein enables high-density and selective 2D arrangements of bionanodot on the substrate. Utilization of ferritin and its bionanodot offers precise control of size, shape, distribution and density of charge storage node of FNGM. In this contribution we demonstrate the FNGM fabrication with supramolecular protein ferritin and its inorganic bionanodot.The memory effect in FNGMs was investigated by fabricating bionanodot embedded metal-oxide-semiconductor (MOS) devices. Cobalt oxide bionanodot (Co-core) accommodated ferritin was deposited on p-type Si substrate with a 3 nm tunnel SiO2 layer. After the elimination of protein, Co-core array were buried into control SiO2 layers and metal electrode was deposited to make MOS structure. SEM and TEM images revealed uniform distribution of Co-cores on SiO2 surface with high density (>8E11 cm-2) and discrete distribution in stacked MOS structure. High frequency capacitance-voltage (CV) characteristics of Co-core embedded MOS capacitor at 1 MHz showed the obvious flat band shift with gate voltage sweep. Note that the CV of MOS capacitor fabricated without Co-core or with apoferritin showed no hysteresis. It suggests that observed flat band shift is due to the charge confinement to the embedded Co-core. Good charge retention after 10000 sec and endurance characteristics up to 100000 cycles of program/erase operation were observed on Co-core embedded MOS capacitor. The drain current-gate voltage (ID-VG) characteristics of Co-core embedded MOSFET showed threshold voltage shift due to the charge confinement to the embedded bionanodot as well as in capacitors. Co-core embedded MOSFET showed similar programming pulse duration dependence and obvious increase in memory window width with increasing of pulse duration. Charge retention characteristics of Co-core embedded MOSFET retained good memory window width after 10000 sec.These results indicate ferritin cores can be used as charge storage node of flash memory. This work proved the feasibility of the biological path for fabrication of electronic device components.
3:45 PM - I2.5
Self-aligned TiSi2/Si Hetero-nanocrystal Floating Gate Nonvolatile Memory
Yan Zhu 1 , Bei Li 1 , Jianlin Liu 1
1 EE Department, University of California, Riverside, Riverside, California, United States
Show AbstractSi nanocrystal as discrete floating gate in nonvolatile MOSFET memory devices has been extensively investigated [1, 2]. The issue of defect-related traps as reported in [2] for Si nanocrystals has led to device thermal instability. Although metal nanocrystal provides stable deep storage levels, the metal/oxide reaction has hindered its further application. In this work, we report that a novel MOSFET memory device with TiSi2/Si hetero-nanocrystals floating gate could resolve these issues.Using self-aligned silicidation method [3], TiSi2/Si hetero-nanocrystals were fabricated on ultra-thin thermal oxide. The process involved is thoroughly compatible to existing silicon process. The experiments showed very good self-aligned growth of TiSi2/Si hetero-nanocrystals on thin oxide with a slight size increase as compared to the original Si nanocrystals [4]. The metallic silicide on Si nanocrystal behaves as an extra quantum well to trap electrons. The activation (de-trapping) rate exponentially depends on the quantum well depth. Therefore, it enables a much lower charge loss rate, namely, much longer retention time. The prototype MOSFET memory cells with TiSi2/Si hetero-nanocrystal floating gate were fabricated. Programming/erasing performance of the device was investigated using both F-N tunneling and hot carrier injection. In both cases, the devices exhibited much better programming/erasing speeds, larger memory window, and very promising retention characteristics. The dual-bit/cell function was also investigated by writing charges to the hetero-nanocrystals near drain or source side, which showed a decent threshold voltage different between different read schemes. The TiSi2/Si hetero-nanocrystal memory showed similar endurance characteristics to the Si nanocrystal memory. In summary, TiSi2/Si hetero-nanocrystal memory is very promising in replacing Si nanocrystals for future-generation nonvolatile memory devices, fulfilling the target of being smaller, faster, and less power consuming.References[1] S. Tiwari, et al. Appl. Phys. Lett. 68, 1377 (1996).[2] Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, Jpn. J. Appl. Phys. 38, 425 (1999).[3] J. P. Gambino, and E. G. Colgan, Mater. Chem. Phys. 52, 99 (1998).[4] Yan Zhu, Dengtao Zhao, Ruigang Li, and Jianlin Liu, Appl. Phys. Lett. 88, 103507 (2006)* Corresponding author: Jianlin LiuEmail: jianlin@ee.ucr.eduTel: (951) 827-7131; Fax: (951) 827-2425
4:00 PM - I2: Post-Flash
BREAK
4:30 PM - I2.6
Temperature Dependence of Hole and Electron Conductance in Silicon Nanocrystal Arrays in SiO2
Gerald Miller 1 , Tao Feng 1 , Harry Atwater 1
1 Applied Physics, California Institute of Technology, Pasadena, California, United States
Show Abstract4:45 PM - I2.7
Magnetic Resonance Studies of Silicon Nano-Crystal Flash Memory Structures.
Jason Ryan 1 , Patrick Lenahan 1 , Lucky Vishnubhotla 2 , Sherry Straub 2 , Muralidhar Ramachandran 2 , Rajesh Rao 2 , Tushar Merchant 2 , Peter Kuhn 2
1 Materials Science and Engineering, The Pennsylvania State University, University Park, Pennsylvania, United States, 2 , Freescale Semiconductor, Austin, Texas, United States
Show AbstractAs the fundamental physical limits of conventional flash memory are approached, new forms of non-volatile charge storage structures must be explored. Conventional Flash memory devices suffer from stress induced leakage currents (SILC) caused by trap assisted tunneling which results in a reduction of data retention time [1-5]. The continued scaling of Flash memory devices has caused trap assisted tunneling related reliability problems to become more prominent [1-5].A promising potential solution to the trap assisted tunneling problems is the use of very small (mean diameter <10 nanometers) silicon nano-crystals [6]. In theory, silicon nano-crystal flash memory structures could reduce or eliminate the reliability problems associated with trap assisted tunneling because the tunneling process clearly involves highly localized tunneling current paths [4, 5, 7]. The introduction of nano-crystals will clearly help with the SILC problems involving the dielectric between the silicon channel and the nano-crystals (tunnel oxide) but the open spaces between the nano-crystals may lead to new problems. In a nano-crystal device, oxides “above” the nano-crystal layer (interlayer oxide) are exposed to charge carriers. In this study, we have begun to utilize electron spin resonance (ESR) measurements on silicon dioxide/silicon nano-crystal/silicon dioxide structures to explore the interaction of charge carriers and oxide defects in these systems. To simulate device operation, ESR measurements were made before and after the structures were subjected to electron and hole flooding. The densities of several intrinsic paramagnetic defects (most importantly, E’ centers) are greatly altered by the electron or hole flooding. We find that various post-deposition treatments quite significantly reduce or enhance the generation of these paramagnetic defects. A comparison of ESR and “electronic” measurements provides some physical insight into “electronic” roles these defects play. We find a strong, but imperfect, correlation between E’ generation and oxide leakage current. Preliminary results also suggest that, at least for the electron injection case, the generated E’ centers are electrically neutral. An additional interesting observation is that our results also indicate that there are far lower densities of silicon/silicon dioxide interface defects (Pb centers) located at the silicon nano-crystal/silicon dioxide interface than at the silicon channel/silicon dioxide interface. This surprising result may provide insight into the underlying physical mechanisms involved in interface trap generation. [1] P. Pavan et al., Proc. IEEE 85, (8) 1997[2] R. Bez et al., Proc. IEEE 91, (4) 2003[3] D. Ielmini et al., Microelectron. Eng. 80, 2005[4] R.A. Rao et al., Solid-State Electron. 48, (9) 2004 [5] J. De Blauwe, IEEE Trans. Nanotech. 1, (1) 2002[6] S. Tiwari et al., IEDM Tech. Digest 1995[7] B. De Salvo et al., IEEE Trans. Dev. Mater. Reliab. 4 (3) 2004
5:00 PM - I2.8
Charging Model of a Si Nanocrystal-based Floating Gate in a Quantum Flash Memory.
Yann Leroy 1 , Anne-Sophie Cordan 1 , Bertrand Leriche 1 , Daniel Mathiot 1
1 Solid State Electronics, InESS-ENSPS, Illkirch France
Show AbstractTuesday, April 10New Presenter - I2.8 @ 4:00 pmCharging Model of a Si Nanocrystal-based Floating Gate in a Quantum Flash Memory. Daniel Mathiot
5:15 PM - I2.9
Charge-trap Flash Memory by Partially-oxidized Amorphous Si Containing Nanodots.
Sangjin Park 1 , Daigil Cha 1 , Kwang Soo Seol 1 , Sangmin Shin 1 , Sangmoo Choi 1 , JungHun Sung 1 , Yoondong Park 1 , Joong Jeon 1 , InKyeong Yoo 1 , Eunha Lee 2 , Yo-Sep Min 3
1 Semiconductor device and material lab, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of), 2 AE center, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of), 3 Nano Fabrication Technology Center, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of)
Show AbstractWe introduce a fabrication method of Si nanodots (NDs) by partially-oxidizing amorphous Si (a-Si) grown by ion beam sputtering deposition (IBSD). A 2nm-thick a-Si layer was grown on top of a 5nm-thick thermal-oxide tunneling layer by reactive IBSD in ultra high vacuum, and subsequently oxidized by annealing the a-Si layer in 10% O2/N2 ambient at 900 oC for 1~9 min. After oxidation, a 20 nm thick Al2O3 control-oxide layer was grown by atomic layer deposition. We observed a positive shift of the memory window as the oxidation time increases, resulting from the decrease of the hole-trap sites. By 3-min oxidation we obtained Si NDs with an average size of 1~1.5nm and an areal density of ~2x1012/cm2 in partially-oxidized a-Si matrix. With this storage node, we successfully achieved a small charge-loss rate with a flat-band voltage shift less than 0.5V at 200oC, 2hr, which corresponds with 10 year data retention and a good endurance up to 105 cycles.
5:30 PM - I2.10
Multi-Bit Localized Charge Trapping Memories – Device Scaling of Twin Flash Cells to a 60nm Generation.
Torsten Mueller 1 , Ch. Kleint 1 , M. Isler 1 , S. Riedel 1 , T. Hoehr 1 , M. Strassburg 1 , F. Beug 1 , V. Pissors 1 , J. Sachse 1 , D. Manger 1 , D. Caspary 1 , S. Parascandola 1 , D. Olligs 1 , H. Boubekeur 1 , F. Heinrichsdorf 1 , V. Polei 2 , J. Gupta 1 , D. Pritchard 1 , U. Bewersdorff-Sarlette 1 , M. Verhoeven 1 , M. Markert 1 , Ch. Ludwig 1 , E. Stein v. Kamienski 1 , Th. Mikolajick 3 , N. Nagel 1
1 , Qimonda, Dresden Germany, 2 , Infineon Technologies, Dresden Germany, 3 Chair of Electronic- and Sensor Materials, Technical University of Technology and Mining, Freiberg Germany
Show Abstract5:45 PM - I2.11
Self-Organization of Ge Nanocrystals on FIB Patterned Substrates for Memory Applications
Isabelle Berbezier 1 , Alim Karmous 1 , Pierre-David Szkutnik 1 , Antoine Ronda 1
1 L2MP, CNRS, Marseille France
Show AbstractThe aim of this work is to develop a fabrication process based on Si or SiO2 FIB nanopatterning followed by Ge NCs self-organization. One of the major challenges of the study is to perfectly understand and control the fabrication of NC floating gate nanostructures in order to determine and to investigate electrical charging, discharching and retention mechanisms still under debate. The originality of the process developed is the scalability of NC size and density and the precise placement and ordering of NCs induced by the regular array of focused ion beam (FIB) nanoscale patterns. Combination of FIB nano-patterning and natural formation of Ge islands permits to circumvent most of the problems induced by self-organisation with a fabrication process of device structures with minimum perturbation of the conventional MOS transistor technology.The work has been divided in 5 major tasks : (1) Nano-patterning of the substrate by Focused Ga+ Ions Beam at the nanometer scale. The results indicate that holes of 15 nm diameter can be milled with a 50kV single beam FIB. The smallest pitch of 2D holes array created was 23 nm (hole diameter ~ 15 nm) which confirms the possibility to reach a hole density of ~ 2x1011 /cm2 which approximately corresponds to the optimized density obtained for memory devices in the literature. (2) Cleaning of the substrate by thermal annealing in ultra-high vacuum. Investigations have focused on the conditions for soft thermal annealing to guarantee total removal of crystalline defects and desorption of Ga implanted atoms without modifying the holes shape/size. Two different cleaning procedures based on chemical etching and rapid thermal annealing cycles have been developed on Si substrate and on SiO2. (3) Fabrication of an array of isolated Ge quantum dots (QD). Two processes using FIB patterning have been developed one on Si substrate and the other on thin SiO2 layer. We show that Ge NC are ordered either inside the FIB holes or in between the FIB holes on Si substrate depending on the growth temperature. We explain this behaviour by kinetically limited nucleation at low temperature and by minimization of elastic energy at high temperature. On SiO2, NC size and density can be controlled by adjusting the initial deposited thickness. Positioning of Ge NC is mainly controlled by surface energy minimization. 2D arrays of perfectly ordered highly dense (> 1011/cm2) and ultra-small (~ 20 nm) Ge dots have been obtained. (4) Fabrication of the oxide (tunnel and control oxide) by thermal oxidation. Tunnel SiO2 oxide layers used were 3.5 and 5 nm thick, showing perfect C-V characteristics and low leakage currents. Control oxide was a TEOS stoichiometric SiO2 layer.(5) Memory device fabrication and electrical characterisation. Capacitors and transistors samples were fabricated. The C-V characteristics of samples without and with FIB ordering will be presented and compared.
I3: Poster Session: Organic and Nano-particle Flash Memories
Session Chairs
Dimitris Tsoukalas
Y. Yang
Wednesday AM, April 11, 2007
Salon Level (Marriott)
9:00 PM - I3.1
Making Plastic Remember: Electrically Rewritable Polymer Memory Devices.
Dominic Prime 1 , Shashi Paul 1
1 Emerging Technologies Research Centre, De Montfort University, Leicester, Leicestershire, United Kingdom
Show AbstractIn recent years there has been a growing interest in both academia and industry in the field of organic electronics and organic semiconducting materials as low cost, easily processible alternatives to silicon and other inorganic semiconductors. There have so far been successful implementations of devices such as organic field effect transistors (OFETs), organic solar cells and organic light emitting diodes (OLEDs), with OLED’s being the main organic devices to have achieved commercial success. In the field of non-volatile polymer memory devices (PMDs) there has been considerably less research conducted. Plenty of structures have shown bistable behaviour, however to make a viable memory devices any new organic memory must either match, or surpass the performance of conventional silicon memory in terms of retention time, memory cycles and power consumption [1]; criteria which so far polymer memories fail to meet sufficiently in one, or more areas.
Among the most promising PMDs to date are devices consisting of an admixture of organic polymer, nanoparticles, and small organic molecules deposited between top and bottom metal electrodes to form a crossbar structure [2, 3]. When voltages are applied, the device can switch between two different conductivity states, with the state being read by an intermediate voltage.
PMDs based on active layers containing gold nanoparticles with 8-hydroxyquinoline (8HQ), and also C
60 with 8HQ will be presented, showing the devices’ electrical characteristics and memory performance attributes. Results presented will give a greater understanding of the physical mechanisms responsible for the change in conductivity states of these devices, which is essential for the realisation of viable organic memory technologies.
References:
[1] J. C. Scott. "Is There an Immortal Memory?" Science, 304, 62-63, (2004)
[2] J. Ouyang, C. -W. Chu, C. Szmanda, L. Ma, Y. Yang, "Programmable Polymer Thin Film an Non-Volatile Memory Device" Nature Materials, 3, 918-922, (2004)
[3] S. Paul, A. Kanwal, M. Chhowalla. "Memory Effect in Thin Films of Insulating Polymer and C60 Nanocomposites" Nanotechnology, 17, 145-151, (2006)
9:00 PM - I3.10
Oxide-nitride-oxide Dielectric Stacks with Embedded Si-nanoparticles Fabricated by Low-energy Ion-beam-synthesis.
Vassilis Ioannou-Sougleridis 1 , Caroline Bonafos 2 , S. Schamm 2 , G. Ben-Assayag 2 , P. Dimitrakis 2 , V. Vamvakas 2 , P. Normand 2 , Dimitris Tsoukalas 3
1 , IMEL/NCSRD, Aghia Paraskevi Greece, 2 , CEMES/CNRS, Toulouse France, 3 Applied Sciences, National Technical University, Athens Greece
Show Abstract9:00 PM - I3.11
The Study on Charge-trapping Mechanism in Nitride Storage Flash Memory Device.
Jia-Lin Wu 1 , Hua-Ching Chien 1 , Chi-Kuang Chang 1 , Chien-Wei Liao 1 , Chih-Yuan Lee 1 , Je-Chuang Wang 1 , Yung-Fang Chen 2 , Chin-Hsing Kao 1
1 Semiconductor Laboratory, Chung-Cheng Institute of Technology, National Defense University, Taoyuan Taiwan, 2 Department of Physics, National Taiwan University, Taipei Taiwan
Show AbstractThe nitride storage flash memory with polysilicon-oxide-nitride-oxide-silicon (SONOS) structure has received much interest recently due to lower operation voltage, simpler fabrication process, higher density, and elimination of the drain induced turn on effect and multi-bit operation. Contrary to the floating gate device where charges are uniformly stored in the floating gate, the charges are discretely trapped in the nitride thin film. Therefore, the distribution of nitride trap is very significant in understanding the trapping efficiency of flash memory devices.In this work, the charge-trapping energy level distributions of SiNx films with different composition ratio deposited by low-pressure chemical vapor deposition (LPCVD) were first characterized by photoluminescence (PL) measurement. Moreover, using F-N/CHE program and charge pumping techniques, the vertical location and the lateral distribution of programmed charges are investigated in the nitride films with different composition ratio.The study offers strong evidence that the density of charge-trapping levels in the Si-rich nitride is higher than the standard nitride. A simple qualitative model and calculation explains that the trapping level distributions in the SiNx films are shallower by increasing relative Si-content. Furthermore, we have observed the nitride trap vertical location was changed by adjusted Si/N composition ratio. And the lateral distribution of hot electron programmed charges in the Si-rich nitride is broader than that in the standard nitride because it offered more charge-trapping sites and shallower charge-trapping levels. In summary, the study can help researchers to understand the nitride charge-trapping mechanism and the analysis of optical/electrical characteristics.
9:00 PM - I3.12
A Comparison of N+ type and P+ type Polysilicon Gate in High Speed Non-Volatible Memories
Moon Kyung Kim 1 , Soodoo Chae 2 , Chungwoo Kim 2 , Sandip Tiwari 1
1 Electrical and Computer Eng., Cornell University, Ithaca, New York, United States, 2 Semiconductor R&D Center, Samsung Electronics, Kiheung Korea (the Republic of)
Show AbstractSilicon-Oxide-Nitride-Oxide-Silicon (SONOS) [1] and nano-crystal memory [2] have been considered as a replacement floating gate memory due to simple process, low voltage operation and high speed. In the SONOS memory, an ultra-thin oxide-nitride-oxide (ONO) film with high trap density and strong localization of the trapping provides the scalability and retention. This may allow longer retention with thinner tunneling dielectrics, leading to lower operating voltages.However for the high speed performance, SONOS needs improvement in erase time - the discharging process of electrons from the traps. Thus we have speculated on the effect of electric fields in the trapping-control gate region, and characterized the effects of doping on poly-silicon gate in SONOS memory device. Our experiments compare the characteristics of SONOS memories between n+ type and p+ type polysilicon gate. Figure 1 shows the schematics of these structures. SONOS memory devices have been fabricated with 0.5 um n+ type gate or p+ type gate on SOI substrates using the conventional CMOS processing technology. The tunneling oxide of 3 nm thickness was grown at 900 C and then a Si3N4 film of 5.5 nm and the blocking oxide layer of 7 nm were deposited by low pressure chemical vapor deposition (LPCVD). Figure 2 shows a transmission-electron micrograph of the cross-section of this grown and deposited memory stack with the dark region as the silicon nitride. After these gate stacks process, n+ type or p+ type poly-silicon is deposited. Using the program/erase threshold voltage window as 4 V in p+ type poly-silicon gate memory, the program time is approximately 20 us at 16 V program voltage and the erase time is about 1 ms at a –16 V erase voltage using FN tunneling method. The capture and erase characteristics also show asymmetries in the capture and erase processes due to the physical differences in the processes themselves. The capture process is based on Fowler-Nordheim injection where the relevant capture cross-section is related to the extent of the potential perturbation of the defect. This capture cross-section is one to two orders of magnitude smaller than that of silicon nanocrystals. The erasure process is presumably a Poole-Frenkel mechanism, or other similar de-trapping process with strong localization and field-dependence. The erase time of SONOS memory device is somewhat slow, and it is due to the injection of electrons through top oxide from the gate and heavy mass of holes. To solve this problem, several methods have been introduced recently. Using a high k material instead of SiO2 thin film is useful for decreasing the transmission of electrons in the top oxide due to the capacitive coupling [3].Also we expect that the higher work-function of p-type gate to improve erase speed. Figure 4 shows that the erase speed of p+ gate is much faster than that of n+ gate. The work will describe detailed experimental measurements in support of this conclusion.
9:00 PM - I3.13
The Effects of the LDD process on Short-channel effects in Nano-scale Charge Trapping Devices.
Moon Kyung Kim 1 , Soodoo Chae 2 , Chungwoo Kim 2 , Jooyeon Kim 3 , Sandip Tiwari 1
1 Electrical and Computer Eng., Cornell University, Ithaca, New York, United States, 2 Semiconductor R&D Center, Samsung Electronics Co, Kiheung Korea (the Republic of), 3 School of Electricity & Electronics, Ulsan college, Ulsan Korea (the Republic of)
Show Abstract9:00 PM - I3.14
Silicon Compatible Nonlinear Dielectric as Tranistor Gate for use as Nonvolatile Memory Element.
Joseph Cuchiaro 1 , Edwin Dons 1 , Jie Yao 1 , S. Sun 1 , Catherine Rice 1 , Lloyde Provost 1 , Gary Tompa 1
1 , Structured Materials Industries, Inc., Piscataway, New Jersey, United States
Show AbstractNonvolatile memory elements have been demonstrated using nonlinear dielectric thin films (NLD) implemented as a transistor gate (NLDFET). The NLD films are formed using Metal Organic Chemical Vapor Deposition (MOCVD). The NLD films exhibit a hysteresis characteristic obtained from application of an applied voltage to the transistor gate in sufficient magnitude to modulate the inversion region of the underlying silicon post removal of the applied voltage. The hysteresis property is obtained at extremely high speed (< 10 ns) for both write and erase operation and at low voltages compatible with state-of-the-art silicon integration (90nm and below). Thus, the our NLD films have a significant potential to be implemented as a high-density nonvolatile memory element that meet and surpass existing FLASH technology in a single transistor memory. Further, the NLD films can replace SiO2 gate materials in logic elements. Successful implementation of NLD films into silicon integrated circuits would revolutionize existing stand-alone and embedded memory technology.In this work, we report the materials properties of NLD thin films grown by SMI’s MOCVD technology for NLDFET application into silicon integrated circuit devices. General NLD film process parameters relevant to silicon transistor integration, NLD material properties, NLDFET device electrical performance are addressed.
9:00 PM - I3.16
Effect of AlON Thin Films as Top Blocking Oxide for NVM.
Kyungsoo Jang 1 , Sunghyun Hwang 1 , Kwangsoo Lee 1 , Jeoungin Lee 1 , Hyungjune Park 1 , Seongwook Jeong 1 , Junsin Yi 1 , Ho-kyoon Chung 2 , Byoung-Deog Choi 2 , Ki-yong Lee 2
1 , SungKyunKwan University, Suwon Korea (the Republic of), 2 , Samsung SDI Co, Ltd., Gyeonggi-do Korea (the Republic of)
Show AbstractThe state-of-the-art techniques for Non-volatile Memory (NVM) have been an important part of modern information processing systems. Among them, one of noticeable technique is the usage of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS). According to previous studies, as physical size of SONOS structure gradually become smaller, vertical size of device material is tend to decrease as well. Specifically in the case of gate oxide, this characteristic causes leakage current problem when oxide size is within special size. To solve this problem effectively, various technique are considered to achieve increase of dielectric constant of gate oxide layer. One of them is to apply material with increased dielectric constant. Throughout ensuring of charge storage, we can expect decrease of leakage current which flows within gate. In this study, we examined the electrical properties of AlON among various high-k materials which will be used for top blocking oxide layer. For the preparation of thin film, AlON thin films of 35Å~65Å thickness were deposited by RF magnetron sputtering on n-type silicon (Si) substrate of (100) orientation using Ar and O2 gas at substrate temperature of 300C. After that, electrical properties of Metal-Insulator-Semiconductor (MIS) type of AlON was analyzed and then characteristic of high-k(K)/Nitride(N)/Oxide(O) structure in MIS was studied. From this experiment, we observed significant result from the case of AlON which has approximate depositing thickness of 40Å. As the value of capacitance-voltage (C-V) hysteresis of this AlONwas 0V, the size of memory is almost value of 0 as well. Therefore, we concluded that this AlON can function as good insulator as well as blocking oxide in KNO structure under specific circumstance. Besides, we also found new characteristic, increased state of flatband voltage(VFB) according to increase of depositing thickness of AlON.
9:00 PM - I3.17
Synthesis and Non-volatile Memory Behavior of Redox Active Conjugated Polymer Containing Ferrocene Unit
Tae-Lim Choi 1 , Kwang-Hee Lee 2 , Won-Jae Joo 2 , Sangkyun Lee 2
1 Electronic Chemical Material Division, Cheil Industries, Inc, Uiwang-si, Gyunggi-do, Korea (the Republic of), 2 Display Device and Material Lab, Samsung Advanced Institute of Technology, Yongin-si, Gyunggi-do, Korea (the Republic of)
Show AbstractDuring the past decade, organic electronics have attracted great amount of attentions after demonstrating their applications on OLEDs, OTFTs and photovoltaic cells. It is due to their advantages such as flexible and low-cost devices arising from solution process such as spin-casting and ink-jetting. Among the several research fields on organic electronics, one of the newly emerging areas is the organic memory application where information is stored in organic materials. In addition to the common advantages for organic electronics, the organic memory can take advantages from its good scalability and 3D stacking to achieve high-density memory. Recently, many research groups have reported non-volatile organic memory device based on various mechanisms. Here, we demonstrate the synthesis of a new conjugated polymer with redox active functionality, ferrocene and its non-volatile memory behavior. In organic memory devices, the data are stored based on a change in the resistance of the organic layer. Our study focuses on ferrocene as the active component since its redox is well-studied and ferrocinium (Fe3+), the oxidized form is also stable which gives possibility for the non-volatility. Therefore, the design concept was to attach ferrocene to conjugated polymer to induce bistability by redox process and this could be applied a resistance memory. With this consideration, a new polymer, PFT2-Fc was synthesized by Suzuki polymerization similar to the well-known polymer, PFT2 used in OTFT devices. Ferrocene group was randomly inserted in the polymer backbone to give high molecular weight PFT2-Fc. HOMO and the band gap of the polymer were found to be 5.3 eV and 2.4 eV respectively. CV revealed two oxidation potentials at 0.6 and 1.0 V. This polymer was fabricated into device with ITO/polymer/LiF/Al structure. The initial memory behavior was observed with I-V characteristics by sweep mode. The device was turned on at -2V allowing high current to flow and turned off at 1.4V. The endurance of our memory device was examined by write-read-erase-read cycles (-2 V/0.2 V/2 V/0.2 V respectively) in pulse mode. More than fifty cycles with on/off ratio up to 1000 was observed. It is notable that the threshold voltages for both on and off states of are low at ± 2 V. Lastly, to demonstrate the non-volatility of the organic memory device, the retention time for PFT2-Fc device was measured and found that the device stably retained the on/off states for several hours. In conclusion, we demonstrated non-volatile organic memory device using ferrocene containing conjugated polymer, PFT2-Fc. The device operated at low driving voltages with high on/off ratio. Although the retention time and the switching cycle are still far from the satisfactory level compared to the current Si technology, the research on organic memory is still in infant stage and its device performance is expected to increase as the methods of the fabrication process improves.
9:00 PM - I3.18
Material Properties of Mixed Polymer and Gold Nanoparticles Structure for Memory Applications
Yan Song 1 , Qidan Ling 2 , Siew Lay Lim 2 , Eric Yeow Hwee Teo 1 , Yoke Ping Tan 1 , En-Tang Kang 2 , Daniel Siu Hung Chan 1 , Chunxiang Zhu 1
1 Electrical and Computer Engineering, National University of Singapore, Singapore Singapore, 2 Chemical and Biomolecular Engineering, National University of Singapore, Singapore Singapore
Show AbstractOrganic materials have been aggressively explored for semiconductor device applications. Very recently, organic memories have received a great attention due to their simple structure, good scalability, CMOS compatibility, and most importantly, low cost. Several kinds of organic materials were found to exhibit memory effects. Of these organic materials, poly (N-vinylcarbazole) (PVK) mixed with gold nanoparticles is a promising candidate due to their simple structure. By using PVK mixed with gold nanoparticles as the active layer, the device showed a good flash-typed memory performance. Till now, the research about the effect of mixing ratio of PVK to gold nanoparticle on the material property is still absent, which makes it difficult to fully understand the mechanism of memory behavior. In this paper, we present a study of the material properties (such as optical, physical and electrical properties) of mixed PVK/gold nanoparticles thin films with various mixing ratio. By using different characterization tools, we shall understand the effect of the mixing ratio of PVK to gold nanoparticles on the material properties.
9:00 PM - I3.2
Memory Effect in Ferroelectric PVDF Copolymer Integrated MOS Structure for Nondestructive Readout Memory Devices.
Sang-Hyun Lim 1 , Rastogi Alok 1 , Seshu Desu 1
1 Electrical and Computer Engineering, Univ. of Massachusetts, Amherst , Massachusetts, United States
Show Abstract9:00 PM - I3.3
Nonvolatile Memory Characteristics of Si-nanocrystal Floating-gate MOSFETs Fabricated by Using 0.5 μm CMOS Standard Processes.
Min Choul Kim 1 , Yong Min Park 1 , Sung Kim 1 , Suk-Ho Choi 1 , Kyung Joong Kim 2
1 College of Electronics and Information, Kyung Hee University, Yongin, Kyungkido, Korea (the Republic of), 2 Division of Advanced Technology, Korea Research Institute of Standards and Science, Taejon Korea (the Republic of)
Show Abstract9:00 PM - I3.4
Silicon Nanocluster Formation by a Pulse-type Gas Feeding Technique in the LPCVD System for the Nonvolatile Memory Applications.
Kyongmin Kim 1 , Eunkyeom Kim 1 , Myeongwook Bae 2 , Daeho Son 1 , Juhyung Lee 1 , Moonsup Han 2 , Junghyun Sok 1 , Kyoungwan Park 1
1 Dept. of Nano Science and Technology, University of Seoul, Seoul Korea (the Republic of), 2 Dept. of Physics, University of Seoul, Seoul Korea (the Republic of)
Show Abstract9:00 PM - I3.5
The Optical and Electrical Properties of SiOx (x<2) Thin Films Prepared by Pulsed Laser Deposition Technique.
Byoung Youl Park 1 , Sol Lee 1 , Chang Hyun Bae 2 , Seung Min Park 2 , Kyoungwan Park 1
1 Dept. of Nano Science and Technology, University of Seoul, Seoul Korea (the Republic of), 2 Dept. of Chemistry, Kyung Hee University, Seoul Korea (the Republic of)
Show Abstract9:00 PM - I3.6
Nonvolatile Memory Device Based On Nanoparticle Functionalized Tobacco Mosaic Virus.
Chunglin Tsai 1 , Ricky Tseng 2 , Liping Ma 2 , Yang Yang 2 , Cengiz Ozkan 3
1 Electrical Engineering, University of California Riverside, Riverside, California, United States, 2 Material Science and Engineering, University of California Los Angeles, Los Angeles, California, United States, 3 Mechanical Engineering, University of California Riverside, Riverside, California, United States
Show AbstractNanostructured protein shelled viruses are attractive templates in ordering quantum dots for constructing self-assembled building blocks towards next generation electronic devices.1 So far, only a few examples of electronic devices have been fabricated from biomolecules due to the lack of charge transport through biomolecular junctions. Here, we report a novel electronic memory effect by incorporating platinum nanoparticles over Tobacco Mosaic Virus templates. The recorded memory effect is based on conductance switching which leads to the formation of bistable states with an on/off ratio larger than three orders of magnitude. The mechanism of this process is attributed to charge trapping in the nanoparticles for data storage and a tunneling process in the high conductance state. Such hybrid bio-inorganic nanostructures are promising for applications in nanoelectronics.
9:00 PM - I3.7
A Low-voltage-operative Nanocrystal Memory Made with High-k Control Oxide.
Chen Chan Wang 1 , Chun-Sheng Liang 1 , Jiun-Yi Tseng 1 , Tai-Bor Wu 1
1 Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan
Show Abstract9:00 PM - I3.8
Deposition of Uniform Size Metallic Nanoparticles for use in Non Volatile Memories
Emanuele Verrelli 1 , Dimitris Tsoukalas 1 , Konstantinos Giannakopoulos 2 , Dimitris Ioannou 3
1 Physics, National Technical University of Athens, Athens, Attikis, Greece, 2 Institute of Material Science, NCSR Demokritos, Aghia Paraskevi, Attikis, Greece, 3 Electrical Engineering, George Mason University, Fairfax, Virginia, United States
Show AbstractAn important issue in nanocrystal memories that is still remaining open it is the control of size and density uniformity of the nanoparticle layer. Especially for metallic nanoparticles the existing methods which rely on the deposition of a thin metal film and subsequent annealing to form the nanoparticles result in uncontrolled size distribution. In this work we are presenting results on the formation of nickel nanoparticles on a thin tunneling thermal SiO2 layer using a new nanoparticle manufacturing technique. The technique is based on a physical vacuum deposition process. Particles are generated using a high-pressure magnetron sputtering device and carried away from the target area by the discharge gas into a condensation zone where nanoparticles are grown. The nanoparticles after being swept through this zone enter the chamber through a final aperture and they are soft-landed on the oxide surface. This way room temperature formation of nanoparticles becomes possible under high purity vacuum conditions. Nanoparticles with size distributions of ±20% and density distributions that can vary between 10^10 cm-2 and 10 ^12 cm-2 are formed. Minimum achieved size of the nanoparticles is 2 nm and maximum size 14 nm by proper variation of process parameters. After analysis of the above results which have been obtained by Transmission Electron Microscopy imaging, we have realized two terminal devices by depositing a control oxide (HfO2) and a patterned metal electrode over the nanoparticle layer. The non volatile memory properties of the structure were then monitored by electrical measurements and correlated with size and surface density distribution of the nanoparticles.
9:00 PM - I3.9
Characteristic of Tellurium films by Remote Plasma Atomic Layer Deposition
Do-Heyoung Kim 2 3 , Hun Jung 1 3 , Yeon-Hong Kim 1 3 , June-Key Lee 4
2 School of Applied Chemical Engineering, Chonnam National University, Kwangju Korea (the Republic of), 3 BK21 Division of Functional nano-novel chemical materials, Chonnam National University, Kwangju Korea (the Republic of), 1 Department of Fine Chemical Engineering, Chonnam National University, Kwangju Korea (the Republic of), 4 School of Materials Science & Engineering, Chonnam National University, Kwangju Korea (the Republic of)
Show AbstractTellurium(Te) films were prepared on TiN/Si and SiO2/Si substrates by remote plasma assisted atomic layer deposition (RPALD). The effects of process parameters, such as deposition temperature, plasma power, plasma pulse time, reactant gas composition, purge pulse time on the characteristics of the films were investigated. Precursor used for tellurium deposition is di-isopropyl-tellurium, [Te(C3H7)2], and hydrogen / argon gases were used as activated reactant. The vapor pressure of tellurium precursor at room temperature were found to be high enought for ALD in this work. Tellurium films were deposited at 423 ~ 573 K, deposition pressure of 1 Torr, plasma power of 250 W. The characteristics of the deposited films were characterized by using the following techniques : The thickness and crystallinity of the films was determinded by x-ray reflectivity (XRR) and x-ray diffraction (XRD), respectively. The cross-section of the films was observed by a field-emission scanning electron microscope (FESEM) and the surface morphology was investigated by atomic force microscopy (AFM) in contact mode under air atmosphere. A chemical composition of the film was obtained by depth profile of auger electron spectroscopy (AES). Also, the reaction mechanism involving tellurium RPALD was investigated by using gas-chromatorgraphy mass spectroscopy (GC-MS).
Symposium Organizers
Tingkai Li Sharp Laboratories of America, Inc.
Yoshihisa Fujisaki Hitachi Ltd.
Jon Slaughter Freescale Semiconductor, Inc.
Dimitris Tsoukalas National Technical University
I4: Resistive Switching Non-volatile Memories I
Session Chairs
Wednesday AM, April 11, 2007
Room 3006 (Moscone West)
9:30 AM - **I4.1
RRAM electronics and Switching Mechanism
ShengTeng Hsu 1 , Tingkai Li 1
1 5, Sharp Laboratories of America, Camas, Washington, United States
Show AbstractThere are several mechanisms proposed to explain the pulse induced resistance change in RRAM resistor. Those models are unable to explain the uni-polar switching of the memory resistors. All as-symmetrical RRAM devices we fabricated showed bipolar as well as uni-polar switching properties. All symmetrical RRAM devices we fabricated exhibit unipolar switching property. For uni-polar switching a narrow pulse caused the resistance to increase while a wider pulse having the same polarity reduces the resistance of the devices. We studied the temperature dependent on resistance, charge transport property, frequency dependent of RRAM impedance, resistivity distribution, and dynamic property of the memory resistor. The experimental data indicated the resistivity is reduced by high electric field. The data also clearly show that a narrow pulse caused an electron packet injection from cathode into the RRAM resistor. When the density of the non-equilibrium electron is larger then the certain value the resistivity near the cathode increases. The injected electron packet corrupts when the pulse width is much wider than the lifetime of the electron packet. Therefore, the RRAM resistance cannot be increased with wider pulse. This leads to the conclusion that the high resistivity is due to the reduction of free valence electron density caused by the high density of non-equilibrium electrons, the well known Jahn-Teller effect. A large non-equilibrium electron density may also be induced at the virtual cathode when the space-charge limited current (SCLC) flow occurs in the RRAM resistor. This also increases the resistivity at the virtual cathode region. Since the charge packet at the virtual cathode of a SCLC flow does not corrupt with time the resistivity can be increased statically via the SCLC flow process.
10:00 AM - I4.2
Direct Observation of Conducting Filament of a Few Nanometer Sizes in NiO Thin Film by Conducting Atomic Force Microscopy Under High Vacuum Condition.
Sejin Kim 1 , Jung-Bin Yun 1 , Changdeuck Bae 1 , Sunae Seo 2 , Myoung-Jae Lee 2 , Dong-Chul Kim 2 , Seung-Eon Ahn 2 , In-Kyeong Yoo 2 , Hyunjung Shin 1
1 School of Advanced Materials Engineering, Kookmin University, Seoul Korea (the Republic of), 2 Semiconductor Device & Material Lab., Samsung Advanced Institute of Tech., Seoul Korea (the Republic of)
Show Abstract10:30 AM - I4.4
Electrode Influence on the Resistive Switching at SrRuO3/Cr-doped SrZrO3/metal Junctions.
Hwan-Soo Lee 1 , Sukwon Choi 2 , Paul Salvador 2 , James Bain 1
1 Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States, 2 Materials Science and Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States
Show Abstract10:45 AM - I4.5
Nonvolatile Resistive Switching Devices Based on Nanoscale Metal/Amorphous Silicon/Crystalline Silicon Junctions
Sung Hyun Jo 1 , Wei Lu 1
1 EECS, University of Michigan, Ann Arbor, Michigan, United States
Show AbstractConventional micron-scale Metal/a-Si/Metal based nonvolatile resistive switching devices have the advantages of high on/off resistance ratio, full CMOS compatibility, and only rely on simple fabrication processes and relatively inexpensive material. However, the high voltage forming process typically required in such devices lowers the device yield, and it is not clear whether a-Si based resistive switching devices can be scaled down to nanoscale. Here we report studies on nanoscale metal/a-Si/c-Si devices in which forming is better controlled by using a heavily doped substrate as the bottom contact material. Devices based on the metal/a-Si/c-Si structure retain all the benefits of conventional amorphous silicon based devices. The a-Si layer sandwiched between a metal layer and the crystalline silicon substrate can be switched reversibly between the high resistance state and the low resistance state by controlling the magnitude and the polarity of the applied voltage. a-Si was prepared by decomposition of silane (Si3H4) either by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) on a heavily doped p-type silicon substrate. Silver, gold and nickel were explored as the top metal electrode. The devices show improved on/off resistance ratio as the device size is scaled down. A device with 50×50 nm^2 active area exhibits similar on-current compared with a device with 30×30 um^2 active area, and 10^6 better on/off ratio, demonstrating excellent scaling capability. Unlike conventional micron-scale metal/a-Si/metal structures, metal/a-Si/c-Si structure does not require high voltage forming, and high device yield (>98%) can be readily obtained. The switching behavior can be further controlled to be either rectifying or non-rectifying such that at on-state the device can be modeled as either a resistor or a diode, adding functionalities at the circuit level. Very promising properties for nonvolatile memory applications were observed, including, on/off resistance ratio larger than 4 orders of magnitude, endurance cycle larger than 10^6, switching speed faster than 5 ns and retention time longer than 70 days without noticeable degradation of the stored data. Such nanoscale CMOS compatible resistive switching devices will be ideally suited as next generation, high-density non-volatile memory devices, and may be used in logic operations based on the cross-bar architecture.
11:00 AM - I4: RRAM I
BREAK
12:00 PM - I4.7
Coexistence of Bipolar and Unipolar Resistive Switching Behavior in a Pt/TiO2/Pt Thin Film Stack.
Doo Seok Jeong 1 , Herbert Schroeder 1
1 Institute of solid state research, Research center Juelich, Juelich, NRW, Germany
Show Abstract12:15 PM - I4.8
New Nonvolatile Memory Effect Showing Reproducible Large Resistance Ratio Employing Nano-gap Gold Junction.
Yasuhisa Naitoh 1 2 , Masayo Horikawa 1 , Tetsuo Shimizu 1
1 NRI, AIST, Tsukuba Japan, 2 , PRESTO-JST, Kawaguchi Japan
Show Abstract Recent research reports have described resistance switches using nanoscale spaces. Most switches are composed of organic molecules possessing a switching effect sandwiched between two metal electrodes, which consist of a great variety of materials, for example, conductive organic wires, carbon nanotubes, or amorphous carbon. Also, K. Terabe et al. have reported atomic switches that employ solid-state electrochemical reactions between Pt electrodes and AgS or CuS. (Terabe et al., Nature, (2005) 433, 47-50.) These atomic switches employ absolutely no physical charge, such as electric charge or magnetization, and therefore they appear to be the ultimately small resistance switches. With the exception of magnetic random access memory, the miniaturization of memory devices generally results in an improvement of the switching speed and operation power, but the lifetime for maintaining the signals tends to shorten. The long lifetime of an atomic switch is maintained even when the device is miniaturized, because there is no diffusion of physical charges. This atomic switch technology will be the basis to realize nonvolatile memory devices for the next generation.In this study, we observed a reversible resistance switching effect in a structure composed of metal electrodes separated by about a 10 nm gap. (Y. Naitoh et al, Nanotechnology (2006) in press.)The structure of the device shown here is relatively simple, requiring no molecules having complicated structures or special combinations of materials, but just simply consisting of Au electrodes on a SiO2-coated Si substrate. A large negative resistance is observed in the I-V characteristics of this junction when high-bias voltages are applied. This phenomenon is characteristic behaviour on the nanometre scale. Furthermore, this junction exhibits a non-volatile resistance hysteresis when the bias voltage is reduced very rapidly from a high level to around 0 V, and when the bias voltage is reduced slowly. The high and low resistance conditions were performed by the rapid and slow reductions of applied bias voltages, respectively. The maximum resistance ratio between high and low resistance was over six orders of magnitude.This study is the first to describe a reversible resistance switching effect occurring across a nanogap between metal electrodes. It has been shown that this effect is peculiar to gaps on the nanometre scale, dependent on the gap width, and that its mechanism is speculated by the reversible migration of gold atoms. The resistance switching ratio can be adjusted by controlling the applied voltage, where it can tolerate over 1,000 cycles. Due to the simplicity of the construction of this device, it appears that this device has great potential for future application in nonvolatile memory and other information storage devices.
12:30 PM - I4.9
Nonvolatile Memory Effects of Ti Oxide Thin Films by a Plasma-enhanced Atomic Layer Deposition.
Min Ki Ryu 1 , Hu Yonng Jeong 1 , Lee-Eun Yu 2 , Yang-Kyu Choi 2 , Sung-Yool Choi 1
1 Nano-Bio-Electronic Devices Team, ETRI, Daejeon Korea (the Republic of), 2 Dept. of Electrical Engineering and Computer Science, KAIST, Daejeon Korea (the Republic of)
Show AbstractI5: Resistive Switching Non-volatile Memories II
Session Chairs
Wednesday PM, April 11, 2007
Room 3006 (Moscone West)
2:30 PM - **I5.1
Memory Devices Based on Solid Electrolytes.
Michael Kozicki 1
1 Center for Applied Nanoionics, Arizona State University, Tempe, Arizona, United States
Show AbstractThe semiconductor industry has acknowledged that it faces ever-increasing difficulty in attaining the goals set forth in the International Technology Roadmap for Semiconductors. The Roadmap states that the problems associated with physical and operational scaling are particularly acute for solid state memory, where current mainstream charge storage technologies have a very doubtful existence in anything like their current form as we move beyond the 32 nm node. The scaling quandary has led to an avalanche of alternative memory technologies and particularly of those that rely on resistance change mechanisms. A wide variety of efforts has been highlighted in the technical press but even though investment has been significant in the most promising cases, no new technology has been universally adopted by the industry, mostly due to non-scalable operational characteristics. This has kept the door open for new contenders. One such new technology is resistance change memory based on solid electrolytes. A number of semiconductor companies and research institutions are developing resistance change devices that utilize a variety of solid electrolytes and mobile ions. The lowering of the resistance is attained by the reduction of ions in the relatively high resistivity electrolyte to form a conducting bridge between the electrodes. The resistance is returned to the high value via the application of a reverse bias (or in some cases a high-current forward bias) that results in the breaking of the metallic filament. Our own variant, Programmable Metallization Cell (PMC), uses deposited thin films of copper- or silver-doped germanium sulfide, germanium selenide, tungsten oxide, or silicon oxide between two electrodes; Cu or Ag is used as an oxidizable electrode on the electrolyte and the lower electrode can be the W via plug in a standard CMOS process. Switching is attainable within a few tens of nanoseconds for voltages of a few hundred mV and currents in the μA range. In addition to possessing the endurance, retention, and CMOS compatibility required of future memory and storage elements, solid electrolyte devices have excellent scaling prospects due to their low operational energy and demonstrated physical scalability to below 20 nm. This presentation will review the state-of-the-art in solid electrolyte resistance-change memory devices and will discuss how the process/thermal stability and electrical characteristics of the most promising variants depend on the unique nanostructure of the ion-containing films and the nanoscale electrodeposits that form within them.
3:00 PM - I5.2
Resistance Switching In Ferroelectric Materials.
Tingkai Li 1 , Sheng Teng Hsu 1
1 , Sharp Labs of America, Inc., Camas, Washington, United States
Show AbstractA ferroelectric crystal with perovskite structure such as PbZr1-xTixO3 (PZT), SrBi2Ta2O9 (SBT), Bi3La1-xTixO12 (BLT) and non-perovskite structure such as Pb3Ge5O11 (PGO) have two polarization states, which can generate two resistance states, which are high resistance and low resistance states. These properties can be used for resistance random access memory applications (RRAM). When a ferroelectric capacitor is polarized an internal electric field opposite polarity to the external applied field is generated. As a result there is a large resistance change at a given bias voltage between the two polarization states of the capacitor. It is the purpose of this paper to show that the ferroelectric capacitor may be used as a current memory cell of non-destructive readout (NDRO) non-volatile Random Access Memory array. It will also be shown that each current sensing ferroelectric memory cell stores two bits of memory information and exhibits long memory retention and excellent endurance properties.
3:15 PM - I5.3
Electric Pulse Induced Programmable Resistance Change in Oxide Films
Alex Ignatiev 1 , Naijuan Wu 1 , Xin Chen 1 , Yibo Nian 1 , Christina Papagianni 1 , John Strozier 1
1 Center for Advanced Materials, University of Houston, Houston, Texas, United States
Show AbstractRecent research on the electric-pulse-induced resistance (EPIR) switching effect in manganite oxide devices is being reviewed. The EPIR effect encompasses the reversible change of resistance of a thin oxide film such as Pr1-xCaxMnO3 (PCMO) under the application of short, low voltage pulses. Positive voltage pulses of < 4V can switch the resistance of the thin film oxide device from a high resistive state into a low resistive state, and negative voltage pulses can return the system back to the high state in times shorter than ~10ns. A resistance change of more than two orders of magnitude has been obtained for samples pulsed at 3 to 4V, in an operating temperature range of 23 oC to 100 oC. It has been shown that the resistance change is non-volatile with retention times >108sec. Moderate fatigue is exhibited by the effect, however, this seems to depend on film processing parameters. Two groups of EPIR devices have been investigated: one with the PCMO layer sandwiched between a top and a bottom electrode; the other with both electrodes on top of the PCMO thin films, which were grown on insulating substrates. I-V switching characteristics, electric pulse switching hysteresis, as well as the dynamic resistance during nanosecond switching pulses of the EPIR devices were measured in the delimitation of the physical basis for the EPIR effect. Scanning Kelvin Probe and Current (I) AFM measurements have shown resistance switching over extended regions from the metal electrode-oxide film interface, with data pointing to enhanced and reversible diffusion of oxygen ions (vacancies) in these extended regions under pulsing conditions. The device performance indicates that a two–state non-volatile resistance random access memory (RRAM) can be realized based on this EPIR effect. This would present the possibility of a new nonvolatile, high density, fast write/read, and low power-consumption memory system.
3:30 PM - I5.4
Scanning Resistive Probe Microscopy: A New Electric Field Sensor as R/W Head for Non-volatile Storage Devices.
Kyunghee Ryu 1 , Hyunjung Shin 1 , Hyoungsoo Ko 2 , Seungbum Hong 2 , Chulmin Park 2 , Yongkwan Kim 2 , Sung-Hoon Choa 2 , Ho Nyung Lee 3
1 School of Advanced Materials Engineering, Kookmin University, Seoul Korea (the Republic of), 2 Semiconductor Device and Material Lab, Samsung Advanced Institute of Technology, Kyunggi-do Korea (the Republic of), 3 Condensed Matter Sciences Division, Oak Ridge National Laboratory, Oak Ridge, Tennessee, United States
Show Abstract3:45 PM - I5.5
Femtosecond Laser Structuring of As2S3 Glass for Erasable and Permanent Optical Memory.
Andrei Rode 1 , Saulius Juodkazis 2 , Toshiaki Kondo 2 , Hiroaki Misawa 2 , Eugene Gamaly 1 , Marek Samoc 1 , Barry Luther-Davies 1
1 Laser Physics Centre, RSPhysSE, The Australian National University, Canberra, Australian Capital Territory, Australia, 2 Nanotechnology Center, Hokkaido University, Sapporo Japan
Show Abstract4:00 PM - I5: RRAM II
BREAK
I6: Ferroelectric Non-volatile Memories I
Session Chairs
Wednesday PM, April 11, 2007
Room 3006 (Moscone West)
4:30 PM - **I6.1
ITO-Channel Ferroelectric-Gate Thin Film Transistor with Large On/off Current Ratio.
Eisuke Tokumitsu 1 , Tomofumi Fujimura 1 , Takashi Sato 1
1 Precision and Intelligence Lab, Tokyo Institute of Technology, Yokohama Japan
Show Abstract5:00 PM - I6.2
No Interfacial Layer for PEDOT Electrodes on PVDF:Characterization of Reactions at the Interface P(VDF/TrFE)/Al and P(VDF/TrFE)/PEDOT:PSS.
Klaus Mueller 1 , Dipanka Mandal 1 , Dieter Schmeisser 1
1 , BTU Cottbus, Cottbus Germany
Show Abstract5:15 PM - I6.3
Large Ferroelectricity of Thin Poly (vinylidene fluoride-trifluoroethylene) Copolymer Films Suitable for Non-Volatile Memory Applications
Sumiko Fujisaki 1 , Yoshihisa Fujisaki 2 , Hiroshi Ishiwara 1
1 Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama Japan, 2 Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo, Japan
Show Abstract Organic ferroelectrics such as Poly vinylidene fluoride (PVDF) are promising material for next generation ferroelectric random access memories (FeRAMs) due to lower processing temperatures. PVDF was the first found organic material that exhibited significant piezoelectric and ferroelectric properties [1]. The challenges to make ferroelectric non-volatile memories with PVDF related materials had begun in 1990s but most of the activities faced with a serious problem in reducing operating voltages. There are two reasons that make the operating voltages great; one is the thickness of the ferroelectric films, and the other one is large coercive field (Ec). In most cases, thickness of films was greater than several hundred nanometers and Ec was larger than 400 kV/cm. In this paper, we tried to reduce the film thickness by introducing trifluoroethylen (TrFE). We optimized the composition of VDF and TrFE first, and then we investigated the dependence of ferroelectricity on the crystallization condition. We prepared P(VDF-TrFE) (Poly vinylidene fluoride-trifluoroethylene) copolymer films with solvent cast process on Pt and Si substrates. Three compositions of VDF/TrFE = 77/23 mol%, 70/30 mol% and 57/43 mol% were tried. The deposited films were at first dried at 120 °C in air. The spin-coating and drying processes were repeated until the appropriate film thickness was obtained. The films were crystallized at temperatures around 140 °C. By optimizing the growth conditions, the maximum remanent polarization (Pr) of 8.6 µC/cm2 was obtained in a 60 nm-thick film. The coercive voltage and field of that ferroelectric capacitor were 1.5 V and 250 kV/cm, respectively. We also fabricated Au/100nm-P(VDF-TrFE)/TaO/Si MFIS (Metal Ferroelectric Insulator Semiconductor) structure. The memory window larger than 2.8 V was observed under the sweep bias of ± 4 V. These sophisticated ferroelectric properties are equivalent to those of oxide ferroelectrics and are much advanced compared to the previous reports on organic ferroelectrics.References[1] H. Kawai, Jpn. J. Appl. Phys., vol.8, pp.975-97 (1969).
5:30 PM - I6.4
Oxygen Bonding in Bismuth Layered Compounds SrBi2Ta2O9.
Dong Su 1 , Nan Jiang 1 , Jianguo Wen 2 , Jianshe Liu 3
1 Department of Physics, Arizona State Universtiy, Tempe, Arizona, United States, 2 Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, Illinois, United States, 3 Institute of Microelectronics, Tsinghua University, Beijing China
Show Abstract5:45 PM - I6.5
Dielectric Characteristics of Donor Doped Nonlead Ba(Cu1/3Nb2/3)O3 Perovskite Material Synthesized by Microwave-assisted Citrate-nitrate Sol-gel Route.
Alp Manavbasi 1 , Jeffrey LaCombe 1
1 Materials Science & Engineering, University of Nevada, Reno, Reno, Nevada, United States
Show AbstractI7: Poster Session: Resistive Switching and Ferroelectric Memories I
Session Chairs
Tingkai Li
Eisuke Tokumitsu
Thursday AM, April 12, 2007
Salon Level (Marriott)
9:00 PM - I7.1
Metal Organic Chemical Vapor Deposition of Titanium Dioxide Thin Films for Applications of Resistive Switching Characteristics.
Ying-Ching Zhang 1 , Yun-Shan Lo 1 , Tai-Bor Wu 1
1 Materials Science and Engineering, National Tsing-Hua University, Hsin-Chu Taiwan
Show AbstractThe resistive switching mechanism of TiO2 crystalline thin films grown on Pt/Ti substrate by MOCVD is studied by current-voltage measurement(sweep mode, HP4155). The anatase structure of TiO2 thin films is obtained at low temperature of 335∼375°C, which is useful for non-volatile memory device of industrial applications. The titanium dioxide(binary transition metal oxide)MIM structure is fabricated by sputtering Pt as top electrode of diameter 300μm at room temperature. The crystalline structure and surface uniformity of TiO2 thin films were investigated by x-ray diffraction(low angle XRD), field-emission scanning electron microscopy(FE-SEM), transmission electron microscopy(TEM)and x-ray photoelectron spectroscopy(XPS). Furthermore, the switching phenomenon shows a voltage-controlled N-shaped negative resistance characteristic consistent with the theory of conducting filamentary current composed of oxygen ions in the TiO2 thin film.
9:00 PM - I7.11
The Microstructure and C-V Characterization for Lanthanum-doped Bi4Ti3O12 Ferroelectric Memory Capacitors Based on MFS and MFIS Structures
Dan Xie 1 , Tianling Ren 1 , Litian Liu 1
1 , Institute of Microelectronics, Tsinghua University, Beijing China
Show Abstract9:00 PM - I7.12
Preferred Orientation Control and Electrical Properties of Sputtered BiFeO3 Thin Films.
Chia-Ching Lee 1 , JennMing Wu 1
1 , National Tsing Hwa Unervisty, Taiwan, R.O.C., Hsinchu Taiwan
Show Abstract9:00 PM - I7.13
Reversible Multi-level Resistance Switching of Ag-La0.7Ca0.3MnO3-Pt Heterostructures.
Dashan Shang 1 2 , Lidong Chen 1 , Qun Wang 1 , Zihua Wu 1 , Wenqing Zhang 1 , Xiaomin Li 1
1 , Shanghai Institute of Ceramics, CAS, Shanghai China, 2 , Graduate School of Chinese Academy of Sciences, Beijing China
Show AbstractWednesday, April 11Transferred I4.3 @ 9:15 am to Poster I7.13Reversible Multi-level Resistance Switching of Ag-La0.7Ca0.3MnO3-Pt Heterostructures. Dashan Shang
9:00 PM - I7.14
Optical, Structural and Surface Properties of Silicon Dioxide Films Doped with Terbium.
Zhe Feng 1 , S. Lien 1 , C. Huang 1 , L. Cheng 1 , P. Huang 1 , Ting Li 2
1 Electrical Engineering, National Taiwan University , Taipei Taiwan, 2 , Sharp Labs of America, Inc., Camas, Washington, United States
Show AbstractWednesday, April 11Transferred I4.10 @ 11:45 am to Poster I7.14Optical, Structural and Surface Properties of Silicon Dioxide Films Doped with Terbium. Zhe Chuan Feng
9:00 PM - I7.3
Effects of SrRuO3 Buffer Layers in Enhancing Resistance Change of Ag/Pr0.7Ca0.3MnO3/Pt Heterostructure.
Seungwoo Han 1 , Junghyun Sok 1 , Kyungwan Park 1 , Wanshik Hong 1 , Sanghyun Joo 1 , Yunsun Park 2
1 Department of Nano Science and Technologies, Univ. of Seoul, Seoul, Seoul, Korea (the Republic of), 2 Department of Industrial and Systems Engineering, Myongji university, Yong-in, kyunggi-do, Korea (the Republic of)
Show Abstract9:00 PM - I7.4
HfOx Thin Films for Resistive Memory Device by Use of Atomic Layer Deposition.
Pang Shiu Chen 1 , Heng-Yuan Lee 2 , Ching-Chiun Wang 2 , Ming-Jinn Tsai 2 , Kou Chen Liu 3
1 Materials Science and Engineering, MingShin University of Science and Technology, Hsin Chu Taiwan, 2 Electronics and Optoelectronics Research Laboratory, Industrial Technology Research Institute, HsinChu Taiwan, 3 Graduate Institute of Electro-Optical Engineering, Chang Gung University, Taoyuan Taiwan
Show Abstract9:00 PM - I7.5
Characteristics of (Pr,Ca)MnO3 Thin Films on LaNiO3-electrodized Si Substrate for Nonvolatile Resistance Random Access Memory(RRAM) Application
Cheng-Wei Wu 1 , Wen-Yuan Chang 1 , Tai-Bor Wu 1
1 , National Tsing-Hua University, Hsinchu Taiwan
Show Abstract