Tingkai Li Sharp Laboratories of America, Inc.
Joan Redwing The Pennsylvania State University
Michael Mastro U. S. Naval Research Laboratory
Edwin L. Piner Nitronex Corporation
Armin Dadgar Otto-von-Guericke-Universitaet Magdeburg
and AZZURRO Semiconductors AG
C1: III-Vs on Si: Layer Transfer and Bonding Approaches
Tuesday PM, March 25, 2008
Room 2003 (Moscone West)
9:30 AM - **C1.1
Formation Of III-V Semiconductor Engineered Substrates Using Smart CutTM Layer Transfer Technology.
Fabrice Letertre 1 Show Abstract
1 , Soitec S.A., Bernin France
Engineered substrates are expected to play a dominant role in the field of modern nano-electronic and optoelectronic technologies. For example, engineered substrates like SOI (Silicon On Insulator) make possible efficient optimization of transistors’ current drive while minimizing the leakage and reducing parasitic elements, thus enhancing the overall IC performance in terms of speed or power consumption. Other generations of engineered substrates like strained SOI (sSOI) provide solutions to traditional scaling for 32 nm node and beyond  technologies. The Smart CutTM technology, introduced in the mid 1990’s by M. Bruel  is a revolutionnary and powerful thin film technology for bringing to industrial maturity engineered substrate solutions. It is a combination of wafer bonding and layer transfer via the use of ion implantation. It allows multiple high quality transfers of thin layers, from a single crystal donor wafer onto another substrate of a different nature, allowing the integration of dissimilar materials. As a consequence, it opens the path to the formation of III-V based engineered substrates by integrating, for example, materials like GaAs , InP , SiC , GaN , Germanium  ,and Si [8 ]on a silicon, poly SiC, sapphire, ceramic, or metal substrates..In this paper, we will review the current wafer bonding and layer transfer technologies with a special emphasis on the Smart Cut technology applied to compound semiconductors. Beyond SOI, the innovation provided by substrate engineering will be illustrated by the case of Silicon and SiC engineered substrate serving as a platform for GaN and related alloys processing [9,10,11,12] as well as the case of Germanium/Si platform for the growth of GaAs/InP materials, opening the path to Si CMOS and III-V microelectronics/ optoelectronics functions hybrid integration [13, 14]. Recent results obtained in these two focused areas will be presented to emphasize the added functionalities offered by engineered substrates. B. Ghyselen et al., ICSI3 proc., 173 5 (2003) M. Bruel et al., Electron. Lett., vol 31, p. 1201 (1995) E. Jalaguier et al., Electron. Lett., 34(4), 408 (1998) E. Jalaguier et al. Proc. llth Intern. Conf. on InP and Related Materials, Davos, Switzerland, (1999) L. Di Cioccio et al., Mat. Sci. and Eng. B Vol. 46, p. 349 (1997) A. Tauzin and al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 119-127 F. Letertre, et al. MRS Symp. Proc., 809, B4.4 (2004). B. Faure et al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 106-118 H. Larèche et al., Mat. Sci. For., Vols. 457–460 pp.. 1621 – 1624 (2004) G. Meneghesso et al , IEDM 2007, to be published  Y. Dikme et al., Journal of Crystal Growth, v.272 (1-4), pp. 500-505 (2004) J. Dorsaz and al., Proceedings, ICNS6 (2005) S.G. Thomas et al., IEEE EDL Vol. 26, July 2005. K. Chilukuri, Semi. Sci. Technol. 22 (2007) 29-34
10:00 AM - C1.2
GaInP/GaAs Dual Junction Solar Cells on Ge/Si Epitaxial Templates.
Melissa Archer 1 , Daniel Law 2 , Shoghig Mesropian 2 , Andreea Boca 2 , Moran Haddad 2 , Richard King 2 , Harry Atwater 1 Show Abstract
1 , California Institute of Technology, Pasadena, California, United States, 2 , Spectrolab Engineering, Inc., Sylmar, California, United States
Future ultrahigh efficiency multijunction solar cells will employ designs that feature three or four or more subcells utilizing lattice-mismatched structures to achieve an optimal bandgap sequence for solar energy conversion. While lattice-mismatched multijunction cells have been fabricated recently using metamorphic growth approaches, use of direct wafer bonding techniques to enable lattice mismatch accommodation at the subcell interfaces allows considerably more design freedom and inherently higher quality, defect-free active regions. We are investigating GaInP/GaAs/InGaAsP/InGaAs/InP/Si four junction cell designs that employ wafer bonding and layer transfer as critical aspects of the cell fabrication process. We will present results from synthesis of large area (>2cm2) crack-free GaInP/GaAs double junction solar cells on Ge/Si templates fabricated using wafer bonding and ion implantation induced layer transfer techniques. Following layer transfer, the surface of the ~500 nm thick transferred Ge (100) has an as-transferred RMS roughness of ~20 nm and a near surface layer containing a high density of ion implantation-induced defects. The RMS roughness has been reduced by wet etching to ~1-5 nm after removing ~500 nm; whereas with chemical mechanical polishing, it can be reduced to <1 nm. Preliminary cells grown on wet etched surfaces showed about 10 absolute percent lower quantum efficiency than the control device grown on a bulk Ge wafer. The surface preparation dominates the performance of these devices, not the coefficient of thermal expansion (CTE) mismatch induced strain. Cells grown on templates prepared with chemical mechanical polishing in addition to the wet etch show comparable performance to control devices grown on bulk Ge substrates. From light current-voltage (I-V) data, the short circuit current is comparable, but the open circuit voltage is slightly lower (2.08V vs. 2.16V). From spectral response measurements, we can see that this drop in open circuit voltage is due to a slight shift of the band gap in the top GaInP cell. The control cells exhibited a conversion efficiency of 28%, whereas the cells grown on Ge/Si templates were 24.8% efficient. In addition, we will discuss the effects of changing the strain state of the template substrate on the performance of the devices by comparing devices grown on Ge/Si and Ge/Sapphire. The CTE mismatch between Si and GaAs/GaInP materials induces a tensile strain, whereas the sapphire substrate induces a compressive strain. Wafer bow and XRD data will be presented to quantify the strain state of each of the epitaxial templates.
10:15 AM - C1.3
High Crystalline-quality III-V Layer Transfer onto Si.
Peng Chen 1 , Yi Jing 1 , S. Lau 1 , Dapeng Xu 2 , Luke Mawst 2 , T. Alford 3 , Charles Paulson 4 , T. Kuech 4 Show Abstract
1 ECE, University of California, San Diego, La Jolla, California, United States, 2 Electrical and Computer Engineering Department, University of Wisconsin, Madison, Wisconsin, Madison, Wisconsin, United States, 3 School of Materials, Arizona State University, Tempe, Arizona, United States, 4 Department of Chemical and Biological Engineering, University of Wisconsin, Madison, Madison, Wisconsin, United States
A novel approach of combining ion-cutting and selective chemical etching for the transfer of high crystalline-quality III-V layers on SiO2/Si substrate is presented. This layer transfer scheme takes advantage of ion-cutting by conservation of the III-V substrate for reuse, and simultaneously improving the transferred layer quality and surface condition without the chemical and mechanical polishing (CMP). The relocation of the ion-implantation damage maximum enables the transfer of a relatively defect-free InP-based layer onto a Si substrate coated with an oxide layer and results in structures ready for further optoelectronic device fabrications or further epitaxial growth.
10:30 AM - C1.4
Patterned Exfoliation of GaAs Based on Masked Light Ion Implantation.
Hyung-Joo Woo 1 , Han-Woo Choi 1 , Gi-Dong Kim 1 , Wan Hong 1 , Joon-Kon Kim 1 Show Abstract
1 , Korea Institute of Geoscience & Mineral Resources, Daejeon Korea (the Republic of)
While blistering is preferred on annealing the 80 keV hydrogen ion implanted GaAs in a fluence range of 1.0 ~ 2.0 x 1017 H+/cm2 at an elevated temperature window of 120 ~ 160 C, a momentary avalanche type exfoliation is found in the GaAs wafer implanted with 100 keV helium ions in the fluence higher than 2 x 1016 He+/cm2 at room temperature and subsequently annealed in the temperature range of 200 ~ 300 C. Based on the preliminary study on the surface morphological changes with light ions, patterned exfoliation of single crystal GaAs has been tried with 200 keV He implantation in a fluence of 3 x 1016 He+/cm2 at room temperature and 600 keV H implantation in a fluence range of 1.0 ~ 1.5 x 1017 H+/cm2 at room temperature or 140 C through Ni mesh (40 μm opening) or stainless steel wire (50 μm in diameter) masks, followed by thermal annealing at 250 ~ 500 C. The influence of ion species, ion fluence, implantation temperature, subsequent annealing and mask pattern on the patterned exfoliation was studied by Normarski optical microscopy and field emission secondary electron microscopy. In case of H implantation, while no surface morphological change could be found with a room temperature implantation followed by high temperature annealing up to 500 C at an extended period of several hours, the high temperature implantation in a predetermined temperature window with lower energy hydrogen implantation was found to be also indispensable for the effective exfoliation of GaAs from the exposed area with thermal annealing. In case of He implantation, large area exfoliation could be demonstrated for the room temperature implanted GaAs samples and a notable dependency of the exfoliated depth on the fluence was found. As pattern size decreases, the time required for the complete exfoliation of the exposed area considerably increases as more surface energy is needed to shear the GaAs layer at the border line and the sharpness of the exfoliated border line markedly decreases.
10:45 AM - C1.5
``III-V-in-Si" as Opposed to III-V-on-Si as an Alternative Route to Light Harvesting in Si.
Kiyoshi Kawamoto 1 , Susumu Fukatsu 1 2 Show Abstract
1 , University of Tokyo, Tokyo Japan, 2 , Japan Science and Technology Agency (JST), Saitama Japan
11:30 AM - **C1.6
Transistor Level Integration of Compound Semiconductor Devices and CMOS - CoSMOS.
Kenneth Elliott 1 Show Abstract
1 , HRL Laboratories, LLC., Malibu, CA, California, United States
HRL is developing new methods to tightly integrate compound semiconductor technologies within state-of-the-art silicon CMOS circuits in order to achieve unprecedented circuit performance levels. Under the DARPA COSMOS program, HRL Laboratories, LLC, will be developing technology for the intimate integration of CMOS devices with 400 GHz InP HBTs to form complex integrated circuits. This research will investigate innovative approaches to the transistor-scale integration of compound semiconductor and silicon-based transistors so as to enable revolutionary advances in science, devices, circuits, and systems. Currently, heterogeneous integration of III-V devices with silicon can be achieved using multi-chip modules and similar large-scale assemblies. While adequate for relatively low performance applications, the integration complexity and performance that can be achieved in this manner is limited. The COSMOS technology will drive the size and integration scale down to that of individual transistors. The approach will be based on aligned die bonding of semiconductor materials and devices onto partially processed Si to offer outstanding overlay accuracy, while solving thermal expansion and stress issues, and maximizing connectivity between CMOS and InP transistors. This approach will provide scalability as feature sizes shrink to sub-100 nm and permit rapid technology readiness for integration of emerging technologies. The approach will also solve issues that have limited transistor level integration including: -Degradation in material quality -Limitation to a single material -Wafer size incompatibility -Poor overlay accuracy (microns vs. nanometers) -Low yield for complex ICs -Ability to use of Si design cell libraries and design infrastructure HRL researchers have previously demonstrated essential elements of a single flip process and will be implementing a “double flip” process to eliminate the need for the device material development required to grow layers upside-down with a “single flip” process. The ultimate objective is to bond processed transistors with overlay accuracy commensurate with modern IC interconnect processes. These methods are expected to be extendible to optical components and devices based on other materials like GaN while providing a straightforward extension of the Si roadmap to advanced heterogeneous system-on-a-chip (SoC) designs. By integrating disparate technologies like CMOS and InP, dramatic improvement in linearity (30 dB), dynamic range and bandwidth (> 500 MHz) of mixed-signal circuits such as digital-to-analog and analog-to-digital converters is expected. Elimination of power consuming components and reduction in supply voltage will also enable tremendous power savings (10X) at high frequencies.
12:00 PM - C1.7
GaAs-Si Hybrid Quantum Cascade Lasers.
Daniela Andrijasevic 1 , Maximilian Austerer 1 , Max Andrews 1 , Pavel Klang 1 , Werner Schrenk 1 , Gottfried Strasser 1 2 Show Abstract
1 ZMNS, Vienna University of Technology, Vienna Austria, 2 University at Buffalo, The State University of New York, Buffalo, New York, United States
The integration of Si- and III-V based devices into single chips has recently been investigated extensively. In particular this will enable further development of information and communication technologies due to integration of infrared optoelectronic devices with well established Si technology. We propose the integration of Si and GaAs quantum cascade lasers (QCL) by Au-Au thermo-compression (TC) bonding. Titanium/gold layers were used as an intermediate cohesion layer between the GaAs laser chip and the Si substrate. The III-V heterostructure was bonded epilayer down onto the patterned Si substrate. The laser material was grown on n-type GaAs by solid source MBE and consists of a GaAs/Al0.45Ga0.55As bound-to-continuum active region embedded in a double-AlGaAs waveguide.Standard 4” Si wafers, p-type doped with Boron (resistivity 1-20 Ohmcm), with a total thickness of 525 µm were used. For electrical insulation a 1 µm thick layer of thermal oxide was grown on the silicon.The hybrid laser chip operates both at cryogenic as well as at room temperatures, emitting around 12 µm wavelength. The performance of the hybrid laser in low-duty-cycle pulsed operation was not compromised when compared to a standard epi-up mounting. The threshold current density of the lasers at liquid-nitrogen temperature is 4.5 kA/cm2, the same as for the chips with standard processing.Due to the fact that gold has the lowest thermal resistivity (0.31 cmK/W @ room temperature) of all metals and alloys used typically for epi-down mounting, heat extraction from the active region of the laser is increased. Furthermore due to the epi-down approach, there is no need for extended contacts on the III-V chip, thus decreasing the number of lithographic steps necessary and making it easier to contact very narrow ridges (< 5µm). Lossy insulation layers on the sidewalls of the ridge waveguides are not necessary anymore. In our future work we will study the benefits of hybrid QCL technology with respect to the integration of SOI waveguides, microfluidic structures and mid-infrared fibre coupling schemes. We will also investigate the improved heat management under high-duty cycle quasi-cw operation of the laser.
12:15 PM - C1.8
Investigation of Blistering Phenomena in Hydrogen-Implanted GaN and AlN for Thin Film Layer Transfer Applications.
Rajendra Singh 1 , Roland Scholz 2 , Silke Christiansen 2 , Goesele Ulrich 2 Show Abstract
1 Department of Physics, Indian Institute of Technology Delhi, New Delhi India, 2 , Max Planck Institute of Microstructure Physics, Halle Germany
Hydrogen implantation-induced layer splitting in conjunction with direct wafer bonding is a promising method for transferring high structural quality thin films of compound semiconductors from bulk substrates onto cheaper foreign substrates such as Si and sapphire. For this process to occur successfully for a particular semiconductor, one has to first understand the hydrogen implantation-induced blistering process for that semiconductor. In this report we have investigated the blistering phenomena in hydrogen implanted GaN and AlN for potential thin film layer transfer applications. GaN and AlN were implanted with 100 keV H2+ ions with various fluences in the range of 5E16 to 2.5E17 cm-2. After implantation the samples were annealed at higher temperatures up to 800°C in order to observe the formation of surface blisters. In the case of GaN only those samples that were implanted with a fluence of 1.3x1017 cm-2 or higher showed surface blistering after post-implantation annealing. The cross-sectional transmission electron microscopic images of the implanted region in GaN showed the formation of nanovoids that served as precursors for the formation microcracks in the damaged region. The formation of microcracks has also been clearly observed in high quality free-standing GaN samples implanted with a dose of 1.3x1017 cm-2. Moreover, the microcrack formation has been observed in both Ga-face and N-face free-standing GaN.In the case of AlN, the samples those were implanted with a dose of 2.0x1017 cm-2 or higher exhibited blistered surfaces in the as-implanted state. Systematic investigation of the blistering phenomenon in AlN implanted with a dose of 1.5x1017 cm-2 and subjected to post-implantation annealing at various temperatures was carried out. The blistering kinetics revealed two different activation energies for the formation of blisters: 0.44 eV in the higher temperature regime and 1.16 eV in the lower temperature regime. Large area microcracks, as revealed in the XTEM images, were clearly observed in the case of implanted and annealed AlN samples. These microcracks due to the overpressure of H2 at higher annealing temperatures ultimately lead to the formation of surface blisters. A comparison of the H-implantation induced blistering in GaN and AlN has also been presented. The present work has significant implications for the thin film layer transfer of GaN and AlN onto Si leading to the fabrication of novel engineered substrates for the epitaxial growth of nitride device layers.
12:30 PM - C1.9
Heterogeneous Integration of Wide Band Gap Materials.
Oussama Moutanabbir 1 , Roland Scholz 1 , Silke Christiansen 1 , Ulrich Goesele 1 , Martin Chicoine 2 , Reinhard Krause-Rehberg 3 , Yves Chabal 4 Show Abstract
1 , Max-Planck Institute of Microstructure Physics, Halle (Saale) Germany, 2 Département de Physique, Université de Montréal, Montréal, Quebec, Canada, 3 Physics, Martin-Luther-University , Halle (Saale) Germany, 4 Departments of Chemistry, Biomedical Engineering, and Physics, Rutgers University, Piscataway, New Jersey, United States
Heteroepitaxial growth of GaN on non-lattice-matched foreign substrates leads unavoidably to the formation of growth-related defects that occur to relax the strain. These growth-related threading dislocations significantly limit the quality of the grown GaN layers with undesirable impact on devices performance. Direct wafer bonding in combination with hydrogen ion-cutting is a promising strategy to integrate bulk quality thin layers onto various host materials achieving a wide variety of heterostructures frequently unattainable by epitaxy. In the first part of this presentation, we will address important issues in direct bonding of 2-inch free standing GaN (FS-GaN) wafers. The large bow of FS-GaN wafers, reaching 60 µm after implantation, presents a serious obstacle for successful bonding. Here, we present a novel method to manipulate and significantly reduce it. Based on this achievement we are exploring the transfer of thin films from FS-GaN wafer onto sapphire, silicon, and ZnO. Since these transferred GaN layers have bulk properties, these new materials are promising for low cost fabrication of GaN-based devices such as phosphorous-free white LEDs and high performance laser diodes. In the second part, the mechanistic picture of hydrogen-induced GaN splitting will be addressed. Intensive experimental studies have been performed in order to understand atomic processes leading to GaN thin film transfer. Thermoevolution and depth profiles of post-implantation nanovoids are investigated by positron annihilation spectroscopy. Displacement fields and strain build-up are quantified by using Rutherford backscattering spectrometry in channeling mode. Elastic recoil detection analysis has been employed to extract hydrogen distribution and its evolution during thermal annealing. The transition from nanovoids to microcracks and extended internal surfaces has been carefully studied by cross section transmission electron microscopy. Hydrogen-defect complexes involved have been identified using multiple internal transmission FTIR.
12:45 PM - C1.10
Bulk Gallium Nitride Growth on Hydrogen-Ion Implanted Silicon Substrate.
Bing-Jung Wu 1 , Teresia Suryasindhu 1 , Adios Hu 1 , T. -H. Lee 1 2 Show Abstract
1 Institute of Materials Science and Engineering, National Central University, Chung-Li City Taiwan, 2 National Central University, Inst. of Materials Science and Engineering, Chung-Li Taiwan
Tingkai Li Sharp Laboratories of America, Inc.
Joan Redwing The Pennsylvania State University
Michael Mastro U. S. Naval Research Laboratory
Edwin L. Piner Nitronex Corporation
Armin Dadgar Otto-von-Guericke-Universitaet Magdeburg
and AZZURRO Semiconductors AG
C4: GaN Electronic Devices and Sensors on Si
Wednesday AM, March 26, 2008
Room 2003 (Moscone West)
9:30 AM - **C4.1
GaN-on-Si HEMTs: From Device Technology to Product Insertion.
Wayne Johnson 1 , Sameer Singhal 1 , Allen Hanson 1 , Robert Therrien 1 , Apurva Chaudhari 1 , Walter Nagy 1 , Pradeep Rajagopal 1 , Quinn Martin 1 , Todd Nichols 1 , John Roberts 1 , Edwin Piner 1 , Isik Kizilyalli 1 , Kevin Linthicum 1 Show Abstract
1 , Nitronex Corporation, Durham, North Carolina, United States
In the last decade, GaN-on-Si has progressed from fundamental crystal growth studies to product realization and reliability demonstration. GaN-on-Si HEMTs addressing cellular, WiMAX, and broadband RF applications are now commercially available and offer GaN performance attributes in a cost-competitive platform. This presentation will briefly describe the underlying GaN-on-Si material, process, and packaging technology, then focus primarily on performance of these products in both commercial and military applications.All Nitronex NRF1 GaN-on-Si products are grown by MOCVD on 100 mm float-zone Si (111) substrates. A proprietary, strain-compensating (Al,Ga)N transition layer and an amorphous SixAl(1-x)Ny nucleation layer are employed to accommodate lattice and thermal expansion mismatch between the substrate and the epilayers. The wafer fabrication process employs Ti/Al-based ohmic contacts, ion implant device isolation, 0.5 um dielectrically-defined gates, gold airbridge interconnects, and through-wafer source vias. Typical inline DC parametrics include 2DEG sheet resistance of 490 ohms/sq., on-resistance of 3 ohm-mm, peak drain current density of 790 mA/mm, and breakdown voltage of >100V. Packaging solutions include traditional LDMOS-style air cavity outlines with thermally-enhanced flange materials and low-cost plastic SOIC.A family of devices addressing emerging OFDM-based applications such as WiMAX has been developed. WiMAX amplifiers require several watts of linear output power with frequency band allocations ranging from 2.3 to 5.8 GHz and instantaneous bandwidth up to ~15%. Translated to the transistor level, this implies simultaneous high frequency and high voltage capability – attributes well-suited to the inherent advantages of GaN-based devices. The flagship product in this family is NPT25100, delivering 125W of peak envelope power at 2.5 GHz. Under 2.5 GHz single-carrier OFDM modulation and 10 MHz channel bandwidth, this device produces 10W linear power at 2.0% EVM with 16.5dB associated gain and 26% drain efficiency. The excellent bandwidth of NRF1 devices enables the same device to operate at cellular frequencies from 2.11 - 2.17 GHz, producing >20W average power at an adjacent channel power ratio of -35 dBc.Primary military insertion opportunities include communications (e.g., JTRS - Joint Tactical Radio System) and electronic warfare (e.g., jammers). For EW applications, broadband operation reduces system-level component count and decreases weight / footprint. A family of 48V GaN-on-Si broadband HEMTs has been developed to deliver power levels from 40W - 180W in a compact package. In the highest power case, a new figure-of-merit “power density” (defined as peak output power divided by package volume) reaches ~600 W/cm3. These power levels – in an outline suitable for highly portable systems – enable improved communications transmit distance and extend the umbrella size of electronic protection units.
10:00 AM - C4.2
Power Performance of AlGaN/GaN HEMT’s Grown on 6” Si Substrates.
Joff Derluyn 1 , Jo Das 1 , Kai Cheng 1 2 , Anne Lorenz 1 2 , Stefan Degroote 1 , Marianne Germain 1 , Staf Borghs 1 Show Abstract
1 NEXT III-V, IMEC, Leuven Belgium, 2 ESAT, KUL, Leuven Belgium
AlGaN/GaN HEMT’s were grown on 6“ Si <111> substrates and passivated using IMEC’s in-situ SiN technique. The epitaxial growth was optimized to minimize RF losses due to the substrate-nitride interface while at the same time maintaining high buffer resistivity and low trap density. To assess RF losses of the epitaxial layer structure, coplanar waveguides were defined on places of the wafer where the top in-situ SiN and AlGaN has been etched away. The attenuation of the RF signals on the coplanar waveguides remained below 0.3dB/mm for frequencies up to 6GHz. The processing of HEMT’s included mesa etching, the formation of TiAlMoAu ohmic contacts, 500nm long gates with source-connected field plates and an airbridge process. The gate fingers are 250µm wide, yielding a total gate periphery of 1.5mm for 6-finger devices and 5mm for the 20-finger version. The devices’ RF power performance was characterised on-wafer. To avoid damage to the RF-probes, active load-pull measurements were performed in pulsed mode with a 100µs period under 10% and 30% duty cycle respectively. As there was no difference between the performance using different duty cycles, we conclude that the channel temperature reaches steady-state in less than 10µs. The 6-finger devices were operated in deep class AB operation mode but showed clear self-biasing effects. The bias voltage was changed from 30V to 60V in 10V increments. Under 60V bias, the devices provide an output power density of 7.9W/mm at 2GHZ with a PAE of 46% and 6.3W/mm at 4GHz with a PAE of 41%. The output power scales linearly with the bias voltage ranging from 30V to 60V, showing that there is no drain lag in the devices. We attribute this to the efficient surface passivation with the in-situ Si3N4 as well as to high crystal quality and hence the low trap density of the buffer layers. At 2GHz, the linear and saturated power gain are 22dB and 16.4dB respectively. An interesting observation is that the maximum gate current, even at power density levels of 7.9W/mm, remains below 50µA/mm which should prove beneficial for reliability. The larger 20-finger devices of 5mm total gate periphery reach a maximum absolute output power of 20W at a bias of 40V which represents the limit of our on-wafer measurement system. These results prove that the use of large area Si substrates is the only viable route forward for AlGaN/GaN HEMT’s.
10:15 AM - C4.3
MOVPE Growth and Characterization of AlInN HFET Structures on Si(111).
Christoph Hums 1 , Aniko Gadanecz 1 , Carsten Baer 1 , Armin Dadgar 1 2 , Jürgen Bläsing 1 , Thomas Hempel 1 , Hartmut Witte 1 , Annette Diez 1 , Jürgen Christen 1 , Alois Krost 1 Show Abstract
1 , Otto-von-Guericke-Universität Magdeburg, Magdeburg Germany, 2 , AZZURRO Semiconductors, Magdeburg Germany
Conventional AlGaN / (AlN) / GaN n-channel HFETs have achieved carrier mobilities above μ = 1700 cm2/Vs at carrier concentrations around ns = 1*1013 cm-2 and are commercially available today. An alternative to AlGaN based HFETs are Al1-xInxN / GaN HFETs. At an indium concentration of 17% AlInN is lattice matched to GaN and an n-channel is formed at the AlInN / GaN interface due to the difference in spontaneous polarization. For pseudomorphic AlInN layers with In concentrations exceeding 30% the formation of a p-channel is predicted on GaN due to the piezoelectric properties of the alloy. In this work the influence of AlN and AlGaN spacer layers on the electrical properties of n-channel FET structures (indium content ≈ 17%) will be discussed. It is well known that the insertion of a thin AlN spacer improves the mobility of the carriers drastically due to reduction of interface roughness scattering. Various groups have reported an optimized layer thickness of the AlN spacer layer to be ≈ 1nm. We will demonstrate that by the insertion of an additional AlGaN spacer the electrical properties can be further improved in AlInN / GaN based HFET structures. For the realization of a p-channel FET based on an AlInN/GaN heterostructure growth of strained AlInN on GaN with an indium content exceeding 30% is necessary. There are three major challenges at high In-Al-ratios: Extremely different growth conditions for the binaries, the high lattice mismatch between GaN and AlInN and a theoretically predicted miscibility gap. We report on a detailed study of the growth conditions of Al1-xInxN in a wide compositional range (0.09 < x < 1). The samples have been characterized by HRXRD, AFM and FESEM measurements. The miscibility gap has been determined to be smaller than predicted by theoretical calculations: Single phased material has been grown up to 50% indium content. A phase diagram based on our experimental results will be displayed as well as a study of the critical layer thickness in a concentration range form 9 to 34%. A detailed discussion on the growth conditions will be given. The major parameter for the boost of indium incorporation into the alloy is the growth temperature. With decreasing temperature the indium content increases linearly. A lower limit for the growth temperature has been found at 740°C since the formation of indium droplets and the reduced mobility of the Al-adatoms lead to three dimensional growth. The given V/Al-ratio primarily influences the growth rate of the alloy and does not have a strong influence on the alloy composition. To provide material with a good crystalline quality the layers have to be grown fully strained on GaN. If the critical layer thickness is exceeded and relaxation occurs, the sample morphology starts to deteriorate and three dimensional growth is observed.
10:30 AM - C4.4
Growth of AlGaN/GaN HEMTs on Silicon Substrates.
Fabrice Semond 1 , Yvon Cordier 1 , Nicolas Baron 1 2 , Sylvain Joblot 1 3 , Eric Frayssinet 1 , Jean-Christophe Moreno 1 3 , Jean Massies 1 Show Abstract
1 , CRHEA-CNRS, Valbonne France, 2 , Picogiga International, Courtaboeuf France, 3 , STMicroelectronics, Crolles France
AlGaN/GaN high electron mobility transistors (HEMTs) are of great interest due to their capabilities to work at high temperature and to achieve high output power densities. For these reasons they are expected to be used for next-generation of power amplifiers . AlGaN/GaN HEMTs are usually grown by metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE) on SiC substrates. Thanks to its high thermal conductivity SiC substrate helps to dissipate the huge output power generated by AlGaN/GaN devices. However in the last years several papers have reported impressive results for AlGaN/GaN HEMTs grown on Si(111) [2-5] suggesting that silicon substrates could offer an interesting alternative approach to develop low cost GaN-based high-power electronic devices.High electron mobility AlGaN/GaN heterostructures on silicon substrates grown by both MOVPE and MBE were firstly reported respectively, few years ago, by Schremer et al.  and Semond et al. . Since then a lot of efforts were made to understand and to improve quality of GaN layers grown on silicon and nowadays, AlGaN/GaN heterostructures on silicon substrates are as good as structures grown on SiC. As a figure of merit of such heterostructures, mobility values around 2000 cm2/Vs are now routinely obtained for AlGaN/GaN HEMTs grown on silicon substrates . Last but not least, still looking for potential integration of power electronics on advanced Si technology, recently efforts have been made to develop AlGaN/GaN HEMTs on Si(100) substrates and surprisingly very encouraging results have been obtained [9-10].This paper gives an overview of what has been achieved in the field of AlGaN/GaN HEMTs on Si substrates and we will discuss why it has been so successful to grow on Si. Recent developments as well as the latest state of the art AlGaN/GaN heterostructures grown on silicon substrates will be presented. K. Yamanaka et al., IEEE MTT-S Int. Microwave Symp., pp. 1251-1254 (2007) D. Ducatteau et al., IEEE Electron Device Lett., vol. 27(1), pp. 7-9 (2006) D.C. Dumka et al., Electron. Lett., vol 40(16), pp. 1023-1024 (2004) J.W. Johnson et al., IEEE Electron Device Lett., vol. 25(7), pp. 459-461 (2004) A. Minko et al., IEEE Electron Device Lett., vol. 25(7), pp. 453-455 (2004) A.T. Schremer et al., Appl. Phys. Lett. 76, 736 (2000) F. Semond et al., Appl. Phys. Lett. 78, 335 (2001) N. Baron et al., to be published S. Joblot et al., Electronics Letters 42, 117 (2006) S. Joblot et al., Superlattices and microstructures 40, 295-299 (2006)
10:45 AM - C4.5
Growth of AlGaN/GaN HEMTs on 3C-SiC/Si(111) Substrates.
Yvon Cordier 1 , Marc Portail 1 , Sebastien Chenot 1 , Olivier Tottereau 1 , Zielinsli Marcin 2 , Thierry Chassagne 2 Show Abstract
1 , CRHEA-CNRS, Valbonne France, 2 , NOVASIC, Le Bourget du Lac France
Cubic SiC/Si(111) substrate is an interesting alternative for growing GaN. As compared with silicon, this substrate allows reducing the stress in GaN films due to both lower lattice and thermal expansion coefficient mismatch, and can provide better heat dissipation. In this work, we first developed the epitaxial growth of 3C-SiC films on 50mm Si(111) substrates by hot wall CVD using propane and silane . Scanning electron microscopy shows coalesced flat films. X-ray diffraction confirms that the SiC films are grown following the  axis, with only one in-plane orientation. (002) reflections show width ranging from 0.3 to 0.5° depending on the thickness of the SiC films ranging from 0.8 to 2.5 µm. AlGaN/GaN HEMT heterostructures were subsequently grown by MBE using a growth process and layer sequence previously developed on bulk substrates . AFM surface roughness (about 5 nm) and dislocation density (<5E9 cm-2) are at least at the same level as the ones of layers grown on bulk substrates. Low temperature photoluminescence and X-ray diffraction confirm the GaN phase is wurtzite only, and show the presence of a noticeable residual compressive strain that allows avoiding any crack generation in GaN. Devices have been realized using a simple 3 level process. Device isolation is achieved using Cl2/Ar reactive ion etching. Ohmic contacts with a specific resistance of 0.8 ohm.mm are obtained after deposition annealing of Ti/Al/Ni/Au metals. Ni/Au sequence has been evaporated for Schottky gates and devices are not passivated. I-V and C-V measurements confirm that GaN buffer layers are highly resistive, whereas a 2D electron gas with a carrier density of 7E12 cm-2 and a mobility of 1500 cm2/V.s has been obtained for a structure with an Al content x=25% in the AlGaN barrier. For a transistor with a 3 µm x150 µm gate and source to drain spacing of 5 µm, the saturated drain current Idsmax is 338 mA/mm at Vgs=0V (450 mA/mm at Vgs=+1V) and the transconductance gm=125 mS/mm. These performances are close to the ones measured on similar devices realized on Si(111) substrates. The drain current at pinch-off (Vgs=-5V) is 15 µA/mm for Vds=10V. All of these characteristics attest the quality of the devices and make this a first step in the demonstration of the potentialities of the 3C-SiC/Si(111) substrate approach for the growth of high quality GaN based heterostructures on Silicon.  T. Chassagne, A. Leycuras, C. Balloud, P. Arcade, H. Peyre, and S. Juillaguet, Mat. Sci. Forum Vol. 457/460 (2004), p. 273 F.Semond, Y.Cordier, N.Grandjean, F.Natali, B.Damilano, S.Vezian and J.Massies, Phys. Stat. Sol. (a) 188, 501 (2001)
11:30 AM - C4.6
High-electron-mobility AlGaN/GaN Heterostructures Grown on Si(001) by Molecular Beam Epitaxy for Microwave Applications.
Sylvain Joblot 1 2 , Yvon Cordier 2 , Fabrice Semond 2 , Philippe Vennegues 2 , Sebastien Chenot 2 , Philippe Lorenzini 2 , Marc Portail 2 , Jean Claude Gerbedoen 3 , Ali Soltani 3 , Christophe Gaquiere 3 , Jean Claude De Jaeger 3 Show Abstract
1 , STMicroelectronics, Crolles France, 2 , CRHEA-CNRS, Valbonne, Sophia Antipolis, France, 3 , IEMN-CNRS, Villeneuve d'Ascq France
11:45 AM - C4.7
Effects of Carbon Doping on AlGaN/GaN HEMTs Grown on Si by Ammonia MBE.
Fabrice Semond 1 2 , Haipeng Tang 1 , Soufien Haffouz 1 , Stephen Rolfe 1 , Tim Lester 1 , Jennifer Bardwell 1 Show Abstract
1 , IMS-CNRC, Ottawa, Ontario, Canada, 2 , CRHEA-CNRS, Valbonne France
AlGaN/GaN high electron mobility transistors (HEMTs) are of great interest due to their capabilities to work at high temperature and to achieve high output power densities . A key issue in the fabrication of such heterostructures is the growth of a highly resistive GaN buffer layer which is mandatory to achieve complete pinch-off and to prevent any leakage that would be responsible for device degradation. Often, unintentionally doped (UID) GaN layers are n-type with a residual carrier concentration typically ranging from 5x1016- 5x1017 cm-3 which is too high to fabricate practical GaN-based HEMTs. In contrast, good-quality UID GaN layers grown on Si substrates exhibit a much lower background carrier concentration, typically in the range 1x1014- 5x1015 cm-3 [2-4], which is one of the reasons why it is so reliable and so reproducible to fabricate AlGaN/GaN HEMTs on silicon. The reason why GaN buffer layers grown on Si are highly resistive is still unclear. Of course compensation mechanisms by deep acceptor states are likely responsible but the exact nature of acceptor states is still unexplained. HEMTs using such UID GaN buffer layers grown on Si have demonstrated amazing performance [5-8], but it would be preferable to have a better understanding and/or better control of the insulating properties of GaN buffer layers grown on silicon. As an example, it was recently demonstrated that the use of Fe-doped GaN buffer helps to achieve stable and more robust breakdown characteristics for AlGaN/GaN HEMTs grown on Si . Ammonia-MBE has been very successful to grow AlGaN/GaN HEMTs on Si [2-8]. On the other hand an original and efficient method of growing semi-insulating GaN epilayers through intentional carbon doping has also been demonstrated using ammonia-MBE . In this paper we investigate the effects of carbon-doped GaN buffer layer on the properties of AlGaN/GaN HEMTs grown on Si substrates by ammonia-MBE combining the two well-established processes. In order to study the effects of C-doping, HEMT heterostructures and devices with C-doped GaN buffer on Si substrates are grown and fabricated along with conventional structures utilizing an UID doped GaN buffer on Si. Then material properties and device characteristics are compared. K. Yamanaka et al., IEEE MTT-S Int. Microwave Symp., pp. 1251-1254 (2007) F. Semond et al., Appl. Phys. Lett. 78, 335 (2001) F. Semond et al., Phys. Stat. Solidi (a) 188, 501 (2001) Y. Cordier et al., Electron. Lett., vol 38(2), pp. 91-92 (2002) D. Ducatteau et al., IEEE Electron Device Lett., vol. 27(1), pp. 7-9 (2006) D.C. Dumka et al., Electron. Lett., vol 40(16), pp. 1023-1024 (2004) J.W. Johnson et al., IEEE Electron Device Lett., vol. 25(7), pp. 459-461 (2004) A. Minko et al., IEEE Electron Device Lett., vol. 25(7), pp. 453-455 (2004) Y.C. Choi et al., IEEE trans. Electron Devices, vol. 53, pp. 2926-2931 (2006) J.B. Webb et al., Appl. Phys. Lett. 75, 953 (1999)
12:00 PM - **C4.8
GaN Electrochemical Probes and MEMS on Si.
Ulrich Heinle 1 , Peter Benkart 1 , Ingo Daumiller 1 , Mike Kunze 1 , Ertugrul Sonmez 1 Show Abstract
1 , microGaN GmbH, Ulm Germany
12:30 PM - C4.9
Adding Diamond to GaN on Silicon Devices.
Jerry Zimmer 1 Show Abstract
1 , sp3 Diamond Technologies, Santa Clara, California, United States
Wednesday, March 26New Presentation Time/Paper NumberC4.9 @ 11:45 AM to C4.10 @ 11:30 AMAdding Diamond to GaN on Silicon Devices. Jerry W. Zimmer