Oxides have always been an integral part of semiconductor manufacturing both in front and back-end processing. With the necessary increase in performances, the demand on these oxide has been increasing leading to their (future) replacement by more complex materials, such as high-k’s in gate oxide and low-k’s in interconnects. With the material complexity, a thorough characterization of all aspects of these materials is necessary, covering, for instance, surfaces and interfaces, nucleation, growth, atomic structure, …. This presentation will mainly focus on the characterization of front-end oxides and their interfaces. We will first focus on the determination of substrate surface preparation conditions before deposition ad their influence on growth mode, including the influence of the growth technique (ALD, MOCVD, MBE, …). Second, we will cover the measurement of film thickness and density before covering the difficulties to achieve composition depth profiling with the necessary depth resolution. Finally, we will cover the characterization of electronic properties, such as band-gap and band-offset. A wide range analysis technique will be covered in this presentation, including XPS, ARXPS, RBS, (TOF)-SIMS, ERD, TEM, … and will consider advantages/disadvantages of the different approaches. We will also emphasize the need to use special sample preparation technique (such as back-side measurement) in order to study phenomena such as metal/oxide interaction and metal in-diffusion in Si

As silicon dioxide gate dialectic thickness for CMOS devices continues scaling down to a few monolayers, the hafnium oxide and other high-k dielectrics have drawn considerable interest in recent years. The characterization of these materials is crucial to understand the fundamental knowledge in order to develop optimum dielectrics for future devices. Even though, the high-k dielectric materials on semiconductor had been extensively studied by performing capacitance-voltage (C-V) measurements, there are little has been reported on C-V measurement under influence of controlled photon energy. We report the characterization technique, which is done by measuring variable frequency C-V curves of metal-oxide-semiconductor (MOS) capacitors under influence of specific photon wavelength ranging from UV to near IR. The experimental setup includes a 150 Watt broadband xenon light source with a grating monochromator to provide spectral range of 1.5 eV to 6.0 eV. The single wavelength light from monochromator is collimated by an achromatic lens and then focused down by another achromatic lens on a metal electrode of a MOS device. The multi-frequency C-V measurements are taken by precision LCR meter as the light is scanned at different incident photon energies. The metal electrodes of MOS devices are fabricated by depositing semitransparent metal pads on top of dielectric layer to allow photon energy penetration into dielectric and semiconductor regions. The range of an active area of MOS capacitors is from 10^-8 cm² to 4×10^-4 cm². Different types of metal were used for gate metal, such as Au, Al, W, TaN/TaSiN and TaN/TaCN. The dielectrics used in this study include SiO₂ on Si and HfO₂ on Si and GaAs substrates. A large amount of data taken on both the traditional SiO₂ dielectrics and technologically relevant HfO₂ dielectrics reveal significant changes in C-V characteristics at different incident photon energies. How these changes relate to the defects in the oxide are still under further investigations. However, the preliminary results show clear and reproducible C-V responses to the presence of photon incidence. It is observed that flatband voltage shifts differently at different photon energies. Such shifts might be induced by the presence of interface traps, bulk charges, and interface defect states when they are photocharged by the photon energy. We will show quantitative flatband modification and its dependency on the photon energy. A physical and electrical explanation will be provided for the causes of the flatband voltage shift. Furthermore, it is suspected that internal photoemission of both electrons and holes under the influence of light with the energy higher then interface barrier heights affect the C-V responses of the devices. In conclusion, this characterization technique show potential new sources of information about the electronic interface and bulk properties of dielectrics in MOS devices.

Colossal dielectric constant in CaCu3Ti4O12 (CCTO) has attracted many research interests. However, the origin of this phenomenon has not been completely disclosed even though many people gradually believe it was caused by the Maxwell-Wagner effect due to the semiconducting nature of the grains. CCTO thin films deposited on polycrystalline, textured Pt electrodes show columnar growth, which provides a good research object to investigate the nature of CDC in this material because series junctions of grain boundaries can be ruled out in this case. Similar to bulk material, the high “apparent” dielectric constant can be observed in the as-deposited thin film by pulsed laser deposition (PLD). The thermal activation energy from the low temperature relaxation is derived as 86meV, quite agreeable with the reported value in single crystals. Parallel plate thin film capacitors were investigated by virtue of the methods applied for semiconductor junctions. We observed a strong dependence of the capacitance on the bias voltage at the reverse direction. C^-2-V curve showed a typical linear relationship, as observed in the case of Metal-Semiconductor (MS) and Metal-Insulator-Semiconductor (MIS) junctions in semiconductors. I-V curves show typical diode behavior. After treated in HCl acid, these electrical properties became more sensitive to the biased voltages. The observed I-V and C^-2-V results in the as-deposited and acid-treated CCTO thin film samples strongly suggested that there was a thin insulating layer at the top electrode/thin film interface, where the MIS junction came into form. Defect density and interface band bending could be derived according to established theories on MIS structures, amounting to approximately 10^19cm^-3 and 0.5~0.8eV, respectively. These values are consistent with grain boundary barriers in CCTO ceramics. Accordingly, the capacitance response of such a MIS junction explained the observed high “apparent” dielectric constant in this material. Hall measurements revealed p-type conductivity ceramics as well in thin films deposited by PLD. Therefore, the semiconducting properties of CCTO should be attributed to acceptor defects, possibly related to valence changes of copper or titanium ions.

In the recent research on higk-k gate stacks, we encountered unusual behaviors of the Schottky barrier (effective workfunction of metals; WF) that have never been observed in our device history and are never explained by the conventional concepts of the WF. What occurs at metal/high-k interfaces ? In this talk, we facus on the following three important topics and explain the mechanisms of unusual WF behaviors at these interfaces, reviewing recent relevant studies and showing our recent theoretical results. Especially, we will show that the large ionicity of high-k materials is the key to elucidate not only these WF variations but also the stability of metal/high-k interfaces. The fundamental understanding of such features will work as new guiding principles and activate advanced designs of future devices. (1) When the metal/high-k interfaces are fabricated at low temperature below a few hundred C, the WFs of p-metals such as Au increase, while those of n-metals such as Al decrease. These changes (S>1, S=WF slope parameter) are entirely opposite to the predictions of the conventional charge-neutrality theories of Schottky barrier (1>S>0), which we believed to use as a guiding principle to design the WF. We show that such unusual variation of intrinsic Schottky barriers is caused by the selective atom coupling and the orbital hybridization at the interface, thus being a natural behavior rather than an anomalous behavior. (See ECS transactions, 3(2006) 129) (2) When the interfaces are exposed to high-temperature annealing, the WFs of n-metals keep the original low-temperature positions, while those of p-metals largely decrease and are fixed at a certain energy position (S=0), which phenomena is often called the Fermi-level pinning (FLP). We show that the FLP is caused by the production of oxygen vacancies in high-k around high-k/Si interface and the charge transfer from such oxygen vacancies to metal layers. (3) When ultrathin metal layers are formed as "ointments" at the interface by the epitaxial deposition or the segregation, the WF often shows remarkable changes. For example, the Al layer insertion into Au/HfO2 interfaces changes the effective Au WF from p-metal-like to n-metal-like one. We show that the charge transfer across such ultrathin layers is the main origin for the WF modulation, which microscopic understanding leads to develop the future techniques such as for the metal-source/drain application.// This work is partly supported by a Grand-in-Aid for Scientific Research No. 18360017, 18083003, and 17540291 by MEXT, Japan. Calculations are done at Computer Center of Chiba University and Institute for Solid State Physics, University of Tokyo.

Germanium is of growing importance in research for ultimately-scaled high speed field effect transistors due to its high intrinsic carrier mobilities. Formation of an interfacial layer with low defect density between a Ge channel and high-k gate dielectrics is one of the most important issues in preparing Ge MOS devices. In this work, we focus on interface reactions which occur during post-dielectric deposition treatments and their relationship to interface properties. Donor-doped Ge(100) wafers were loaded into ALD system with ICP remote plasma source immediately after DHF/DI water wet cleaning to avoid oxidation. Nitridation of the Ge (100) surface was done using H2/N2/Ar remote plasma at 435°C and GeOxNy films which have good thermal stability and resistance to aqueous etching were obtained. After GeOxNy formation, HfO2 was deposited at 150 °C using tetradiethylaminohafnium (TDEAH) and H2O by atomic layer deposition without exposure to air. Capacitance-voltage (CV) measurements at low temperature (77K-250K) revealed forming gas annealed (FGA) sample has a substantially lower density of interface trapped charge, Dit (~1012 cm-2eV-1) than does the high vacuum annealed (HVA) sample (>1013 cm-2eV-1). To probe differences in electrical properties, synchrotron radiation photoelectron spectroscopy (SRPES) was performed on HfO2 (~4 nm)/GeOxNy (~1.5 nm)/Ge stack. After FGA, Ge 3d peak which shifts 3.3 eV higher than bulk Ge (Ge0) appeared clearly. On the other hand, after HVA, Ge 3d peak appeared but has a lower binding energy shift (~2.3eV) than for the FGA sample. These binding energy shifts are considered to correspond to Ge4+(3.4 eV) and a mixture of Ge3+(1.8 eV) and Ge2+(2.6 eV) binding states. It is interesting that the FGA sample, which has a higher Ge binding energy shift, also has lower Dit. These results indicate that an interface with Ge3N4 or GeO2-like bonding has fewer defects than a suboxide-like Ge interface layer, and that control of Ge chemical states at the high-k/Ge interface is important to achieve lower Dit.

Wednesday, March 26Transfer H5.9 @ 4:45 PM to H5.8 @ 4:30 PMAbrupt Metal-Oxide/Semiconductor Interfaces through Adsorption and Reaction of HfCl4 with H2O-terminated Si(100)-2x1. Brian G. Willis