Two-dimensional layered materials have many useful properties that may be useful for future high-performance, energy efficient computing systems technology. Semiconducting 2D layered materials such as MoS2 and black phosphorous (BP) have shown promise as transistor channel materials. I will present our results on making low-resistance electrical contacts to these materials [1, 2]. Graphene, a semi-metal, has very useful properties that makes it particularly suited for extending the use of copper as interconnect wires. These useful properties include serving as a highly effective copper diffusion barrier (thus replacing TaN as the copper liner), and providing enhanced electromigration immunity for a graphene/Cu composite with graphene cladding the copper wire. We will present recent experimental results on these two very promising applications of graphene to complement copper wires [3, 4]. We have also developed a system-level modeling framework that allows us to benchmark the speed performance and energy efficiency of a microprocessor, including contributions from parasitics and wiring interconnects using industry-standard place-and-route optimization tools coupled with compact device models. We will present results that compare 5-nm FinFET CMOS with MoS2 and BP transistors, as well as various wiring options including multilayer graphene and graphene cladded Cu wires .
Acknowledgements: Supported in part by member companies of the Stanford Initiative for Nanoscale Materials and Processes (INMP), member companies of the Stanford SystemX Alliance, the National Science Foundation (EFRI 2-DARE: Energy Efficient Electronics with Atomic Layers (E3AL), Award Abstract #1542883), and also in part by Systems on Nanoscale Information fabriCs (SONIC) and Function Accelerated NanoMaterials Engineering (FAME) Center, two of the six SRC STARnet Centers, sponsored by MARCO and DARPA.
 S. Lee, A. Tang, S. Aloni, H.-S. P. Wong, “Statistical Study on the Schottky Barrier Reduction of Tunneling Contacts to CVD Synthesized MoS2,” Nano Lett., 16 (1), pp 276–281 (2016).
 L. Li, M. Engel, D. B. Farmer, S.-J. Han, H.-S. P. Wong, “High Performance p-Type Black Phosphorus Transistor with Scandium Contact,” ACS Nano, 10 (4), pp 4672–4677 (2016).
 L. Li, X. Chen, C.-H. Wang, J. Cao, S. Lee, A. Tang, C. Ahn, S. S. Roy, M. S. Arnold, and H.-S. P. Wong, “Vertical and Lateral Copper Transport through Graphene Layers,” ACS Nano, 2015, 9 (8), pp 8361–8367.
 L. Li, Z. Zhu, T. Wang, J.A. Currivan-Incorvia, A. Yoon, and H.-S. P. Wong, “BEOL Compatible Graphene/Cu with Improved Electromigration Lifetime for Future Interconnects,” IEEE International Electron Devices Meeting (IEDM), paper 9.5, 2016.
 C.-S. Lee, B. Cline, S. Sinha, G. Yeric, and H.-S. P. Wong, “32-bit Processor Core at 5-nm Technology: Analysis of Transistor and Interconnect Impact on VLSI System Performance,” IEEE International Electron Devices Meeting (IEDM), paper 28.3, 2016.